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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / isdn / hisax / avm_pci.c
blobb04a178e502102e96270963a1028e22c7c5cae83
1 /* $Id: avm_pci.c,v 1.29.2.4 2004/02/11 13:21:32 keil Exp $
2 *
3 * low level stuff for AVM Fritz!PCI and ISA PnP isdn cards
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 * Thanks to AVM, Berlin for information
12 *
13 */
14
15 #include <linux/init.h>
16 #include "hisax.h"
17 #include "isac.h"
18 #include "isdnl1.h"
19 #include <linux/pci.h>
20 #include <linux/isapnp.h>
21 #include <linux/interrupt.h>
22
23 extern const char *CardType[];
24 static const char *avm_pci_rev = "$Revision: 1.29.2.4 $";
25
26 #define AVM_FRITZ_PCI 1
27 #define AVM_FRITZ_PNP 2
28
29 #define HDLC_FIFO 0x0
30 #define HDLC_STATUS 0x4
31
32 #define AVM_HDLC_1 0x00
33 #define AVM_HDLC_2 0x01
34 #define AVM_ISAC_FIFO 0x02
35 #define AVM_ISAC_REG_LOW 0x04
36 #define AVM_ISAC_REG_HIGH 0x06
37
38 #define AVM_STATUS0_IRQ_ISAC 0x01
39 #define AVM_STATUS0_IRQ_HDLC 0x02
40 #define AVM_STATUS0_IRQ_TIMER 0x04
41 #define AVM_STATUS0_IRQ_MASK 0x07
42
43 #define AVM_STATUS0_RESET 0x01
44 #define AVM_STATUS0_DIS_TIMER 0x02
45 #define AVM_STATUS0_RES_TIMER 0x04
46 #define AVM_STATUS0_ENA_IRQ 0x08
47 #define AVM_STATUS0_TESTBIT 0x10
48
49 #define AVM_STATUS1_INT_SEL 0x0f
50 #define AVM_STATUS1_ENA_IOM 0x80
51
52 #define HDLC_MODE_ITF_FLG 0x01
53 #define HDLC_MODE_TRANS 0x02
54 #define HDLC_MODE_CCR_7 0x04
55 #define HDLC_MODE_CCR_16 0x08
56 #define HDLC_MODE_TESTLOOP 0x80
57
58 #define HDLC_INT_XPR 0x80
59 #define HDLC_INT_XDU 0x40
60 #define HDLC_INT_RPR 0x20
61 #define HDLC_INT_MASK 0xE0
62
63 #define HDLC_STAT_RME 0x01
64 #define HDLC_STAT_RDO 0x10
65 #define HDLC_STAT_CRCVFRRAB 0x0E
66 #define HDLC_STAT_CRCVFR 0x06
67 #define HDLC_STAT_RML_MASK 0x3f00
68
69 #define HDLC_CMD_XRS 0x80
70 #define HDLC_CMD_XME 0x01
71 #define HDLC_CMD_RRS 0x20
72 #define HDLC_CMD_XML_MASK 0x3f00
73
74
75 /* Interface functions */
76
77 static u_char
78 ReadISAC(struct IsdnCardState *cs, u_char offset)
79 {
80 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
81 register u_char val;
82
83 outb(idx, cs->hw.avm.cfg_reg + 4);
84 val = inb(cs->hw.avm.isac + (offset & 0xf));
85 return (val);
86 }
87
88 static void
89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
90 {
91 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
92
93 outb(idx, cs->hw.avm.cfg_reg + 4);
94 outb(value, cs->hw.avm.isac + (offset & 0xf));
95 }
96
97 static void
98 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
99 {
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
101 insb(cs->hw.avm.isac, data, size);
102 }
103
104 static void
105 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
106 {
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
108 outsb(cs->hw.avm.isac, data, size);
109 }
110
111 static inline u_int
112 ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset)
113 {
114 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
115 register u_int val;
116
117 outl(idx, cs->hw.avm.cfg_reg + 4);
118 val = inl(cs->hw.avm.isac + offset);
119 return (val);
120 }
121
122 static inline void
123 WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value)
124 {
125 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
126
127 outl(idx, cs->hw.avm.cfg_reg + 4);
128 outl(value, cs->hw.avm.isac + offset);
129 }
130
131 static inline u_char
132 ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset)
133 {
134 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
135 register u_char val;
136
137 outb(idx, cs->hw.avm.cfg_reg + 4);
138 val = inb(cs->hw.avm.isac + offset);
139 return (val);
140 }
141
142 static inline void
143 WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
144 {
145 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
146
147 outb(idx, cs->hw.avm.cfg_reg + 4);
148 outb(value, cs->hw.avm.isac + offset);
149 }
150
151 static u_char
152 ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset)
153 {
154 return(0xff & ReadHDLCPCI(cs, chan, offset));
155 }
156
157 static void
158 WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
159 {
160 WriteHDLCPCI(cs, chan, offset, value);
161 }
162
163 static inline
164 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
165 {
166 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
167 return(&cs->bcs[0]);
168 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
169 return(&cs->bcs[1]);
170 else
171 return(NULL);
172 }
173
174 static void
175 write_ctrl(struct BCState *bcs, int which) {
176
177 if (bcs->cs->debug & L1_DEB_HSCX)
178 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
179 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
180 if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
182 } else {
183 if (which & 4)
184 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
185 bcs->hw.hdlc.ctrl.sr.mode);
186 if (which & 2)
187 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
188 bcs->hw.hdlc.ctrl.sr.xml);
189 if (which & 1)
190 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
191 bcs->hw.hdlc.ctrl.sr.cmd);
192 }
193 }
194
195 static void
196 modehdlc(struct BCState *bcs, int mode, int bc)
197 {
198 struct IsdnCardState *cs = bcs->cs;
199 int hdlc = bcs->channel;
200
201 if (cs->debug & L1_DEB_HSCX)
202 debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d",
203 'A' + hdlc, bcs->mode, mode, hdlc, bc);
204 bcs->hw.hdlc.ctrl.ctrl = 0;
205 switch (mode) {
206 case (-1): /* used for init */
207 bcs->mode = 1;
208 bcs->channel = bc;
209 bc = 0;
210 case (L1_MODE_NULL):
211 if (bcs->mode == L1_MODE_NULL)
212 return;
213 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
214 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
215 write_ctrl(bcs, 5);
216 bcs->mode = L1_MODE_NULL;
217 bcs->channel = bc;
218 break;
219 case (L1_MODE_TRANS):
220 bcs->mode = mode;
221 bcs->channel = bc;
222 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
223 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
224 write_ctrl(bcs, 5);
225 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
226 write_ctrl(bcs, 1);
227 bcs->hw.hdlc.ctrl.sr.cmd = 0;
228 schedule_event(bcs, B_XMTBUFREADY);
229 break;
230 case (L1_MODE_HDLC):
231 bcs->mode = mode;
232 bcs->channel = bc;
233 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
234 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
235 write_ctrl(bcs, 5);
236 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
237 write_ctrl(bcs, 1);
238 bcs->hw.hdlc.ctrl.sr.cmd = 0;
239 schedule_event(bcs, B_XMTBUFREADY);
240 break;
241 }
242 }
243
244 static inline void
245 hdlc_empty_fifo(struct BCState *bcs, int count)
246 {
247 register u_int *ptr;
248 u_char *p;
249 u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
250 int cnt=0;
251 struct IsdnCardState *cs = bcs->cs;
252
253 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
254 debugl1(cs, "hdlc_empty_fifo %d", count);
255 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
256 if (cs->debug & L1_DEB_WARN)
257 debugl1(cs, "hdlc_empty_fifo: incoming packet too large");
258 return;
259 }
260 p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
261 ptr = (u_int *)p;
262 bcs->hw.hdlc.rcvidx += count;
263 if (cs->subtyp == AVM_FRITZ_PCI) {
264 outl(idx, cs->hw.avm.cfg_reg + 4);
265 while (cnt < count) {
266 #ifdef __powerpc__
267 #ifdef CONFIG_APUS
268 *ptr++ = in_le32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
269 #else
270 *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
271 #endif /* CONFIG_APUS */
272 #else
273 *ptr++ = inl(cs->hw.avm.isac);
274 #endif /* __powerpc__ */
275 cnt += 4;
276 }
277 } else {
278 outb(idx, cs->hw.avm.cfg_reg + 4);
279 while (cnt < count) {
280 *p++ = inb(cs->hw.avm.isac);
281 cnt++;
282 }
283 }
284 if (cs->debug & L1_DEB_HSCX_FIFO) {
285 char *t = bcs->blog;
286
287 if (cs->subtyp == AVM_FRITZ_PNP)
288 p = (u_char *) ptr;
289 t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
290 bcs->channel ? 'B' : 'A', count);
291 QuickHex(t, p, count);
292 debugl1(cs, bcs->blog);
293 }
294 }
295
296 static inline void
297 hdlc_fill_fifo(struct BCState *bcs)
298 {
299 struct IsdnCardState *cs = bcs->cs;
300 int count, cnt =0;
301 int fifo_size = 32;
302 u_char *p;
303 u_int *ptr;
304
305 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
306 debugl1(cs, "hdlc_fill_fifo");
307 if (!bcs->tx_skb)
308 return;
309 if (bcs->tx_skb->len <= 0)
310 return;
311
312 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
313 if (bcs->tx_skb->len > fifo_size) {
314 count = fifo_size;
315 } else {
316 count = bcs->tx_skb->len;
317 if (bcs->mode != L1_MODE_TRANS)
318 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
319 }
320 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
321 debugl1(cs, "hdlc_fill_fifo %d/%ld", count, bcs->tx_skb->len);
322 p = bcs->tx_skb->data;
323 ptr = (u_int *)p;
324 skb_pull(bcs->tx_skb, count);
325 bcs->tx_cnt -= count;
326 bcs->hw.hdlc.count += count;
327 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
328 write_ctrl(bcs, 3); /* sets the correct index too */
329 if (cs->subtyp == AVM_FRITZ_PCI) {
330 while (cnt<count) {
331 #ifdef __powerpc__
332 #ifdef CONFIG_APUS
333 out_le32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
334 #else
335 out_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
336 #endif /* CONFIG_APUS */
337 #else
338 outl(*ptr++, cs->hw.avm.isac);
339 #endif /* __powerpc__ */
340 cnt += 4;
341 }
342 } else {
343 while (cnt<count) {
344 outb(*p++, cs->hw.avm.isac);
345 cnt++;
346 }
347 }
348 if (cs->debug & L1_DEB_HSCX_FIFO) {
349 char *t = bcs->blog;
350
351 if (cs->subtyp == AVM_FRITZ_PNP)
352 p = (u_char *) ptr;
353 t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
354 bcs->channel ? 'B' : 'A', count);
355 QuickHex(t, p, count);
356 debugl1(cs, bcs->blog);
357 }
358 }
359
360 static void
361 HDLC_irq(struct BCState *bcs, u_int stat) {
362 int len;
363 struct sk_buff *skb;
364
365 if (bcs->cs->debug & L1_DEB_HSCX)
366 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
367 if (stat & HDLC_INT_RPR) {
368 if (stat & HDLC_STAT_RDO) {
369 if (bcs->cs->debug & L1_DEB_HSCX)
370 debugl1(bcs->cs, "RDO");
371 else
372 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
373 bcs->hw.hdlc.ctrl.sr.xml = 0;
374 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
375 write_ctrl(bcs, 1);
376 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
377 write_ctrl(bcs, 1);
378 bcs->hw.hdlc.rcvidx = 0;
379 } else {
380 if (!(len = (stat & HDLC_STAT_RML_MASK)>>8))
381 len = 32;
382 hdlc_empty_fifo(bcs, len);
383 if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
384 if (((stat & HDLC_STAT_CRCVFRRAB)==HDLC_STAT_CRCVFR) ||
385 (bcs->mode == L1_MODE_TRANS)) {
386 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
387 printk(KERN_WARNING "HDLC: receive out of memory\n");
388 else {
389 memcpy(skb_put(skb, bcs->hw.hdlc.rcvidx),
390 bcs->hw.hdlc.rcvbuf, bcs->hw.hdlc.rcvidx);
391 skb_queue_tail(&bcs->rqueue, skb);
392 }
393 bcs->hw.hdlc.rcvidx = 0;
394 schedule_event(bcs, B_RCVBUFREADY);
395 } else {
396 if (bcs->cs->debug & L1_DEB_HSCX)
397 debugl1(bcs->cs, "invalid frame");
398 else
399 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
400 bcs->hw.hdlc.rcvidx = 0;
401 }
402 }
403 }
404 }
405 if (stat & HDLC_INT_XDU) {
406 /* Here we lost an TX interrupt, so
407 * restart transmitting the whole frame.
408 */
409 if (bcs->tx_skb) {
410 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
411 bcs->tx_cnt += bcs->hw.hdlc.count;
412 bcs->hw.hdlc.count = 0;
413 if (bcs->cs->debug & L1_DEB_WARN)
414 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
415 } else if (bcs->cs->debug & L1_DEB_WARN)
416 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
417 bcs->hw.hdlc.ctrl.sr.xml = 0;
418 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
419 write_ctrl(bcs, 1);
420 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
421 write_ctrl(bcs, 1);
422 hdlc_fill_fifo(bcs);
423 } else if (stat & HDLC_INT_XPR) {
424 if (bcs->tx_skb) {
425 if (bcs->tx_skb->len) {
426 hdlc_fill_fifo(bcs);
427 return;
428 } else {
429 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
430 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
431 u_long flags;
432 spin_lock_irqsave(&bcs->aclock, flags);
433 bcs->ackcnt += bcs->hw.hdlc.count;
434 spin_unlock_irqrestore(&bcs->aclock, flags);
435 schedule_event(bcs, B_ACKPENDING);
436 }
437 dev_kfree_skb_irq(bcs->tx_skb);
438 bcs->hw.hdlc.count = 0;
439 bcs->tx_skb = NULL;
440 }
441 }
442 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
443 bcs->hw.hdlc.count = 0;
444 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
445 hdlc_fill_fifo(bcs);
446 } else {
447 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
448 schedule_event(bcs, B_XMTBUFREADY);
449 }
450 }
451 }
452
453 static inline void
454 HDLC_irq_main(struct IsdnCardState *cs)
455 {
456 u_int stat;
457 struct BCState *bcs;
458
459 if (cs->subtyp == AVM_FRITZ_PCI) {
460 stat = ReadHDLCPCI(cs, 0, HDLC_STATUS);
461 } else {
462 stat = ReadHDLCPnP(cs, 0, HDLC_STATUS);
463 if (stat & HDLC_INT_RPR)
464 stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS+1))<<8;
465 }
466 if (stat & HDLC_INT_MASK) {
467 if (!(bcs = Sel_BCS(cs, 0))) {
468 if (cs->debug)
469 debugl1(cs, "hdlc spurious channel 0 IRQ");
470 } else
471 HDLC_irq(bcs, stat);
472 }
473 if (cs->subtyp == AVM_FRITZ_PCI) {
474 stat = ReadHDLCPCI(cs, 1, HDLC_STATUS);
475 } else {
476 stat = ReadHDLCPnP(cs, 1, HDLC_STATUS);
477 if (stat & HDLC_INT_RPR)
478 stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS+1))<<8;
479 }
480 if (stat & HDLC_INT_MASK) {
481 if (!(bcs = Sel_BCS(cs, 1))) {
482 if (cs->debug)
483 debugl1(cs, "hdlc spurious channel 1 IRQ");
484 } else
485 HDLC_irq(bcs, stat);
486 }
487 }
488
489 static void
490 hdlc_l2l1(struct PStack *st, int pr, void *arg)
491 {
492 struct BCState *bcs = st->l1.bcs;
493 struct sk_buff *skb = arg;
494 u_long flags;
495
496 switch (pr) {
497 case (PH_DATA | REQUEST):
498 spin_lock_irqsave(&bcs->cs->lock, flags);
499 if (bcs->tx_skb) {
500 skb_queue_tail(&bcs->squeue, skb);
501 } else {
502 bcs->tx_skb = skb;
503 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
504 bcs->hw.hdlc.count = 0;
505 bcs->cs->BC_Send_Data(bcs);
506 }
507 spin_unlock_irqrestore(&bcs->cs->lock, flags);
508 break;
509 case (PH_PULL | INDICATION):
510 spin_lock_irqsave(&bcs->cs->lock, flags);
511 if (bcs->tx_skb) {
512 printk(KERN_WARNING "hdlc_l2l1: this shouldn't happen\n");
513 } else {
514 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
515 bcs->tx_skb = skb;
516 bcs->hw.hdlc.count = 0;
517 bcs->cs->BC_Send_Data(bcs);
518 }
519 spin_unlock_irqrestore(&bcs->cs->lock, flags);
520 break;
521 case (PH_PULL | REQUEST):
522 if (!bcs->tx_skb) {
523 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
524 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
525 } else
526 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
527 break;
528 case (PH_ACTIVATE | REQUEST):
529 spin_lock_irqsave(&bcs->cs->lock, flags);
530 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
531 modehdlc(bcs, st->l1.mode, st->l1.bc);
532 spin_unlock_irqrestore(&bcs->cs->lock, flags);
533 l1_msg_b(st, pr, arg);
534 break;
535 case (PH_DEACTIVATE | REQUEST):
536 l1_msg_b(st, pr, arg);
537 break;
538 case (PH_DEACTIVATE | CONFIRM):
539 spin_lock_irqsave(&bcs->cs->lock, flags);
540 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
541 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
542 modehdlc(bcs, 0, st->l1.bc);
543 spin_unlock_irqrestore(&bcs->cs->lock, flags);
544 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
545 break;
546 }
547 }
548
549 static void
550 close_hdlcstate(struct BCState *bcs)
551 {
552 modehdlc(bcs, 0, 0);
553 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
554 kfree(bcs->hw.hdlc.rcvbuf);
555 bcs->hw.hdlc.rcvbuf = NULL;
556 kfree(bcs->blog);
557 bcs->blog = NULL;
558 skb_queue_purge(&bcs->rqueue);
559 skb_queue_purge(&bcs->squeue);
560 if (bcs->tx_skb) {
561 dev_kfree_skb_any(bcs->tx_skb);
562 bcs->tx_skb = NULL;
563 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
564 }
565 }
566 }
567
568 static int
569 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
570 {
571 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
572 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
573 printk(KERN_WARNING
574 "HiSax: No memory for hdlc.rcvbuf\n");
575 return (1);
576 }
577 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
578 printk(KERN_WARNING
579 "HiSax: No memory for bcs->blog\n");
580 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
581 kfree(bcs->hw.hdlc.rcvbuf);
582 bcs->hw.hdlc.rcvbuf = NULL;
583 return (2);
584 }
585 skb_queue_head_init(&bcs->rqueue);
586 skb_queue_head_init(&bcs->squeue);
587 }
588 bcs->tx_skb = NULL;
589 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
590 bcs->event = 0;
591 bcs->hw.hdlc.rcvidx = 0;
592 bcs->tx_cnt = 0;
593 return (0);
594 }
595
596 static int
597 setstack_hdlc(struct PStack *st, struct BCState *bcs)
598 {
599 bcs->channel = st->l1.bc;
600 if (open_hdlcstate(st->l1.hardware, bcs))
601 return (-1);
602 st->l1.bcs = bcs;
603 st->l2.l2l1 = hdlc_l2l1;
604 setstack_manager(st);
605 bcs->st = st;
606 setstack_l1_B(st);
607 return (0);
608 }
609
610 #if 0
611 void __init
612 clear_pending_hdlc_ints(struct IsdnCardState *cs)
613 {
614 u_int val;
615
616 if (cs->subtyp == AVM_FRITZ_PCI) {
617 val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
618 debugl1(cs, "HDLC 1 STA %x", val);
619 val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
620 debugl1(cs, "HDLC 2 STA %x", val);
621 } else {
622 val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
623 debugl1(cs, "HDLC 1 STA %x", val);
624 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
625 debugl1(cs, "HDLC 1 RML %x", val);
626 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
627 debugl1(cs, "HDLC 1 MODE %x", val);
628 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
629 debugl1(cs, "HDLC 1 VIN %x", val);
630 val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
631 debugl1(cs, "HDLC 2 STA %x", val);
632 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
633 debugl1(cs, "HDLC 2 RML %x", val);
634 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
635 debugl1(cs, "HDLC 2 MODE %x", val);
636 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
637 debugl1(cs, "HDLC 2 VIN %x", val);
638 }
639 }
640 #endif /* 0 */
641
642 static void
643 inithdlc(struct IsdnCardState *cs)
644 {
645 cs->bcs[0].BC_SetStack = setstack_hdlc;
646 cs->bcs[1].BC_SetStack = setstack_hdlc;
647 cs->bcs[0].BC_Close = close_hdlcstate;
648 cs->bcs[1].BC_Close = close_hdlcstate;
649 modehdlc(cs->bcs, -1, 0);
650 modehdlc(cs->bcs + 1, -1, 1);
651 }
652
653 static irqreturn_t
654 avm_pcipnp_interrupt(int intno, void *dev_id)
655 {
656 struct IsdnCardState *cs = dev_id;
657 u_long flags;
658 u_char val;
659 u_char sval;
660
661 spin_lock_irqsave(&cs->lock, flags);
662 sval = inb(cs->hw.avm.cfg_reg + 2);
663 if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) {
664 /* possible a shared IRQ reqest */
665 spin_unlock_irqrestore(&cs->lock, flags);
666 return IRQ_NONE;
667 }
668 if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
669 val = ReadISAC(cs, ISAC_ISTA);
670 isac_interrupt(cs, val);
671 }
672 if (!(sval & AVM_STATUS0_IRQ_HDLC)) {
673 HDLC_irq_main(cs);
674 }
675 WriteISAC(cs, ISAC_MASK, 0xFF);
676 WriteISAC(cs, ISAC_MASK, 0x0);
677 spin_unlock_irqrestore(&cs->lock, flags);
678 return IRQ_HANDLED;
679 }
680
681 static void
682 reset_avmpcipnp(struct IsdnCardState *cs)
683 {
684 printk(KERN_INFO "AVM PCI/PnP: reset\n");
685 outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
686 mdelay(10);
687 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
688 outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
689 mdelay(10);
690 printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
691 }
692
693 static int
694 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
695 {
696 u_long flags;
697
698 switch (mt) {
699 case CARD_RESET:
700 spin_lock_irqsave(&cs->lock, flags);
701 reset_avmpcipnp(cs);
702 spin_unlock_irqrestore(&cs->lock, flags);
703 return(0);
704 case CARD_RELEASE:
705 outb(0, cs->hw.avm.cfg_reg + 2);
706 release_region(cs->hw.avm.cfg_reg, 32);
707 return(0);
708 case CARD_INIT:
709 spin_lock_irqsave(&cs->lock, flags);
710 reset_avmpcipnp(cs);
711 clear_pending_isac_ints(cs);
712 initisac(cs);
713 inithdlc(cs);
714 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER,
715 cs->hw.avm.cfg_reg + 2);
716 WriteISAC(cs, ISAC_MASK, 0);
717 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER |
718 AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
719 /* RESET Receiver and Transmitter */
720 WriteISAC(cs, ISAC_CMDR, 0x41);
721 spin_unlock_irqrestore(&cs->lock, flags);
722 return(0);
723 case CARD_TEST:
724 return(0);
725 }
726 return(0);
727 }
728
729 #ifdef CONFIG_PCI
730 static struct pci_dev *dev_avm __devinitdata = NULL;
731 #endif
732 #ifdef __ISAPNP__
733 static struct pnp_card *pnp_avm_c __devinitdata = NULL;
734 #endif
735
736 int __devinit
737 setup_avm_pcipnp(struct IsdnCard *card)
738 {
739 u_int val, ver;
740 struct IsdnCardState *cs = card->cs;
741 char tmp[64];
742
743 strcpy(tmp, avm_pci_rev);
744 printk(KERN_INFO "HiSax: AVM PCI driver Rev. %s\n", HiSax_getrev(tmp));
745 if (cs->typ != ISDN_CTYPE_FRITZPCI)
746 return (0);
747 if (card->para[1]) {
748 /* old manual method */
749 cs->hw.avm.cfg_reg = card->para[1];
750 cs->irq = card->para[0];
751 cs->subtyp = AVM_FRITZ_PNP;
752 goto ready;
753 }
754 #ifdef __ISAPNP__
755 if (isapnp_present()) {
756 struct pnp_dev *pnp_avm_d = NULL;
757 if ((pnp_avm_c = pnp_find_card(
758 ISAPNP_VENDOR('A', 'V', 'M'),
759 ISAPNP_FUNCTION(0x0900), pnp_avm_c))) {
760 if ((pnp_avm_d = pnp_find_dev(pnp_avm_c,
761 ISAPNP_VENDOR('A', 'V', 'M'),
762 ISAPNP_FUNCTION(0x0900), pnp_avm_d))) {
763 int err;
764
765 pnp_disable_dev(pnp_avm_d);
766 err = pnp_activate_dev(pnp_avm_d);
767 if (err<0) {
768 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
769 __FUNCTION__, err);
770 return(0);
771 }
772 cs->hw.avm.cfg_reg =
773 pnp_port_start(pnp_avm_d, 0);
774 cs->irq = pnp_irq(pnp_avm_d, 0);
775 if (!cs->irq) {
776 printk(KERN_ERR "FritzPnP:No IRQ\n");
777 return(0);
778 }
779 if (!cs->hw.avm.cfg_reg) {
780 printk(KERN_ERR "FritzPnP:No IO address\n");
781 return(0);
782 }
783 cs->subtyp = AVM_FRITZ_PNP;
784 goto ready;
785 }
786 }
787 } else {
788 printk(KERN_INFO "FritzPnP: no ISA PnP present\n");
789 }
790 #endif
791 #ifdef CONFIG_PCI
792 if ((dev_avm = pci_find_device(PCI_VENDOR_ID_AVM,
793 PCI_DEVICE_ID_AVM_A1, dev_avm))) {
794 if (pci_enable_device(dev_avm))
795 return(0);
796 cs->irq = dev_avm->irq;
797 if (!cs->irq) {
798 printk(KERN_ERR "FritzPCI: No IRQ for PCI card found\n");
799 return(0);
800 }
801 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1);
802 if (!cs->hw.avm.cfg_reg) {
803 printk(KERN_ERR "FritzPCI: No IO-Adr for PCI card found\n");
804 return(0);
805 }
806 cs->subtyp = AVM_FRITZ_PCI;
807 } else {
808 printk(KERN_WARNING "FritzPCI: No PCI card found\n");
809 return(0);
810 }
811 cs->irq_flags |= IRQF_SHARED;
812 #else
813 printk(KERN_WARNING "FritzPCI: NO_PCI_BIOS\n");
814 return (0);
815 #endif /* CONFIG_PCI */
816 ready:
817 cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
818 if (!request_region(cs->hw.avm.cfg_reg, 32,
819 (cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP")) {
820 printk(KERN_WARNING
821 "HiSax: %s config port %x-%x already in use\n",
822 CardType[card->typ],
823 cs->hw.avm.cfg_reg,
824 cs->hw.avm.cfg_reg + 31);
825 return (0);
826 }
827 switch (cs->subtyp) {
828 case AVM_FRITZ_PCI:
829 val = inl(cs->hw.avm.cfg_reg);
830 printk(KERN_INFO "AVM PCI: stat %#x\n", val);
831 printk(KERN_INFO "AVM PCI: Class %X Rev %d\n",
832 val & 0xff, (val>>8) & 0xff);
833 cs->BC_Read_Reg = &ReadHDLC_s;
834 cs->BC_Write_Reg = &WriteHDLC_s;
835 break;
836 case AVM_FRITZ_PNP:
837 val = inb(cs->hw.avm.cfg_reg);
838 ver = inb(cs->hw.avm.cfg_reg + 1);
839 printk(KERN_INFO "AVM PnP: Class %X Rev %d\n", val, ver);
840 cs->BC_Read_Reg = &ReadHDLCPnP;
841 cs->BC_Write_Reg = &WriteHDLCPnP;
842 break;
843 default:
844 printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp);
845 return(0);
846 }
847 printk(KERN_INFO "HiSax: %s config irq:%d base:0x%X\n",
848 (cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP",
849 cs->irq, cs->hw.avm.cfg_reg);
850
851 setup_isac(cs);
852 cs->readisac = &ReadISAC;
853 cs->writeisac = &WriteISAC;
854 cs->readisacfifo = &ReadISACfifo;
855 cs->writeisacfifo = &WriteISACfifo;
856 cs->BC_Send_Data = &hdlc_fill_fifo;
857 cs->cardmsg = &AVM_card_msg;
858 cs->irq_func = &avm_pcipnp_interrupt;
859 cs->writeisac(cs, ISAC_MASK, 0xFF);
860 ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:");
861 return (1);
862 }
Tomato firmware and modifications.