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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / ide / ppc / pmac.c
blob45fc36f0f219feaba9649978c69d697966e2ba57
1 /*
2 * linux/drivers/ide/ppc/pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
36
37 #include <asm/prom.h>
38 #include <asm/io.h>
39 #include <asm/dbdma.h>
40 #include <asm/ide.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
45 #include <asm/irq.h>
46
47 #ifndef CONFIG_PPC64
48 #include <asm/mediabay.h>
49 #endif
50
51 #include "../ide-timing.h"
52
53 #undef IDE_PMAC_DEBUG
54
55 #define DMA_WAIT_TIMEOUT 50
56
57 typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78 #endif
79
80 } pmac_ide_hwif_t;
81
82 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
83 static int pmac_ide_count;
84
85 enum {
86 controller_ohare, /* OHare based */
87 controller_heathrow, /* Heathrow/Paddington */
88 controller_kl_ata3, /* KeyLargo ATA-3 */
89 controller_kl_ata4, /* KeyLargo ATA-4 */
90 controller_un_ata6, /* UniNorth2 ATA-6 */
91 controller_k2_ata6, /* K2 ATA-6 */
92 controller_sh_ata6, /* Shasta ATA-6 */
93 };
94
95 static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103 };
104
105 /*
106 * Extra registers, both 32-bit little-endian
107 */
108 #define IDE_TIMING_CONFIG 0x200
109 #define IDE_INTERRUPT 0x300
110
111 /* Kauai (U2) ATA has different register setup */
112 #define IDE_KAUAI_PIO_CONFIG 0x200
113 #define IDE_KAUAI_ULTRA_CONFIG 0x210
114 #define IDE_KAUAI_POLL_CONFIG 0x220
115
116 /*
117 * Timing configuration register definitions
118 */
119
120 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
125
126 /* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
129 */
130 #define TR_133_PIOREG_PIO_MASK 0xff000fff
131 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
132 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133 #define TR_133_UDMAREG_UDMA_EN 0x00000001
134
135 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
141 *
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
144 *
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
150 */
151 #define TR_100_PIOREG_PIO_MASK 0xff000fff
152 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
153 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154 #define TR_100_UDMAREG_UDMA_EN 0x00000001
155
156
157 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
160 *
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
169 * min value of 45ns.
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
171 * reads.
172 */
173 #define TR_66_UDMA_MASK 0xfff00000
174 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
177 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
179 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
181 #define TR_66_MDMA_MASK 0x000ffc00
182 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183 #define TR_66_MDMA_RECOVERY_SHIFT 15
184 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
185 #define TR_66_MDMA_ACCESS_SHIFT 10
186 #define TR_66_PIO_MASK 0x000003ff
187 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
188 #define TR_66_PIO_RECOVERY_SHIFT 5
189 #define TR_66_PIO_ACCESS_MASK 0x0000001f
190 #define TR_66_PIO_ACCESS_SHIFT 0
191
192 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
194 *
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
202 */
203 #define TR_33_MDMA_MASK 0x003ff800
204 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205 #define TR_33_MDMA_RECOVERY_SHIFT 16
206 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
207 #define TR_33_MDMA_ACCESS_SHIFT 11
208 #define TR_33_MDMA_HALFTICK 0x00200000
209 #define TR_33_PIO_MASK 0x000007ff
210 #define TR_33_PIO_E 0x00000400
211 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
212 #define TR_33_PIO_RECOVERY_SHIFT 5
213 #define TR_33_PIO_ACCESS_MASK 0x0000001f
214 #define TR_33_PIO_ACCESS_SHIFT 0
215
216 /*
217 * Interrupt register definitions
218 */
219 #define IDE_INTR_DMA 0x80000000
220 #define IDE_INTR_DEVICE 0x40000000
221
222 /*
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
224 */
225 #define KAUAI_FCR_UATA_MAGIC 0x00000004
226 #define KAUAI_FCR_UATA_RESET_N 0x00000002
227 #define KAUAI_FCR_UATA_ENABLE 0x00000001
228
229 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
230
231 /* Rounded Multiword DMA timings
232 *
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
236 */
237 struct mdma_timings_t {
238 int accessTime;
239 int recoveryTime;
240 int cycleTime;
241 };
242
243 struct mdma_timings_t mdma_timings_33[] =
244 {
245 { 240, 240, 480 },
246 { 180, 180, 360 },
247 { 135, 135, 270 },
248 { 120, 120, 240 },
249 { 105, 105, 210 },
250 { 90, 90, 180 },
251 { 75, 75, 150 },
252 { 75, 45, 120 },
253 { 0, 0, 0 }
254 };
255
256 struct mdma_timings_t mdma_timings_33k[] =
257 {
258 { 240, 240, 480 },
259 { 180, 180, 360 },
260 { 150, 150, 300 },
261 { 120, 120, 240 },
262 { 90, 120, 210 },
263 { 90, 90, 180 },
264 { 90, 60, 150 },
265 { 90, 30, 120 },
266 { 0, 0, 0 }
267 };
268
269 struct mdma_timings_t mdma_timings_66[] =
270 {
271 { 240, 240, 480 },
272 { 180, 180, 360 },
273 { 135, 135, 270 },
274 { 120, 120, 240 },
275 { 105, 105, 210 },
276 { 90, 90, 180 },
277 { 90, 75, 165 },
278 { 75, 45, 120 },
279 { 0, 0, 0 }
280 };
281
282 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
283 struct {
284 int addrSetup; /* ??? */
285 int rdy2pause;
286 int wrDataSetup;
287 } kl66_udma_timings[] =
288 {
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
294 };
295
296 /* UniNorth 2 ATA/100 timings */
297 struct kauai_timing {
298 int cycle_time;
299 u32 timing_reg;
300 };
301
302 static struct kauai_timing kauai_pio_timings[] =
303 {
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
314 { 120 , 0x04000148 }
315 };
316
317 static struct kauai_timing kauai_mdma_timings[] =
318 {
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
328 { 0 , 0 },
329 };
330
331 static struct kauai_timing kauai_udma_timings[] =
332 {
333 { 120 , 0x000070c0 },
334 { 90 , 0x00005d80 },
335 { 60 , 0x00004a60 },
336 { 45 , 0x00003a50 },
337 { 30 , 0x00002a30 },
338 { 20 , 0x00002921 },
339 { 0 , 0 },
340 };
341
342 static struct kauai_timing shasta_pio_timings[] =
343 {
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
354 { 120 , 0x0400010a }
355 };
356
357 static struct kauai_timing shasta_mdma_timings[] =
358 {
359 { 1260 , 0x00fff000 },
360 { 480 , 0x00820800 },
361 { 360 , 0x00820800 },
362 { 270 , 0x00820800 },
363 { 240 , 0x00820800 },
364 { 210 , 0x00820800 },
365 { 180 , 0x00820800 },
366 { 150 , 0x0028b000 },
367 { 120 , 0x001ca000 },
368 { 0 , 0 },
369 };
370
371 static struct kauai_timing shasta_udma133_timings[] =
372 {
373 { 120 , 0x00035901, },
374 { 90 , 0x000348b1, },
375 { 60 , 0x00033881, },
376 { 45 , 0x00033861, },
377 { 30 , 0x00033841, },
378 { 20 , 0x00033031, },
379 { 15 , 0x00033021, },
380 { 0 , 0 },
381 };
382
383
384 static inline u32
385 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
386 {
387 int i;
388
389 for (i=0; table[i].cycle_time; i++)
390 if (cycle_time > table[i+1].cycle_time)
391 return table[i].timing_reg;
392 return 0;
393 }
394
395 /* allow up to 256 DBDMA commands per xfer */
396 #define MAX_DCMDS 256
397
398 /*
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
401 *
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
409 */
410 #define IDE_WAKEUP_DELAY (1*HZ)
411
412 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
413 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
414 static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
415 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
416 static void pmac_ide_selectproc(ide_drive_t *drive);
417 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
418
419 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
420
421 /*
422 * N.B. this can't be an initfunc, because the media-bay task can
423 * call ide_[un]register at any time.
424 */
425 void
426 pmac_ide_init_hwif_ports(hw_regs_t *hw,
427 unsigned long data_port, unsigned long ctrl_port,
428 int *irq)
429 {
430 int i, ix;
431
432 if (data_port == 0)
433 return;
434
435 for (ix = 0; ix < MAX_HWIFS; ++ix)
436 if (data_port == pmac_ide[ix].regbase)
437 break;
438
439 if (ix >= MAX_HWIFS) {
440 /* Probably a PCI interface... */
441 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
442 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
443 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
444 return;
445 }
446
447 for (i = 0; i < 8; ++i)
448 hw->io_ports[i] = data_port + i * 0x10;
449 hw->io_ports[8] = data_port + 0x160;
450
451 if (irq != NULL)
452 *irq = pmac_ide[ix].irq;
453
454 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
455 }
456
457 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
458
459 /*
460 * Apply the timings of the proper unit (master/slave) to the shared
461 * timing register when selecting that unit. This version is for
462 * ASICs with a single timing register
463 */
464 static void
465 pmac_ide_selectproc(ide_drive_t *drive)
466 {
467 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
468
469 if (pmif == NULL)
470 return;
471
472 if (drive->select.b.unit & 0x01)
473 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
474 else
475 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
477 }
478
479 /*
480 * Apply the timings of the proper unit (master/slave) to the shared
481 * timing register when selecting that unit. This version is for
482 * ASICs with a dual timing register (Kauai)
483 */
484 static void
485 pmac_ide_kauai_selectproc(ide_drive_t *drive)
486 {
487 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
488
489 if (pmif == NULL)
490 return;
491
492 if (drive->select.b.unit & 0x01) {
493 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
494 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
495 } else {
496 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
497 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
498 }
499 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
500 }
501
502 /*
503 * Force an update of controller timing values for a given drive
504 */
505 static void
506 pmac_ide_do_update_timings(ide_drive_t *drive)
507 {
508 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
509
510 if (pmif == NULL)
511 return;
512
513 if (pmif->kind == controller_sh_ata6 ||
514 pmif->kind == controller_un_ata6 ||
515 pmif->kind == controller_k2_ata6)
516 pmac_ide_kauai_selectproc(drive);
517 else
518 pmac_ide_selectproc(drive);
519 }
520
521 static void
522 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
523 {
524 u32 tmp;
525
526 writeb(value, (void __iomem *) port);
527 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
528 }
529
530 /*
531 * Send the SET_FEATURE IDE command to the drive and update drive->id with
532 * the new state. We currently don't use the generic routine as it used to
533 * cause various trouble, especially with older mediabays.
534 * This code is sometimes triggering a spurrious interrupt though, I need
535 * to sort that out sooner or later and see if I can finally get the
536 * common version to work properly in all cases
537 */
538 static int
539 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
540 {
541 ide_hwif_t *hwif = HWIF(drive);
542 int result = 1;
543
544 disable_irq_nosync(hwif->irq);
545 udelay(1);
546 SELECT_DRIVE(drive);
547 SELECT_MASK(drive, 0);
548 udelay(1);
549 /* Get rid of pending error state */
550 (void) hwif->INB(IDE_STATUS_REG);
551 /* Timeout bumped for some powerbooks */
552 if (wait_for_ready(drive, 2000)) {
553 /* Timeout bumped for some powerbooks */
554 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
555 "before SET_FEATURE!\n", drive->name);
556 goto out;
557 }
558 udelay(10);
559 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
560 hwif->OUTB(command, IDE_NSECTOR_REG);
561 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
562 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
563 udelay(1);
564 /* Timeout bumped for some powerbooks */
565 result = wait_for_ready(drive, 2000);
566 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
567 if (result)
568 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
569 "after SET_FEATURE !\n", drive->name);
570 out:
571 SELECT_MASK(drive, 0);
572 if (result == 0) {
573 drive->id->dma_ultra &= ~0xFF00;
574 drive->id->dma_mword &= ~0x0F00;
575 drive->id->dma_1word &= ~0x0F00;
576 switch(command) {
577 case XFER_UDMA_7:
578 drive->id->dma_ultra |= 0x8080; break;
579 case XFER_UDMA_6:
580 drive->id->dma_ultra |= 0x4040; break;
581 case XFER_UDMA_5:
582 drive->id->dma_ultra |= 0x2020; break;
583 case XFER_UDMA_4:
584 drive->id->dma_ultra |= 0x1010; break;
585 case XFER_UDMA_3:
586 drive->id->dma_ultra |= 0x0808; break;
587 case XFER_UDMA_2:
588 drive->id->dma_ultra |= 0x0404; break;
589 case XFER_UDMA_1:
590 drive->id->dma_ultra |= 0x0202; break;
591 case XFER_UDMA_0:
592 drive->id->dma_ultra |= 0x0101; break;
593 case XFER_MW_DMA_2:
594 drive->id->dma_mword |= 0x0404; break;
595 case XFER_MW_DMA_1:
596 drive->id->dma_mword |= 0x0202; break;
597 case XFER_MW_DMA_0:
598 drive->id->dma_mword |= 0x0101; break;
599 case XFER_SW_DMA_2:
600 drive->id->dma_1word |= 0x0404; break;
601 case XFER_SW_DMA_1:
602 drive->id->dma_1word |= 0x0202; break;
603 case XFER_SW_DMA_0:
604 drive->id->dma_1word |= 0x0101; break;
605 default: break;
606 }
607 }
608 enable_irq(hwif->irq);
609 return result;
610 }
611
612 /*
613 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
614 */
615 static void
616 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
617 {
618 ide_pio_data_t d;
619 u32 *timings;
620 unsigned accessTicks, recTicks;
621 unsigned accessTime, recTime;
622 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
623
624 if (pmif == NULL)
625 return;
626
627 /* which drive is it ? */
628 timings = &pmif->timings[drive->select.b.unit & 0x01];
629
630 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
631
632 switch (pmif->kind) {
633 case controller_sh_ata6: {
634 /* 133Mhz cell */
635 u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
636 if (tr == 0)
637 return;
638 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
639 break;
640 }
641 case controller_un_ata6:
642 case controller_k2_ata6: {
643 /* 100Mhz cell */
644 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
645 if (tr == 0)
646 return;
647 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
648 break;
649 }
650 case controller_kl_ata4:
651 /* 66Mhz cell */
652 recTime = d.cycle_time - ide_pio_timings[pio].active_time
653 - ide_pio_timings[pio].setup_time;
654 recTime = max(recTime, 150U);
655 accessTime = ide_pio_timings[pio].active_time;
656 accessTime = max(accessTime, 150U);
657 accessTicks = SYSCLK_TICKS_66(accessTime);
658 accessTicks = min(accessTicks, 0x1fU);
659 recTicks = SYSCLK_TICKS_66(recTime);
660 recTicks = min(recTicks, 0x1fU);
661 *timings = ((*timings) & ~TR_66_PIO_MASK) |
662 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
663 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
664 break;
665 default: {
666 /* 33Mhz cell */
667 int ebit = 0;
668 recTime = d.cycle_time - ide_pio_timings[pio].active_time
669 - ide_pio_timings[pio].setup_time;
670 recTime = max(recTime, 150U);
671 accessTime = ide_pio_timings[pio].active_time;
672 accessTime = max(accessTime, 150U);
673 accessTicks = SYSCLK_TICKS(accessTime);
674 accessTicks = min(accessTicks, 0x1fU);
675 accessTicks = max(accessTicks, 4U);
676 recTicks = SYSCLK_TICKS(recTime);
677 recTicks = min(recTicks, 0x1fU);
678 recTicks = max(recTicks, 5U) - 4;
679 if (recTicks > 9) {
680 recTicks--; /* guess, but it's only for PIO0, so... */
681 ebit = 1;
682 }
683 *timings = ((*timings) & ~TR_33_PIO_MASK) |
684 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
685 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
686 if (ebit)
687 *timings |= TR_33_PIO_E;
688 break;
689 }
690 }
691
692 #ifdef IDE_PMAC_DEBUG
693 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
694 drive->name, pio, *timings);
695 #endif
696
697 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
698 pmac_ide_do_update_timings(drive);
699 }
700
701 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
702
703 /*
704 * Calculate KeyLargo ATA/66 UDMA timings
705 */
706 static int
707 set_timings_udma_ata4(u32 *timings, u8 speed)
708 {
709 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
710
711 if (speed > XFER_UDMA_4)
712 return 1;
713
714 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
715 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
716 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
717
718 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
719 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
720 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
721 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
722 TR_66_UDMA_EN;
723 #ifdef IDE_PMAC_DEBUG
724 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
725 speed & 0xf, *timings);
726 #endif
727
728 return 0;
729 }
730
731 /*
732 * Calculate Kauai ATA/100 UDMA timings
733 */
734 static int
735 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
736 {
737 struct ide_timing *t = ide_timing_find_mode(speed);
738 u32 tr;
739
740 if (speed > XFER_UDMA_5 || t == NULL)
741 return 1;
742 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
743 if (tr == 0)
744 return 1;
745 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
746 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
747
748 return 0;
749 }
750
751 /*
752 * Calculate Shasta ATA/133 UDMA timings
753 */
754 static int
755 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
756 {
757 struct ide_timing *t = ide_timing_find_mode(speed);
758 u32 tr;
759
760 if (speed > XFER_UDMA_6 || t == NULL)
761 return 1;
762 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
763 if (tr == 0)
764 return 1;
765 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
766 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
767
768 return 0;
769 }
770
771 /*
772 * Calculate MDMA timings for all cells
773 */
774 static int
775 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
776 u8 speed, int drive_cycle_time)
777 {
778 int cycleTime, accessTime = 0, recTime = 0;
779 unsigned accessTicks, recTicks;
780 struct mdma_timings_t* tm = NULL;
781 int i;
782
783 /* Get default cycle time for mode */
784 switch(speed & 0xf) {
785 case 0: cycleTime = 480; break;
786 case 1: cycleTime = 150; break;
787 case 2: cycleTime = 120; break;
788 default:
789 return 1;
790 }
791 /* Adjust for drive */
792 if (drive_cycle_time && drive_cycle_time > cycleTime)
793 cycleTime = drive_cycle_time;
794 /* OHare limits according to some old Apple sources */
795 if ((intf_type == controller_ohare) && (cycleTime < 150))
796 cycleTime = 150;
797 /* Get the proper timing array for this controller */
798 switch(intf_type) {
799 case controller_sh_ata6:
800 case controller_un_ata6:
801 case controller_k2_ata6:
802 break;
803 case controller_kl_ata4:
804 tm = mdma_timings_66;
805 break;
806 case controller_kl_ata3:
807 tm = mdma_timings_33k;
808 break;
809 default:
810 tm = mdma_timings_33;
811 break;
812 }
813 if (tm != NULL) {
814 /* Lookup matching access & recovery times */
815 i = -1;
816 for (;;) {
817 if (tm[i+1].cycleTime < cycleTime)
818 break;
819 i++;
820 }
821 if (i < 0)
822 return 1;
823 cycleTime = tm[i].cycleTime;
824 accessTime = tm[i].accessTime;
825 recTime = tm[i].recoveryTime;
826
827 #ifdef IDE_PMAC_DEBUG
828 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
829 drive->name, cycleTime, accessTime, recTime);
830 #endif
831 }
832 switch(intf_type) {
833 case controller_sh_ata6: {
834 /* 133Mhz cell */
835 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
836 if (tr == 0)
837 return 1;
838 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
839 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
840 }
841 case controller_un_ata6:
842 case controller_k2_ata6: {
843 /* 100Mhz cell */
844 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
845 if (tr == 0)
846 return 1;
847 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
848 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
849 }
850 break;
851 case controller_kl_ata4:
852 /* 66Mhz cell */
853 accessTicks = SYSCLK_TICKS_66(accessTime);
854 accessTicks = min(accessTicks, 0x1fU);
855 accessTicks = max(accessTicks, 0x1U);
856 recTicks = SYSCLK_TICKS_66(recTime);
857 recTicks = min(recTicks, 0x1fU);
858 recTicks = max(recTicks, 0x3U);
859 /* Clear out mdma bits and disable udma */
860 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
861 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
862 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
863 break;
864 case controller_kl_ata3:
865 /* 33Mhz cell on KeyLargo */
866 accessTicks = SYSCLK_TICKS(accessTime);
867 accessTicks = max(accessTicks, 1U);
868 accessTicks = min(accessTicks, 0x1fU);
869 accessTime = accessTicks * IDE_SYSCLK_NS;
870 recTicks = SYSCLK_TICKS(recTime);
871 recTicks = max(recTicks, 1U);
872 recTicks = min(recTicks, 0x1fU);
873 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
874 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
875 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
876 break;
877 default: {
878 /* 33Mhz cell on others */
879 int halfTick = 0;
880 int origAccessTime = accessTime;
881 int origRecTime = recTime;
882
883 accessTicks = SYSCLK_TICKS(accessTime);
884 accessTicks = max(accessTicks, 1U);
885 accessTicks = min(accessTicks, 0x1fU);
886 accessTime = accessTicks * IDE_SYSCLK_NS;
887 recTicks = SYSCLK_TICKS(recTime);
888 recTicks = max(recTicks, 2U) - 1;
889 recTicks = min(recTicks, 0x1fU);
890 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
891 if ((accessTicks > 1) &&
892 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
893 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
894 halfTick = 1;
895 accessTicks--;
896 }
897 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
898 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
899 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
900 if (halfTick)
901 *timings |= TR_33_MDMA_HALFTICK;
902 }
903 }
904 #ifdef IDE_PMAC_DEBUG
905 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
906 drive->name, speed & 0xf, *timings);
907 #endif
908 return 0;
909 }
910 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
911
912 /*
913 * Speedproc. This function is called by the core to set any of the standard
914 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
915 * You may notice we don't use this function on normal "dma check" operation,
916 * our dedicated function is more precise as it uses the drive provided
917 * cycle time value. We should probably fix this one to deal with that too...
918 */
919 static int
920 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
921 {
922 int unit = (drive->select.b.unit & 0x01);
923 int ret = 0;
924 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
925 u32 *timings, *timings2;
926
927 if (pmif == NULL)
928 return 1;
929
930 timings = &pmif->timings[unit];
931 timings2 = &pmif->timings[unit+2];
932
933 switch(speed) {
934 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
935 case XFER_UDMA_6:
936 if (pmif->kind != controller_sh_ata6)
937 return 1;
938 case XFER_UDMA_5:
939 if (pmif->kind != controller_un_ata6 &&
940 pmif->kind != controller_k2_ata6 &&
941 pmif->kind != controller_sh_ata6)
942 return 1;
943 case XFER_UDMA_4:
944 case XFER_UDMA_3:
945 if (HWIF(drive)->udma_four == 0)
946 return 1;
947 case XFER_UDMA_2:
948 case XFER_UDMA_1:
949 case XFER_UDMA_0:
950 if (pmif->kind == controller_kl_ata4)
951 ret = set_timings_udma_ata4(timings, speed);
952 else if (pmif->kind == controller_un_ata6
953 || pmif->kind == controller_k2_ata6)
954 ret = set_timings_udma_ata6(timings, timings2, speed);
955 else if (pmif->kind == controller_sh_ata6)
956 ret = set_timings_udma_shasta(timings, timings2, speed);
957 else
958 ret = 1;
959 break;
960 case XFER_MW_DMA_2:
961 case XFER_MW_DMA_1:
962 case XFER_MW_DMA_0:
963 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
964 break;
965 case XFER_SW_DMA_2:
966 case XFER_SW_DMA_1:
967 case XFER_SW_DMA_0:
968 return 1;
969 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
970 case XFER_PIO_4:
971 case XFER_PIO_3:
972 case XFER_PIO_2:
973 case XFER_PIO_1:
974 case XFER_PIO_0:
975 pmac_ide_tuneproc(drive, speed & 0x07);
976 break;
977 default:
978 ret = 1;
979 }
980 if (ret)
981 return ret;
982
983 ret = pmac_ide_do_setfeature(drive, speed);
984 if (ret)
985 return ret;
986
987 pmac_ide_do_update_timings(drive);
988 drive->current_speed = speed;
989
990 return 0;
991 }
992
993 /*
994 * Blast some well known "safe" values to the timing registers at init or
995 * wakeup from sleep time, before we do real calculation
996 */
997 static void
998 sanitize_timings(pmac_ide_hwif_t *pmif)
999 {
1000 unsigned int value, value2 = 0;
1001
1002 switch(pmif->kind) {
1003 case controller_sh_ata6:
1004 value = 0x0a820c97;
1005 value2 = 0x00033031;
1006 break;
1007 case controller_un_ata6:
1008 case controller_k2_ata6:
1009 value = 0x08618a92;
1010 value2 = 0x00002921;
1011 break;
1012 case controller_kl_ata4:
1013 value = 0x0008438c;
1014 break;
1015 case controller_kl_ata3:
1016 value = 0x00084526;
1017 break;
1018 case controller_heathrow:
1019 case controller_ohare:
1020 default:
1021 value = 0x00074526;
1022 break;
1023 }
1024 pmif->timings[0] = pmif->timings[1] = value;
1025 pmif->timings[2] = pmif->timings[3] = value2;
1026 }
1027
1028 unsigned long
1029 pmac_ide_get_base(int index)
1030 {
1031 return pmac_ide[index].regbase;
1032 }
1033
1034 int
1035 pmac_ide_check_base(unsigned long base)
1036 {
1037 int ix;
1038
1039 for (ix = 0; ix < MAX_HWIFS; ++ix)
1040 if (base == pmac_ide[ix].regbase)
1041 return ix;
1042 return -1;
1043 }
1044
1045 int
1046 pmac_ide_get_irq(unsigned long base)
1047 {
1048 int ix;
1049
1050 for (ix = 0; ix < MAX_HWIFS; ++ix)
1051 if (base == pmac_ide[ix].regbase)
1052 return pmac_ide[ix].irq;
1053 return 0;
1054 }
1055
1056 static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1057
1058 dev_t __init
1059 pmac_find_ide_boot(char *bootdevice, int n)
1060 {
1061 int i;
1062
1063 /*
1064 * Look through the list of IDE interfaces for this one.
1065 */
1066 for (i = 0; i < pmac_ide_count; ++i) {
1067 char *name;
1068 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1069 continue;
1070 name = pmac_ide[i].node->full_name;
1071 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1072 /* XXX should cope with the 2nd drive as well... */
1073 return MKDEV(ide_majors[i], 0);
1074 }
1075 }
1076
1077 return 0;
1078 }
1079
1080 /* Suspend call back, should be called after the child devices
1081 * have actually been suspended
1082 */
1083 static int
1084 pmac_ide_do_suspend(ide_hwif_t *hwif)
1085 {
1086 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1087
1088 /* We clear the timings */
1089 pmif->timings[0] = 0;
1090 pmif->timings[1] = 0;
1091
1092 disable_irq(pmif->irq);
1093
1094 /* The media bay will handle itself just fine */
1095 if (pmif->mediabay)
1096 return 0;
1097
1098 /* Kauai has bus control FCRs directly here */
1099 if (pmif->kauai_fcr) {
1100 u32 fcr = readl(pmif->kauai_fcr);
1101 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1102 writel(fcr, pmif->kauai_fcr);
1103 }
1104
1105 /* Disable the bus on older machines and the cell on kauai */
1106 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1107 0);
1108
1109 return 0;
1110 }
1111
1112 /* Resume call back, should be called before the child devices
1113 * are resumed
1114 */
1115 static int
1116 pmac_ide_do_resume(ide_hwif_t *hwif)
1117 {
1118 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1119
1120 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1121 if (!pmif->mediabay) {
1122 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1123 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1124 msleep(10);
1125 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1126
1127 /* Kauai has it different */
1128 if (pmif->kauai_fcr) {
1129 u32 fcr = readl(pmif->kauai_fcr);
1130 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1131 writel(fcr, pmif->kauai_fcr);
1132 }
1133
1134 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1135 }
1136
1137 /* Sanitize drive timings */
1138 sanitize_timings(pmif);
1139
1140 enable_irq(pmif->irq);
1141
1142 return 0;
1143 }
1144
1145 /*
1146 * Setup, register & probe an IDE channel driven by this driver, this is
1147 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1148 * that ends up beeing free of any device is not kept around by this driver
1149 * (it is kept in 2.4). This introduce an interface numbering change on some
1150 * rare machines unfortunately, but it's better this way.
1151 */
1152 static int
1153 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1154 {
1155 struct device_node *np = pmif->node;
1156 const int *bidp;
1157
1158 pmif->cable_80 = 0;
1159 pmif->broken_dma = pmif->broken_dma_warn = 0;
1160 if (of_device_is_compatible(np, "shasta-ata"))
1161 pmif->kind = controller_sh_ata6;
1162 else if (of_device_is_compatible(np, "kauai-ata"))
1163 pmif->kind = controller_un_ata6;
1164 else if (of_device_is_compatible(np, "K2-UATA"))
1165 pmif->kind = controller_k2_ata6;
1166 else if (of_device_is_compatible(np, "keylargo-ata")) {
1167 if (strcmp(np->name, "ata-4") == 0)
1168 pmif->kind = controller_kl_ata4;
1169 else
1170 pmif->kind = controller_kl_ata3;
1171 } else if (of_device_is_compatible(np, "heathrow-ata"))
1172 pmif->kind = controller_heathrow;
1173 else {
1174 pmif->kind = controller_ohare;
1175 pmif->broken_dma = 1;
1176 }
1177
1178 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1179 pmif->aapl_bus_id = bidp ? *bidp : 0;
1180
1181 /* Get cable type from device-tree */
1182 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1183 || pmif->kind == controller_k2_ata6
1184 || pmif->kind == controller_sh_ata6) {
1185 const char* cable = of_get_property(np, "cable-type", NULL);
1186 if (cable && !strncmp(cable, "80-", 3))
1187 pmif->cable_80 = 1;
1188 }
1189 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1190 * they have a 80 conductor cable, this seem to be always the case unless
1191 * the user mucked around
1192 */
1193 if (of_device_is_compatible(np, "K2-UATA") ||
1194 of_device_is_compatible(np, "shasta-ata"))
1195 pmif->cable_80 = 1;
1196
1197 /* On Kauai-type controllers, we make sure the FCR is correct */
1198 if (pmif->kauai_fcr)
1199 writel(KAUAI_FCR_UATA_MAGIC |
1200 KAUAI_FCR_UATA_RESET_N |
1201 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1202
1203 pmif->mediabay = 0;
1204
1205 /* Make sure we have sane timings */
1206 sanitize_timings(pmif);
1207
1208 #ifndef CONFIG_PPC64
1209 /* XXX FIXME: Media bay stuff need re-organizing */
1210 if (np->parent && np->parent->name
1211 && strcasecmp(np->parent->name, "media-bay") == 0) {
1212 #ifdef CONFIG_PMAC_MEDIABAY
1213 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1214 #endif /* CONFIG_PMAC_MEDIABAY */
1215 pmif->mediabay = 1;
1216 if (!bidp)
1217 pmif->aapl_bus_id = 1;
1218 } else if (pmif->kind == controller_ohare) {
1219 /* The code below is having trouble on some ohare machines
1220 * (timing related ?). Until I can put my hand on one of these
1221 * units, I keep the old way
1222 */
1223 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1224 } else
1225 #endif
1226 {
1227 /* This is necessary to enable IDE when net-booting */
1228 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1229 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1230 msleep(10);
1231 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1232 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1233 }
1234
1235 /* Setup MMIO ops */
1236 default_hwif_mmiops(hwif);
1237 hwif->OUTBSYNC = pmac_outbsync;
1238
1239 /* Tell common code _not_ to mess with resources */
1240 hwif->mmio = 1;
1241 hwif->hwif_data = pmif;
1242 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1243 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1244 hwif->chipset = ide_pmac;
1245 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1246 hwif->hold = pmif->mediabay;
1247 hwif->udma_four = pmif->cable_80;
1248 hwif->drives[0].unmask = 1;
1249 hwif->drives[1].unmask = 1;
1250 hwif->tuneproc = pmac_ide_tuneproc;
1251 if (pmif->kind == controller_un_ata6
1252 || pmif->kind == controller_k2_ata6
1253 || pmif->kind == controller_sh_ata6)
1254 hwif->selectproc = pmac_ide_kauai_selectproc;
1255 else
1256 hwif->selectproc = pmac_ide_selectproc;
1257 hwif->speedproc = pmac_ide_tune_chipset;
1258
1259 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1260 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1261 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1262
1263 #ifdef CONFIG_PMAC_MEDIABAY
1264 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1265 hwif->noprobe = 0;
1266 #endif /* CONFIG_PMAC_MEDIABAY */
1267
1268 hwif->sg_max_nents = MAX_DCMDS;
1269
1270 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1271 /* has a DBDMA controller channel */
1272 if (pmif->dma_regs)
1273 pmac_ide_setup_dma(pmif, hwif);
1274 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1275
1276 /* We probe the hwif now */
1277 probe_hwif_init(hwif);
1278
1279 ide_proc_register_port(hwif);
1280
1281 return 0;
1282 }
1283
1284 /*
1285 * Attach to a macio probed interface
1286 */
1287 static int __devinit
1288 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1289 {
1290 void __iomem *base;
1291 unsigned long regbase;
1292 int irq;
1293 ide_hwif_t *hwif;
1294 pmac_ide_hwif_t *pmif;
1295 int i, rc;
1296
1297 i = 0;
1298 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1299 || pmac_ide[i].node != NULL))
1300 ++i;
1301 if (i >= MAX_HWIFS) {
1302 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1303 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1304 return -ENODEV;
1305 }
1306
1307 pmif = &pmac_ide[i];
1308 hwif = &ide_hwifs[i];
1309
1310 if (macio_resource_count(mdev) == 0) {
1311 printk(KERN_WARNING "ide%d: no address for %s\n",
1312 i, mdev->ofdev.node->full_name);
1313 return -ENXIO;
1314 }
1315
1316 /* Request memory resource for IO ports */
1317 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1318 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1319 return -EBUSY;
1320 }
1321
1322 /* XXX This is bogus. Should be fixed in the registry by checking
1323 * the kind of host interrupt controller, a bit like gatwick
1324 * fixes in irq.c. That works well enough for the single case
1325 * where that happens though...
1326 */
1327 if (macio_irq_count(mdev) == 0) {
1328 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1329 i, mdev->ofdev.node->full_name);
1330 irq = irq_create_mapping(NULL, 13);
1331 } else
1332 irq = macio_irq(mdev, 0);
1333
1334 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1335 regbase = (unsigned long) base;
1336
1337 hwif->pci_dev = mdev->bus->pdev;
1338 hwif->gendev.parent = &mdev->ofdev.dev;
1339
1340 pmif->mdev = mdev;
1341 pmif->node = mdev->ofdev.node;
1342 pmif->regbase = regbase;
1343 pmif->irq = irq;
1344 pmif->kauai_fcr = NULL;
1345 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1346 if (macio_resource_count(mdev) >= 2) {
1347 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1348 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1349 else
1350 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1351 } else
1352 pmif->dma_regs = NULL;
1353 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1354 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1355
1356 rc = pmac_ide_setup_device(pmif, hwif);
1357 if (rc != 0) {
1358 /* The inteface is released to the common IDE layer */
1359 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1360 iounmap(base);
1361 if (pmif->dma_regs)
1362 iounmap(pmif->dma_regs);
1363 memset(pmif, 0, sizeof(*pmif));
1364 macio_release_resource(mdev, 0);
1365 if (pmif->dma_regs)
1366 macio_release_resource(mdev, 1);
1367 }
1368
1369 return rc;
1370 }
1371
1372 static int
1373 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1374 {
1375 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1376 int rc = 0;
1377
1378 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1379 && mesg.event == PM_EVENT_SUSPEND) {
1380 rc = pmac_ide_do_suspend(hwif);
1381 if (rc == 0)
1382 mdev->ofdev.dev.power.power_state = mesg;
1383 }
1384
1385 return rc;
1386 }
1387
1388 static int
1389 pmac_ide_macio_resume(struct macio_dev *mdev)
1390 {
1391 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1392 int rc = 0;
1393
1394 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1395 rc = pmac_ide_do_resume(hwif);
1396 if (rc == 0)
1397 mdev->ofdev.dev.power.power_state = PMSG_ON;
1398 }
1399
1400 return rc;
1401 }
1402
1403 /*
1404 * Attach to a PCI probed interface
1405 */
1406 static int __devinit
1407 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1408 {
1409 ide_hwif_t *hwif;
1410 struct device_node *np;
1411 pmac_ide_hwif_t *pmif;
1412 void __iomem *base;
1413 unsigned long rbase, rlen;
1414 int i, rc;
1415
1416 np = pci_device_to_OF_node(pdev);
1417 if (np == NULL) {
1418 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1419 return -ENODEV;
1420 }
1421 i = 0;
1422 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1423 || pmac_ide[i].node != NULL))
1424 ++i;
1425 if (i >= MAX_HWIFS) {
1426 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1427 printk(KERN_ERR " %s\n", np->full_name);
1428 return -ENODEV;
1429 }
1430
1431 pmif = &pmac_ide[i];
1432 hwif = &ide_hwifs[i];
1433
1434 if (pci_enable_device(pdev)) {
1435 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1436 i, np->full_name);
1437 return -ENXIO;
1438 }
1439 pci_set_master(pdev);
1440
1441 if (pci_request_regions(pdev, "Kauai ATA")) {
1442 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1443 i, np->full_name);
1444 return -ENXIO;
1445 }
1446
1447 hwif->pci_dev = pdev;
1448 hwif->gendev.parent = &pdev->dev;
1449 pmif->mdev = NULL;
1450 pmif->node = np;
1451
1452 rbase = pci_resource_start(pdev, 0);
1453 rlen = pci_resource_len(pdev, 0);
1454
1455 base = ioremap(rbase, rlen);
1456 pmif->regbase = (unsigned long) base + 0x2000;
1457 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1458 pmif->dma_regs = base + 0x1000;
1459 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1460 pmif->kauai_fcr = base;
1461 pmif->irq = pdev->irq;
1462
1463 pci_set_drvdata(pdev, hwif);
1464
1465 rc = pmac_ide_setup_device(pmif, hwif);
1466 if (rc != 0) {
1467 /* The inteface is released to the common IDE layer */
1468 pci_set_drvdata(pdev, NULL);
1469 iounmap(base);
1470 memset(pmif, 0, sizeof(*pmif));
1471 pci_release_regions(pdev);
1472 }
1473
1474 return rc;
1475 }
1476
1477 static int
1478 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1479 {
1480 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1481 int rc = 0;
1482
1483 if (mesg.event != pdev->dev.power.power_state.event
1484 && mesg.event == PM_EVENT_SUSPEND) {
1485 rc = pmac_ide_do_suspend(hwif);
1486 if (rc == 0)
1487 pdev->dev.power.power_state = mesg;
1488 }
1489
1490 return rc;
1491 }
1492
1493 static int
1494 pmac_ide_pci_resume(struct pci_dev *pdev)
1495 {
1496 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1497 int rc = 0;
1498
1499 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1500 rc = pmac_ide_do_resume(hwif);
1501 if (rc == 0)
1502 pdev->dev.power.power_state = PMSG_ON;
1503 }
1504
1505 return rc;
1506 }
1507
1508 static struct of_device_id pmac_ide_macio_match[] =
1509 {
1510 {
1511 .name = "IDE",
1512 },
1513 {
1514 .name = "ATA",
1515 },
1516 {
1517 .type = "ide",
1518 },
1519 {
1520 .type = "ata",
1521 },
1522 {},
1523 };
1524
1525 static struct macio_driver pmac_ide_macio_driver =
1526 {
1527 .name = "ide-pmac",
1528 .match_table = pmac_ide_macio_match,
1529 .probe = pmac_ide_macio_attach,
1530 .suspend = pmac_ide_macio_suspend,
1531 .resume = pmac_ide_macio_resume,
1532 };
1533
1534 static struct pci_device_id pmac_ide_pci_match[] = {
1535 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1537 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1539 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1541 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1543 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1545 };
1546
1547 static struct pci_driver pmac_ide_pci_driver = {
1548 .name = "ide-pmac",
1549 .id_table = pmac_ide_pci_match,
1550 .probe = pmac_ide_pci_attach,
1551 .suspend = pmac_ide_pci_suspend,
1552 .resume = pmac_ide_pci_resume,
1553 };
1554 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1555
1556 int __init pmac_ide_probe(void)
1557 {
1558 int error;
1559
1560 if (!machine_is(powermac))
1561 return -ENODEV;
1562
1563 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1564 error = pci_register_driver(&pmac_ide_pci_driver);
1565 if (error)
1566 goto out;
1567 error = macio_register_driver(&pmac_ide_macio_driver);
1568 if (error) {
1569 pci_unregister_driver(&pmac_ide_pci_driver);
1570 goto out;
1571 }
1572 #else
1573 error = macio_register_driver(&pmac_ide_macio_driver);
1574 if (error)
1575 goto out;
1576 error = pci_register_driver(&pmac_ide_pci_driver);
1577 if (error) {
1578 macio_unregister_driver(&pmac_ide_macio_driver);
1579 goto out;
1580 }
1581 #endif
1582 out:
1583 return error;
1584 }
1585
1586 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1587
1588 /*
1589 * pmac_ide_build_dmatable builds the DBDMA command list
1590 * for a transfer and sets the DBDMA channel to point to it.
1591 */
1592 static int
1593 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1594 {
1595 struct dbdma_cmd *table;
1596 int i, count = 0;
1597 ide_hwif_t *hwif = HWIF(drive);
1598 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1599 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1600 struct scatterlist *sg;
1601 int wr = (rq_data_dir(rq) == WRITE);
1602
1603 /* DMA table is already aligned */
1604 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1605
1606 /* Make sure DMA controller is stopped (necessary ?) */
1607 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1608 while (readl(&dma->status) & RUN)
1609 udelay(1);
1610
1611 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1612
1613 if (!i)
1614 return 0;
1615
1616 /* Build DBDMA commands list */
1617 sg = hwif->sg_table;
1618 while (i && sg_dma_len(sg)) {
1619 u32 cur_addr;
1620 u32 cur_len;
1621
1622 cur_addr = sg_dma_address(sg);
1623 cur_len = sg_dma_len(sg);
1624
1625 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1626 if (pmif->broken_dma_warn == 0) {
1627 printk(KERN_WARNING "%s: DMA on non aligned address,"
1628 "switching to PIO on Ohare chipset\n", drive->name);
1629 pmif->broken_dma_warn = 1;
1630 }
1631 goto use_pio_instead;
1632 }
1633 while (cur_len) {
1634 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1635
1636 if (count++ >= MAX_DCMDS) {
1637 printk(KERN_WARNING "%s: DMA table too small\n",
1638 drive->name);
1639 goto use_pio_instead;
1640 }
1641 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1642 st_le16(&table->req_count, tc);
1643 st_le32(&table->phy_addr, cur_addr);
1644 table->cmd_dep = 0;
1645 table->xfer_status = 0;
1646 table->res_count = 0;
1647 cur_addr += tc;
1648 cur_len -= tc;
1649 ++table;
1650 }
1651 sg++;
1652 i--;
1653 }
1654
1655 /* convert the last command to an input/output last command */
1656 if (count) {
1657 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1658 /* add the stop command to the end of the list */
1659 memset(table, 0, sizeof(struct dbdma_cmd));
1660 st_le16(&table->command, DBDMA_STOP);
1661 mb();
1662 writel(hwif->dmatable_dma, &dma->cmdptr);
1663 return 1;
1664 }
1665
1666 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1667 use_pio_instead:
1668 pci_unmap_sg(hwif->pci_dev,
1669 hwif->sg_table,
1670 hwif->sg_nents,
1671 hwif->sg_dma_direction);
1672 return 0; /* revert to PIO for this request */
1673 }
1674
1675 /* Teardown mappings after DMA has completed. */
1676 static void
1677 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1678 {
1679 ide_hwif_t *hwif = drive->hwif;
1680 struct pci_dev *dev = HWIF(drive)->pci_dev;
1681 struct scatterlist *sg = hwif->sg_table;
1682 int nents = hwif->sg_nents;
1683
1684 if (nents) {
1685 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1686 hwif->sg_nents = 0;
1687 }
1688 }
1689
1690 /*
1691 * Pick up best MDMA timing for the drive and apply it
1692 */
1693 static int
1694 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1695 {
1696 ide_hwif_t *hwif = HWIF(drive);
1697 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1698 int drive_cycle_time;
1699 struct hd_driveid *id = drive->id;
1700 u32 *timings, *timings2;
1701 u32 timing_local[2];
1702 int ret;
1703
1704 /* which drive is it ? */
1705 timings = &pmif->timings[drive->select.b.unit & 0x01];
1706 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1707
1708 /* Check if drive provide explicit cycle time */
1709 if ((id->field_valid & 2) && (id->eide_dma_time))
1710 drive_cycle_time = id->eide_dma_time;
1711 else
1712 drive_cycle_time = 0;
1713
1714 /* Copy timings to local image */
1715 timing_local[0] = *timings;
1716 timing_local[1] = *timings2;
1717
1718 /* Calculate controller timings */
1719 ret = set_timings_mdma( drive, pmif->kind,
1720 &timing_local[0],
1721 &timing_local[1],
1722 mode,
1723 drive_cycle_time);
1724 if (ret)
1725 return 0;
1726
1727 /* Set feature on drive */
1728 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1729 ret = pmac_ide_do_setfeature(drive, mode);
1730 if (ret) {
1731 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1732 return 0;
1733 }
1734
1735 /* Apply timings to controller */
1736 *timings = timing_local[0];
1737 *timings2 = timing_local[1];
1738
1739 /* Set speed info in drive */
1740 drive->current_speed = mode;
1741 if (!drive->init_speed)
1742 drive->init_speed = mode;
1743
1744 return 1;
1745 }
1746
1747 /*
1748 * Pick up best UDMA timing for the drive and apply it
1749 */
1750 static int
1751 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1752 {
1753 ide_hwif_t *hwif = HWIF(drive);
1754 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1755 u32 *timings, *timings2;
1756 u32 timing_local[2];
1757 int ret;
1758
1759 /* which drive is it ? */
1760 timings = &pmif->timings[drive->select.b.unit & 0x01];
1761 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1762
1763 /* Copy timings to local image */
1764 timing_local[0] = *timings;
1765 timing_local[1] = *timings2;
1766
1767 /* Calculate timings for interface */
1768 if (pmif->kind == controller_un_ata6
1769 || pmif->kind == controller_k2_ata6)
1770 ret = set_timings_udma_ata6( &timing_local[0],
1771 &timing_local[1],
1772 mode);
1773 else if (pmif->kind == controller_sh_ata6)
1774 ret = set_timings_udma_shasta( &timing_local[0],
1775 &timing_local[1],
1776 mode);
1777 else
1778 ret = set_timings_udma_ata4(&timing_local[0], mode);
1779 if (ret)
1780 return 0;
1781
1782 /* Set feature on drive */
1783 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1784 ret = pmac_ide_do_setfeature(drive, mode);
1785 if (ret) {
1786 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1787 return 0;
1788 }
1789
1790 /* Apply timings to controller */
1791 *timings = timing_local[0];
1792 *timings2 = timing_local[1];
1793
1794 /* Set speed info in drive */
1795 drive->current_speed = mode;
1796 if (!drive->init_speed)
1797 drive->init_speed = mode;
1798
1799 return 1;
1800 }
1801
1802 /*
1803 * Check what is the best DMA timing setting for the drive and
1804 * call appropriate functions to apply it.
1805 */
1806 static int
1807 pmac_ide_dma_check(ide_drive_t *drive)
1808 {
1809 struct hd_driveid *id = drive->id;
1810 ide_hwif_t *hwif = HWIF(drive);
1811 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1812 int enable = 1;
1813 int map;
1814 drive->using_dma = 0;
1815
1816 if (drive->media == ide_floppy)
1817 enable = 0;
1818 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1819 enable = 0;
1820 if (__ide_dma_bad_drive(drive))
1821 enable = 0;
1822
1823 if (enable) {
1824 short mode;
1825
1826 map = XFER_MWDMA;
1827 if (pmif->kind == controller_kl_ata4
1828 || pmif->kind == controller_un_ata6
1829 || pmif->kind == controller_k2_ata6
1830 || pmif->kind == controller_sh_ata6) {
1831 map |= XFER_UDMA;
1832 if (pmif->cable_80) {
1833 map |= XFER_UDMA_66;
1834 if (pmif->kind == controller_un_ata6 ||
1835 pmif->kind == controller_k2_ata6 ||
1836 pmif->kind == controller_sh_ata6)
1837 map |= XFER_UDMA_100;
1838 if (pmif->kind == controller_sh_ata6)
1839 map |= XFER_UDMA_133;
1840 }
1841 }
1842 mode = ide_find_best_mode(drive, map);
1843 if (mode & XFER_UDMA)
1844 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1845 else if (mode & XFER_MWDMA)
1846 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1847 hwif->OUTB(0, IDE_CONTROL_REG);
1848 /* Apply settings to controller */
1849 pmac_ide_do_update_timings(drive);
1850 }
1851 return 0;
1852 }
1853
1854 /*
1855 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1856 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1857 */
1858 static int
1859 pmac_ide_dma_setup(ide_drive_t *drive)
1860 {
1861 ide_hwif_t *hwif = HWIF(drive);
1862 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1863 struct request *rq = HWGROUP(drive)->rq;
1864 u8 unit = (drive->select.b.unit & 0x01);
1865 u8 ata4;
1866
1867 if (pmif == NULL)
1868 return 1;
1869 ata4 = (pmif->kind == controller_kl_ata4);
1870
1871 if (!pmac_ide_build_dmatable(drive, rq)) {
1872 ide_map_sg(drive, rq);
1873 return 1;
1874 }
1875
1876 /* Apple adds 60ns to wrDataSetup on reads */
1877 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1878 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1879 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1880 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1881 }
1882
1883 drive->waiting_for_dma = 1;
1884
1885 return 0;
1886 }
1887
1888 static void
1889 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1890 {
1891 /* issue cmd to drive */
1892 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1893 }
1894
1895 /*
1896 * Kick the DMA controller into life after the DMA command has been issued
1897 * to the drive.
1898 */
1899 static void
1900 pmac_ide_dma_start(ide_drive_t *drive)
1901 {
1902 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1903 volatile struct dbdma_regs __iomem *dma;
1904
1905 dma = pmif->dma_regs;
1906
1907 writel((RUN << 16) | RUN, &dma->control);
1908 /* Make sure it gets to the controller right now */
1909 (void)readl(&dma->control);
1910 }
1911
1912 /*
1913 * After a DMA transfer, make sure the controller is stopped
1914 */
1915 static int
1916 pmac_ide_dma_end (ide_drive_t *drive)
1917 {
1918 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1919 volatile struct dbdma_regs __iomem *dma;
1920 u32 dstat;
1921
1922 if (pmif == NULL)
1923 return 0;
1924 dma = pmif->dma_regs;
1925
1926 drive->waiting_for_dma = 0;
1927 dstat = readl(&dma->status);
1928 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1929 pmac_ide_destroy_dmatable(drive);
1930 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1931 * in theory, but with ATAPI decices doing buffer underruns, that would
1932 * cause us to disable DMA, which isn't what we want
1933 */
1934 return (dstat & (RUN|DEAD)) != RUN;
1935 }
1936
1937 /*
1938 * Check out that the interrupt we got was for us. We can't always know this
1939 * for sure with those Apple interfaces (well, we could on the recent ones but
1940 * that's not implemented yet), on the other hand, we don't have shared interrupts
1941 * so it's not really a problem
1942 */
1943 static int
1944 pmac_ide_dma_test_irq (ide_drive_t *drive)
1945 {
1946 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1947 volatile struct dbdma_regs __iomem *dma;
1948 unsigned long status, timeout;
1949
1950 if (pmif == NULL)
1951 return 0;
1952 dma = pmif->dma_regs;
1953
1954 /* We have to things to deal with here:
1955 *
1956 * - The dbdma won't stop if the command was started
1957 * but completed with an error without transferring all
1958 * datas. This happens when bad blocks are met during
1959 * a multi-block transfer.
1960 *
1961 * - The dbdma fifo hasn't yet finished flushing to
1962 * to system memory when the disk interrupt occurs.
1963 *
1964 */
1965
1966 /* If ACTIVE is cleared, the STOP command have passed and
1967 * transfer is complete.
1968 */
1969 status = readl(&dma->status);
1970 if (!(status & ACTIVE))
1971 return 1;
1972 if (!drive->waiting_for_dma)
1973 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1974 called while not waiting\n", HWIF(drive)->index);
1975
1976 /* If dbdma didn't execute the STOP command yet, the
1977 * active bit is still set. We consider that we aren't
1978 * sharing interrupts (which is hopefully the case with
1979 * those controllers) and so we just try to flush the
1980 * channel for pending data in the fifo
1981 */
1982 udelay(1);
1983 writel((FLUSH << 16) | FLUSH, &dma->control);
1984 timeout = 0;
1985 for (;;) {
1986 udelay(1);
1987 status = readl(&dma->status);
1988 if ((status & FLUSH) == 0)
1989 break;
1990 if (++timeout > 100) {
1991 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1992 timeout flushing channel\n", HWIF(drive)->index);
1993 break;
1994 }
1995 }
1996 return 1;
1997 }
1998
1999 static void pmac_ide_dma_host_off(ide_drive_t *drive)
2000 {
2001 }
2002
2003 static void pmac_ide_dma_host_on(ide_drive_t *drive)
2004 {
2005 }
2006
2007 static int
2008 pmac_ide_dma_lostirq (ide_drive_t *drive)
2009 {
2010 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2011 volatile struct dbdma_regs __iomem *dma;
2012 unsigned long status;
2013
2014 if (pmif == NULL)
2015 return 0;
2016 dma = pmif->dma_regs;
2017
2018 status = readl(&dma->status);
2019 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
2020 return 0;
2021 }
2022
2023 /*
2024 * Allocate the data structures needed for using DMA with an interface
2025 * and fill the proper list of functions pointers
2026 */
2027 static void __init
2028 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2029 {
2030 /* We won't need pci_dev if we switch to generic consistent
2031 * DMA routines ...
2032 */
2033 if (hwif->pci_dev == NULL)
2034 return;
2035 /*
2036 * Allocate space for the DBDMA commands.
2037 * The +2 is +1 for the stop command and +1 to allow for
2038 * aligning the start address to a multiple of 16 bytes.
2039 */
2040 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2041 hwif->pci_dev,
2042 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2043 &hwif->dmatable_dma);
2044 if (pmif->dma_table_cpu == NULL) {
2045 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2046 hwif->name);
2047 return;
2048 }
2049
2050 hwif->dma_off_quietly = &ide_dma_off_quietly;
2051 hwif->ide_dma_on = &__ide_dma_on;
2052 hwif->ide_dma_check = &pmac_ide_dma_check;
2053 hwif->dma_setup = &pmac_ide_dma_setup;
2054 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2055 hwif->dma_start = &pmac_ide_dma_start;
2056 hwif->ide_dma_end = &pmac_ide_dma_end;
2057 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2058 hwif->dma_host_off = &pmac_ide_dma_host_off;
2059 hwif->dma_host_on = &pmac_ide_dma_host_on;
2060 hwif->ide_dma_timeout = &__ide_dma_timeout;
2061 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2062
2063 hwif->atapi_dma = 1;
2064 switch(pmif->kind) {
2065 case controller_sh_ata6:
2066 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2067 hwif->mwdma_mask = 0x07;
2068 hwif->swdma_mask = 0x00;
2069 break;
2070 case controller_un_ata6:
2071 case controller_k2_ata6:
2072 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2073 hwif->mwdma_mask = 0x07;
2074 hwif->swdma_mask = 0x00;
2075 break;
2076 case controller_kl_ata4:
2077 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2078 hwif->mwdma_mask = 0x07;
2079 hwif->swdma_mask = 0x00;
2080 break;
2081 default:
2082 hwif->ultra_mask = 0x00;
2083 hwif->mwdma_mask = 0x07;
2084 hwif->swdma_mask = 0x00;
2085 break;
2086 }
2087 }
2088
2089 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Tomato firmware and modifications.