release/src-rt-6.x/linux/linux-2.6/drivers/i2c/busses/i2c-ibm_iic.c

   1 /*
   2  * drivers/i2c/busses/i2c-ibm_iic.c
   3  *
   4  * Support for the IIC peripheral on IBM PPC 4xx
   5  *
   6  * Copyright (c) 2003, 2004 Zultys Technologies.
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  *
   9  * Based on original work by
  10  *      Ian DaSilva  <idasilva@mvista.com>
  11  *      Armin Kuster <akuster@mvista.com>
  12  *      Matt Porter  <mporter@mvista.com>
  13  *
  14  *      Copyright 2000-2003 MontaVista Software Inc.
  15  *
  16  * Original driver version was highly leveraged from i2c-elektor.c
  17  *
  18  *      Copyright 1995-97 Simon G. Vogl
  19  *                1998-99 Hans Berglund
  20  *
  21  *      With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
  22  *      and even Frodo Looijaard <frodol@dds.nl>
  23  *
  24  * This program is free software; you can redistribute  it and/or modify it
  25  * under  the terms of  the GNU General  Public License as published by the
  26  * Free Software Foundation;  either version 2 of the  License, or (at your
  27  * option) any later version.
  28  *
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/ioport.h>
  34 #include <linux/delay.h>
  35 #include <linux/slab.h>
  36 #include <linux/init.h>
  37 #include <linux/interrupt.h>
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40 #include <linux/i2c.h>
  41 #include <linux/i2c-id.h>
  42 #include <asm/ocp.h>
  43 #include <asm/ibm4xx.h>
  44
  45 #include "i2c-ibm_iic.h"
  46
  47 #define DRIVER_VERSION "2.1"
  48
  49 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
  50 MODULE_LICENSE("GPL");
  51
  52 static int iic_force_poll;
  53 module_param(iic_force_poll, bool, 0);
  54 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
  55
  56 static int iic_force_fast;
  57 module_param(iic_force_fast, bool, 0);
  58 MODULE_PARM_DESC(iic_fast_poll, "Force fast mode (400 kHz)");
  59
  60 #define DBG_LEVEL 0
  61
  62 #ifdef DBG
  63 #undef DBG
  64 #endif
  65
  66 #ifdef DBG2
  67 #undef DBG2
  68 #endif
  69
  70 #if DBG_LEVEL > 0
  71 #  define DBG(f,x...)   printk(KERN_DEBUG "ibm-iic" f, ##x)
  72 #else
  73 #  define DBG(f,x...)   ((void)0)
  74 #endif
  75 #if DBG_LEVEL > 1
  76 #  define DBG2(f,x...)  DBG(f, ##x)
  77 #else
  78 #  define DBG2(f,x...)  ((void)0)
  79 #endif
  80 #if DBG_LEVEL > 2
  81 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
  82 {
  83         volatile struct iic_regs __iomem *iic = dev->vaddr;
  84         printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
  85         printk(KERN_DEBUG "  cntl     = 0x%02x, mdcntl = 0x%02x\n"
  86                KERN_DEBUG "  sts      = 0x%02x, extsts = 0x%02x\n"
  87                KERN_DEBUG "  clkdiv   = 0x%02x, xfrcnt = 0x%02x\n"
  88                KERN_DEBUG "  xtcntlss = 0x%02x, directcntl = 0x%02x\n",
  89                 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
  90                 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
  91                 in_8(&iic->xtcntlss), in_8(&iic->directcntl));
  92 }
  93 #  define DUMP_REGS(h,dev)      dump_iic_regs((h),(dev))
  94 #else
  95 #  define DUMP_REGS(h,dev)      ((void)0)
  96 #endif
  97
  98 /* Bus timings (in ns) for bit-banging */
  99 static struct i2c_timings {
 100         unsigned int hd_sta;
 101         unsigned int su_sto;
 102         unsigned int low;
 103         unsigned int high;
 104         unsigned int buf;
 105 } timings [] = {
 106 /* Standard mode (100 KHz) */
 107 {
 108         .hd_sta = 4000,
 109         .su_sto = 4000,
 110         .low    = 4700,
 111         .high   = 4000,
 112         .buf    = 4700,
 113 },
 114 /* Fast mode (400 KHz) */
 115 {
 116         .hd_sta = 600,
 117         .su_sto = 600,
 118         .low    = 1300,
 119         .high   = 600,
 120         .buf    = 1300,
 121 }};
 122
 123 /* Enable/disable interrupt generation */
 124 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
 125 {
 126         out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
 127 }
 128
 129 /*
 130  * Initialize IIC interface.
 131  */
 132 static void iic_dev_init(struct ibm_iic_private* dev)
 133 {
 134         volatile struct iic_regs __iomem *iic = dev->vaddr;
 135
 136         DBG("%d: init\n", dev->idx);
 137
 138         /* Clear master address */
 139         out_8(&iic->lmadr, 0);
 140         out_8(&iic->hmadr, 0);
 141
 142         /* Clear slave address */
 143         out_8(&iic->lsadr, 0);
 144         out_8(&iic->hsadr, 0);
 145
 146         /* Clear status & extended status */
 147         out_8(&iic->sts, STS_SCMP | STS_IRQA);
 148         out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
 149                             | EXTSTS_ICT | EXTSTS_XFRA);
 150
 151         /* Set clock divider */
 152         out_8(&iic->clkdiv, dev->clckdiv);
 153
 154         /* Clear transfer count */
 155         out_8(&iic->xfrcnt, 0);
 156
 157         /* Clear extended control and status */
 158         out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
 159                             | XTCNTLSS_SWS);
 160
 161         /* Clear control register */
 162         out_8(&iic->cntl, 0);
 163
 164         /* Enable interrupts if possible */
 165         iic_interrupt_mode(dev, dev->irq >= 0);
 166
 167         /* Set mode control */
 168         out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
 169                             | (dev->fast_mode ? MDCNTL_FSM : 0));
 170
 171         DUMP_REGS("iic_init", dev);
 172 }
 173
 174 /*
 175  * Reset IIC interface
 176  */
 177 static void iic_dev_reset(struct ibm_iic_private* dev)
 178 {
 179         volatile struct iic_regs __iomem *iic = dev->vaddr;
 180         int i;
 181         u8 dc;
 182
 183         DBG("%d: soft reset\n", dev->idx);
 184         DUMP_REGS("reset", dev);
 185
 186         /* Place chip in the reset state */
 187         out_8(&iic->xtcntlss, XTCNTLSS_SRST);
 188
 189         /* Check if bus is free */
 190         dc = in_8(&iic->directcntl);
 191         if (!DIRCTNL_FREE(dc)){
 192                 DBG("%d: trying to regain bus control\n", dev->idx);
 193
 194                 /* Try to set bus free state */
 195                 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 196
 197                 /* Wait until we regain bus control */
 198                 for (i = 0; i < 100; ++i){
 199                         dc = in_8(&iic->directcntl);
 200                         if (DIRCTNL_FREE(dc))
 201                                 break;
 202
 203                         /* Toggle SCL line */
 204                         dc ^= DIRCNTL_SCC;
 205                         out_8(&iic->directcntl, dc);
 206                         udelay(10);
 207                         dc ^= DIRCNTL_SCC;
 208                         out_8(&iic->directcntl, dc);
 209
 210                         /* be nice */
 211                         cond_resched();
 212                 }
 213         }
 214
 215         /* Remove reset */
 216         out_8(&iic->xtcntlss, 0);
 217
 218         /* Reinitialize interface */
 219         iic_dev_init(dev);
 220 }
 221
 222 /*
 223  * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
 224  */
 225
 226 /* Wait for SCL and/or SDA to be high */
 227 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
 228 {
 229         unsigned long x = jiffies + HZ / 28 + 2;
 230         while ((in_8(&iic->directcntl) & mask) != mask){
 231                 if (unlikely(time_after(jiffies, x)))
 232                         return -1;
 233                 cond_resched();
 234         }
 235         return 0;
 236 }
 237
 238 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
 239 {
 240         volatile struct iic_regs __iomem *iic = dev->vaddr;
 241         const struct i2c_timings* t = &timings[dev->fast_mode ? 1 : 0];
 242         u8 mask, v, sda;
 243         int i, res;
 244
 245         /* Only 7-bit addresses are supported */
 246         if (unlikely(p->flags & I2C_M_TEN)){
 247                 DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
 248                         dev->idx);
 249                 return -EINVAL;
 250         }
 251
 252         DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
 253
 254         /* Reset IIC interface */
 255         out_8(&iic->xtcntlss, XTCNTLSS_SRST);
 256
 257         /* Wait for bus to become free */
 258         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 259         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
 260                 goto err;
 261         ndelay(t->buf);
 262
 263         /* START */
 264         out_8(&iic->directcntl, DIRCNTL_SCC);
 265         sda = 0;
 266         ndelay(t->hd_sta);
 267
 268         /* Send address */
 269         v = (u8)((p->addr << 1) | ((p->flags & I2C_M_RD) ? 1 : 0));
 270         for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
 271                 out_8(&iic->directcntl, sda);
 272                 ndelay(t->low / 2);
 273                 sda = (v & mask) ? DIRCNTL_SDAC : 0;
 274                 out_8(&iic->directcntl, sda);
 275                 ndelay(t->low / 2);
 276
 277                 out_8(&iic->directcntl, DIRCNTL_SCC | sda);
 278                 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 279                         goto err;
 280                 ndelay(t->high);
 281         }
 282
 283         /* ACK */
 284         out_8(&iic->directcntl, sda);
 285         ndelay(t->low / 2);
 286         out_8(&iic->directcntl, DIRCNTL_SDAC);
 287         ndelay(t->low / 2);
 288         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 289         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 290                 goto err;
 291         res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
 292         ndelay(t->high);
 293
 294         /* STOP */
 295         out_8(&iic->directcntl, 0);
 296         ndelay(t->low);
 297         out_8(&iic->directcntl, DIRCNTL_SCC);
 298         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
 299                 goto err;
 300         ndelay(t->su_sto);
 301         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
 302
 303         ndelay(t->buf);
 304
 305         DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
 306 out:
 307         /* Remove reset */
 308         out_8(&iic->xtcntlss, 0);
 309
 310         /* Reinitialize interface */
 311         iic_dev_init(dev);
 312
 313         return res;
 314 err:
 315         DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
 316         res = -EREMOTEIO;
 317         goto out;
 318 }
 319
 320 /*
 321  * IIC interrupt handler
 322  */
 323 static irqreturn_t iic_handler(int irq, void *dev_id)
 324 {
 325         struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
 326         volatile struct iic_regs __iomem *iic = dev->vaddr;
 327
 328         DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
 329              dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
 330
 331         /* Acknowledge IRQ and wakeup iic_wait_for_tc */
 332         out_8(&iic->sts, STS_IRQA | STS_SCMP);
 333         wake_up_interruptible(&dev->wq);
 334
 335         return IRQ_HANDLED;
 336 }
 337
 338 /*
 339  * Get master transfer result and clear errors if any.
 340  * Returns the number of actually transferred bytes or error (<0)
 341  */
 342 static int iic_xfer_result(struct ibm_iic_private* dev)
 343 {
 344         volatile struct iic_regs __iomem *iic = dev->vaddr;
 345
 346         if (unlikely(in_8(&iic->sts) & STS_ERR)){
 347                 DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
 348                         in_8(&iic->extsts));
 349
 350                 /* Clear errors and possible pending IRQs */
 351                 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
 352                         EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
 353
 354                 /* Flush master data buffer */
 355                 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
 356
 357                 /* Is bus free?
 358                  * If error happened during combined xfer
 359                  * IIC interface is usually stuck in some strange
 360                  * state, the only way out - soft reset.
 361                  */
 362                 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 363                         DBG("%d: bus is stuck, resetting\n", dev->idx);
 364                         iic_dev_reset(dev);
 365                 }
 366                 return -EREMOTEIO;
 367         }
 368         else
 369                 return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
 370 }
 371
 372 /*
 373  * Try to abort active transfer.
 374  */
 375 static void iic_abort_xfer(struct ibm_iic_private* dev)
 376 {
 377         volatile struct iic_regs __iomem *iic = dev->vaddr;
 378         unsigned long x;
 379
 380         DBG("%d: iic_abort_xfer\n", dev->idx);
 381
 382         out_8(&iic->cntl, CNTL_HMT);
 383
 384         /*
 385          * Wait for the abort command to complete.
 386          * It's not worth to be optimized, just poll (timeout >= 1 tick)
 387          */
 388         x = jiffies + 2;
 389         while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 390                 if (time_after(jiffies, x)){
 391                         DBG("%d: abort timeout, resetting...\n", dev->idx);
 392                         iic_dev_reset(dev);
 393                         return;
 394                 }
 395                 schedule();
 396         }
 397
 398         /* Just to clear errors */
 399         iic_xfer_result(dev);
 400 }
 401
 402 /*
 403  * Wait for master transfer to complete.
 404  * It puts current process to sleep until we get interrupt or timeout expires.
 405  * Returns the number of transferred bytes or error (<0)
 406  */
 407 static int iic_wait_for_tc(struct ibm_iic_private* dev){
 408
 409         volatile struct iic_regs __iomem *iic = dev->vaddr;
 410         int ret = 0;
 411
 412         if (dev->irq >= 0){
 413                 /* Interrupt mode */
 414                 ret = wait_event_interruptible_timeout(dev->wq,
 415                         !(in_8(&iic->sts) & STS_PT), dev->adap.timeout * HZ);
 416
 417                 if (unlikely(ret < 0))
 418                         DBG("%d: wait interrupted\n", dev->idx);
 419                 else if (unlikely(in_8(&iic->sts) & STS_PT)){
 420                         DBG("%d: wait timeout\n", dev->idx);
 421                         ret = -ETIMEDOUT;
 422                 }
 423         }
 424         else {
 425                 /* Polling mode */
 426                 unsigned long x = jiffies + dev->adap.timeout * HZ;
 427
 428                 while (in_8(&iic->sts) & STS_PT){
 429                         if (unlikely(time_after(jiffies, x))){
 430                                 DBG("%d: poll timeout\n", dev->idx);
 431                                 ret = -ETIMEDOUT;
 432                                 break;
 433                         }
 434
 435                         if (unlikely(signal_pending(current))){
 436                                 DBG("%d: poll interrupted\n", dev->idx);
 437                                 ret = -ERESTARTSYS;
 438                                 break;
 439                         }
 440                         schedule();
 441                 }
 442         }
 443
 444         if (unlikely(ret < 0))
 445                 iic_abort_xfer(dev);
 446         else
 447                 ret = iic_xfer_result(dev);
 448
 449         DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
 450
 451         return ret;
 452 }
 453
 454 /*
 455  * Low level master transfer routine
 456  */
 457 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
 458                           int combined_xfer)
 459 {
 460         volatile struct iic_regs __iomem *iic = dev->vaddr;
 461         char* buf = pm->buf;
 462         int i, j, loops, ret = 0;
 463         int len = pm->len;
 464
 465         u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
 466         if (pm->flags & I2C_M_RD)
 467                 cntl |= CNTL_RW;
 468
 469         loops = (len + 3) / 4;
 470         for (i = 0; i < loops; ++i, len -= 4){
 471                 int count = len > 4 ? 4 : len;
 472                 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
 473
 474                 if (!(cntl & CNTL_RW))
 475                         for (j = 0; j < count; ++j)
 476                                 out_8((void __iomem *)&iic->mdbuf, *buf++);
 477
 478                 if (i < loops - 1)
 479                         cmd |= CNTL_CHT;
 480                 else if (combined_xfer)
 481                         cmd |= CNTL_RPST;
 482
 483                 DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
 484
 485                 /* Start transfer */
 486                 out_8(&iic->cntl, cmd);
 487
 488                 /* Wait for completion */
 489                 ret = iic_wait_for_tc(dev);
 490
 491                 if (unlikely(ret < 0))
 492                         break;
 493                 else if (unlikely(ret != count)){
 494                         DBG("%d: xfer_bytes, requested %d, transfered %d\n",
 495                                 dev->idx, count, ret);
 496
 497                         /* If it's not a last part of xfer, abort it */
 498                         if (combined_xfer || (i < loops - 1))
 499                                 iic_abort_xfer(dev);
 500
 501                         ret = -EREMOTEIO;
 502                         break;
 503                 }
 504
 505                 if (cntl & CNTL_RW)
 506                         for (j = 0; j < count; ++j)
 507                                 *buf++ = in_8((void __iomem *)&iic->mdbuf);
 508         }
 509
 510         return ret > 0 ? 0 : ret;
 511 }
 512
 513 /*
 514  * Set target slave address for master transfer
 515  */
 516 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
 517 {
 518         volatile struct iic_regs __iomem *iic = dev->vaddr;
 519         u16 addr = msg->addr;
 520
 521         DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
 522                 addr, msg->flags & I2C_M_TEN ? 10 : 7);
 523
 524         if (msg->flags & I2C_M_TEN){
 525             out_8(&iic->cntl, CNTL_AMD);
 526             out_8(&iic->lmadr, addr);
 527             out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
 528         }
 529         else {
 530             out_8(&iic->cntl, 0);
 531             out_8(&iic->lmadr, addr << 1);
 532         }
 533 }
 534
 535 static inline int iic_invalid_address(const struct i2c_msg* p)
 536 {
 537         return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
 538 }
 539
 540 static inline int iic_address_neq(const struct i2c_msg* p1,
 541                                   const struct i2c_msg* p2)
 542 {
 543         return (p1->addr != p2->addr)
 544                 || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
 545 }
 546
 547 /*
 548  * Generic master transfer entrypoint.
 549  * Returns the number of processed messages or error (<0)
 550  */
 551 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 552 {
 553         struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
 554         volatile struct iic_regs __iomem *iic = dev->vaddr;
 555         int i, ret = 0;
 556
 557         DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
 558
 559         if (!num)
 560                 return 0;
 561
 562         /* Check the sanity of the passed messages.
 563          * Uhh, generic i2c layer is more suitable place for such code...
 564          */
 565         if (unlikely(iic_invalid_address(&msgs[0]))){
 566                 DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
 567                         msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
 568                 return -EINVAL;
 569         }
 570         for (i = 0; i < num; ++i){
 571                 if (unlikely(msgs[i].len <= 0)){
 572                         if (num == 1 && !msgs[0].len){
 573                                 /* Special case for I2C_SMBUS_QUICK emulation.
 574                                  * IBM IIC doesn't support 0-length transactions
 575                                  * so we have to emulate them using bit-banging.
 576                                  */
 577                                 return iic_smbus_quick(dev, &msgs[0]);
 578                         }
 579                         DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
 580                                 msgs[i].len, i);
 581                         return -EINVAL;
 582                 }
 583                 if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
 584                         DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
 585                         return -EINVAL;
 586                 }
 587         }
 588
 589         /* Check bus state */
 590         if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
 591                 DBG("%d: iic_xfer, bus is not free\n", dev->idx);
 592
 593                 /* Usually it means something serious has happend.
 594                  * We *cannot* have unfinished previous transfer
 595                  * so it doesn't make any sense to try to stop it.
 596                  * Probably we were not able to recover from the
 597                  * previous error.
 598                  * The only *reasonable* thing I can think of here
 599                  * is soft reset.  --ebs
 600                  */
 601                 iic_dev_reset(dev);
 602
 603                 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
 604                         DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
 605                         return -EREMOTEIO;
 606                 }
 607         }
 608         else {
 609                 /* Flush master data buffer (just in case) */
 610                 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
 611         }
 612
 613         /* Load slave address */
 614         iic_address(dev, &msgs[0]);
 615
 616         /* Do real transfer */
 617         for (i = 0; i < num && !ret; ++i)
 618                 ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
 619
 620         return ret < 0 ? ret : num;
 621 }
 622
 623 static u32 iic_func(struct i2c_adapter *adap)
 624 {
 625         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 626 }
 627
 628 static const struct i2c_algorithm iic_algo = {
 629         .master_xfer    = iic_xfer,
 630         .functionality  = iic_func
 631 };
 632
 633 /*
 634  * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
 635  */
 636 static inline u8 iic_clckdiv(unsigned int opb)
 637 {
 638         /* Compatibility kludge, should go away after all cards
 639          * are fixed to fill correct value for opbfreq.
 640          * Previous driver version used hardcoded divider value 4,
 641          * it corresponds to OPB frequency from the range (40, 50] MHz
 642          */
 643         if (!opb){
 644                 printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
 645                         " fix your board specific setup\n");
 646                 opb = 50000000;
 647         }
 648
 649         /* Convert to MHz */
 650         opb /= 1000000;
 651
 652         if (opb < 20 || opb > 150){
 653                 printk(KERN_CRIT "ibm-iic: invalid OPB clock frequency %u MHz\n",
 654                         opb);
 655                 opb = opb < 20 ? 20 : 150;
 656         }
 657         return (u8)((opb + 9) / 10 - 1);
 658 }
 659
 660 /*
 661  * Register single IIC interface
 662  */
 663 static int __devinit iic_probe(struct ocp_device *ocp){
 664
 665         struct ibm_iic_private* dev;
 666         struct i2c_adapter* adap;
 667         struct ocp_func_iic_data* iic_data = ocp->def->additions;
 668         int ret;
 669
 670         if (!iic_data)
 671                 printk(KERN_WARNING"ibm-iic%d: missing additional data!\n",
 672                         ocp->def->index);
 673
 674         if (!(dev = kzalloc(sizeof(*dev), GFP_KERNEL))) {
 675                 printk(KERN_CRIT "ibm-iic%d: failed to allocate device data\n",
 676                         ocp->def->index);
 677                 return -ENOMEM;
 678         }
 679
 680         dev->idx = ocp->def->index;
 681         ocp_set_drvdata(ocp, dev);
 682
 683         if (!request_mem_region(ocp->def->paddr, sizeof(struct iic_regs),
 684                                 "ibm_iic")) {
 685                 ret = -EBUSY;
 686                 goto fail1;
 687         }
 688
 689         if (!(dev->vaddr = ioremap(ocp->def->paddr, sizeof(struct iic_regs)))){
 690                 printk(KERN_CRIT "ibm-iic%d: failed to ioremap device registers\n",
 691                         dev->idx);
 692                 ret = -ENXIO;
 693                 goto fail2;
 694         }
 695
 696         init_waitqueue_head(&dev->wq);
 697
 698         dev->irq = iic_force_poll ? -1 : ocp->def->irq;
 699         if (dev->irq >= 0){
 700                 /* Disable interrupts until we finish initialization,
 701                    assumes level-sensitive IRQ setup...
 702                  */
 703                 iic_interrupt_mode(dev, 0);
 704                 if (request_irq(dev->irq, iic_handler, 0, "IBM IIC", dev)){
 705                         printk(KERN_ERR "ibm-iic%d: request_irq %d failed\n",
 706                                 dev->idx, dev->irq);
 707                         /* Fallback to the polling mode */
 708                         dev->irq = -1;
 709                 }
 710         }
 711
 712         if (dev->irq < 0)
 713                 printk(KERN_WARNING "ibm-iic%d: using polling mode\n",
 714                         dev->idx);
 715
 716         /* Board specific settings */
 717         dev->fast_mode = iic_force_fast ? 1 : (iic_data ? iic_data->fast_mode : 0);
 718
 719         /* clckdiv is the same for *all* IIC interfaces,
 720          * but I'd rather make a copy than introduce another global. --ebs
 721          */
 722         dev->clckdiv = iic_clckdiv(ocp_sys_info.opb_bus_freq);
 723         DBG("%d: clckdiv = %d\n", dev->idx, dev->clckdiv);
 724
 725         /* Initialize IIC interface */
 726         iic_dev_init(dev);
 727
 728         /* Register it with i2c layer */
 729         adap = &dev->adap;
 730         adap->dev.parent = &ocp->dev;
 731         strcpy(adap->name, "IBM IIC");
 732         i2c_set_adapdata(adap, dev);
 733         adap->id = I2C_HW_OCP;
 734         adap->class = I2C_CLASS_HWMON;
 735         adap->algo = &iic_algo;
 736         adap->client_register = NULL;
 737         adap->client_unregister = NULL;
 738         adap->timeout = 1;
 739         adap->retries = 1;
 740
 741         if ((ret = i2c_add_adapter(adap)) != 0){
 742                 printk(KERN_CRIT "ibm-iic%d: failed to register i2c adapter\n",
 743                         dev->idx);
 744                 goto fail;
 745         }
 746
 747         printk(KERN_INFO "ibm-iic%d: using %s mode\n", dev->idx,
 748                 dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
 749
 750         return 0;
 751
 752 fail:
 753         if (dev->irq >= 0){
 754                 iic_interrupt_mode(dev, 0);
 755                 free_irq(dev->irq, dev);
 756         }
 757
 758         iounmap(dev->vaddr);
 759 fail2:
 760         release_mem_region(ocp->def->paddr, sizeof(struct iic_regs));
 761 fail1:
 762         ocp_set_drvdata(ocp, NULL);
 763         kfree(dev);
 764         return ret;
 765 }
 766
 767 /*
 768  * Cleanup initialized IIC interface
 769  */
 770 static void __devexit iic_remove(struct ocp_device *ocp)
 771 {
 772         struct ibm_iic_private* dev = (struct ibm_iic_private*)ocp_get_drvdata(ocp);
 773         BUG_ON(dev == NULL);
 774         if (i2c_del_adapter(&dev->adap)){
 775                 printk(KERN_CRIT "ibm-iic%d: failed to delete i2c adapter :(\n",
 776                         dev->idx);
 777                 /* That's *very* bad, just shutdown IRQ ... */
 778                 if (dev->irq >= 0){
 779                     iic_interrupt_mode(dev, 0);
 780                     free_irq(dev->irq, dev);
 781                     dev->irq = -1;
 782                 }
 783         } else {
 784                 if (dev->irq >= 0){
 785                     iic_interrupt_mode(dev, 0);
 786                     free_irq(dev->irq, dev);
 787                 }
 788                 iounmap(dev->vaddr);
 789                 release_mem_region(ocp->def->paddr, sizeof(struct iic_regs));
 790                 kfree(dev);
 791         }
 792 }
 793
 794 static struct ocp_device_id ibm_iic_ids[] __devinitdata =
 795 {
 796         { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_IIC },
 797         { .vendor = OCP_VENDOR_INVALID }
 798 };
 799
 800 MODULE_DEVICE_TABLE(ocp, ibm_iic_ids);
 801
 802 static struct ocp_driver ibm_iic_driver =
 803 {
 804         .name           = "iic",
 805         .id_table       = ibm_iic_ids,
 806         .probe          = iic_probe,
 807         .remove         = __devexit_p(iic_remove),
 808 #if defined(CONFIG_PM)
 809         .suspend        = NULL,
 810         .resume         = NULL,
 811 #endif
 812 };
 813
 814 static int __init iic_init(void)
 815 {
 816         printk(KERN_INFO "IBM IIC driver v" DRIVER_VERSION "\n");
 817         return ocp_register_driver(&ibm_iic_driver);
 818 }
 819
 820 static void __exit iic_exit(void)
 821 {
 822         ocp_unregister_driver(&ibm_iic_driver);
 823 }
 824
 825 module_init(iic_init);
 826 module_exit(iic_exit);