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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / char / drm / radeon_drv.h
blob54f49ef4bef084b8ae816a301596b8833c58e961
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 */
101 #define DRIVER_MAJOR 1
102 #define DRIVER_MINOR 27
103 #define DRIVER_PATCHLEVEL 0
104
105 /*
106 * Radeon chip families
107 */
108 enum radeon_family {
109 CHIP_R100,
110 CHIP_RV100,
111 CHIP_RS100,
112 CHIP_RV200,
113 CHIP_RS200,
114 CHIP_R200,
115 CHIP_RV250,
116 CHIP_RS300,
117 CHIP_RV280,
118 CHIP_R300,
119 CHIP_R350,
120 CHIP_RV350,
121 CHIP_RV380,
122 CHIP_R420,
123 CHIP_RV410,
124 CHIP_RS400,
125 CHIP_LAST,
126 };
127
128 enum radeon_cp_microcode_version {
129 UCODE_R100,
130 UCODE_R200,
131 UCODE_R300,
132 };
133
134 /*
135 * Chip flags
136 */
137 enum radeon_chip_flags {
138 RADEON_FAMILY_MASK = 0x0000ffffUL,
139 RADEON_FLAGS_MASK = 0xffff0000UL,
140 RADEON_IS_MOBILITY = 0x00010000UL,
141 RADEON_IS_IGP = 0x00020000UL,
142 RADEON_SINGLE_CRTC = 0x00040000UL,
143 RADEON_IS_AGP = 0x00080000UL,
144 RADEON_HAS_HIERZ = 0x00100000UL,
145 RADEON_IS_PCIE = 0x00200000UL,
146 RADEON_NEW_MEMMAP = 0x00400000UL,
147 RADEON_IS_PCI = 0x00800000UL,
148 RADEON_IS_IGPGART = 0x01000000UL,
149 };
150
151 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
152 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
153 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
154
155 typedef struct drm_radeon_freelist {
156 unsigned int age;
157 drm_buf_t *buf;
158 struct drm_radeon_freelist *next;
159 struct drm_radeon_freelist *prev;
160 } drm_radeon_freelist_t;
161
162 typedef struct drm_radeon_ring_buffer {
163 u32 *start;
164 u32 *end;
165 int size;
166 int size_l2qw;
167
168 u32 tail;
169 u32 tail_mask;
170 int space;
171
172 int high_mark;
173 } drm_radeon_ring_buffer_t;
174
175 typedef struct drm_radeon_depth_clear_t {
176 u32 rb3d_cntl;
177 u32 rb3d_zstencilcntl;
178 u32 se_cntl;
179 } drm_radeon_depth_clear_t;
180
181 struct drm_radeon_driver_file_fields {
182 int64_t radeon_fb_delta;
183 };
184
185 struct mem_block {
186 struct mem_block *next;
187 struct mem_block *prev;
188 int start;
189 int size;
190 DRMFILE filp; /* 0: free, -1: heap, other: real files */
191 };
192
193 struct radeon_surface {
194 int refcount;
195 u32 lower;
196 u32 upper;
197 u32 flags;
198 };
199
200 struct radeon_virt_surface {
201 int surface_index;
202 u32 lower;
203 u32 upper;
204 u32 flags;
205 DRMFILE filp;
206 };
207
208 typedef struct drm_radeon_private {
209 drm_radeon_ring_buffer_t ring;
210 drm_radeon_sarea_t *sarea_priv;
211
212 u32 fb_location;
213 u32 fb_size;
214 int new_memmap;
215
216 int gart_size;
217 u32 gart_vm_start;
218 unsigned long gart_buffers_offset;
219
220 int cp_mode;
221 int cp_running;
222
223 drm_radeon_freelist_t *head;
224 drm_radeon_freelist_t *tail;
225 int last_buf;
226 volatile u32 *scratch;
227 int writeback_works;
228
229 int usec_timeout;
230
231 int microcode_version;
232
233 struct {
234 u32 boxes;
235 int freelist_timeouts;
236 int freelist_loops;
237 int requested_bufs;
238 int last_frame_reads;
239 int last_clear_reads;
240 int clears;
241 int texture_uploads;
242 } stats;
243
244 int do_boxes;
245 int page_flipping;
246
247 u32 color_fmt;
248 unsigned int front_offset;
249 unsigned int front_pitch;
250 unsigned int back_offset;
251 unsigned int back_pitch;
252
253 u32 depth_fmt;
254 unsigned int depth_offset;
255 unsigned int depth_pitch;
256
257 u32 front_pitch_offset;
258 u32 back_pitch_offset;
259 u32 depth_pitch_offset;
260
261 drm_radeon_depth_clear_t depth_clear;
262
263 unsigned long ring_offset;
264 unsigned long ring_rptr_offset;
265 unsigned long buffers_offset;
266 unsigned long gart_textures_offset;
267
268 drm_local_map_t *sarea;
269 drm_local_map_t *mmio;
270 drm_local_map_t *cp_ring;
271 drm_local_map_t *ring_rptr;
272 drm_local_map_t *gart_textures;
273
274 struct mem_block *gart_heap;
275 struct mem_block *fb_heap;
276
277 /* SW interrupt */
278 wait_queue_head_t swi_queue;
279 atomic_t swi_emitted;
280
281 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
282 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
283
284 unsigned long pcigart_offset;
285 unsigned int pcigart_offset_set;
286 drm_ati_pcigart_info gart_info;
287
288 u32 scratch_ages[5];
289
290 /* starting from here on, data is preserved accross an open */
291 uint32_t flags; /* see radeon_chip_flags */
292 } drm_radeon_private_t;
293
294 typedef struct drm_radeon_buf_priv {
295 u32 age;
296 } drm_radeon_buf_priv_t;
297
298 typedef struct drm_radeon_kcmd_buffer {
299 int bufsz;
300 char *buf;
301 int nbox;
302 drm_clip_rect_t __user *boxes;
303 } drm_radeon_kcmd_buffer_t;
304
305 extern int radeon_no_wb;
306 extern drm_ioctl_desc_t radeon_ioctls[];
307 extern int radeon_max_ioctl;
308
309 /* Check whether the given hardware address is inside the framebuffer or the
310 * GART area.
311 */
312 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
313 u64 off)
314 {
315 u32 fb_start = dev_priv->fb_location;
316 u32 fb_end = fb_start + dev_priv->fb_size - 1;
317 u32 gart_start = dev_priv->gart_vm_start;
318 u32 gart_end = gart_start + dev_priv->gart_size - 1;
319
320 return ((off >= fb_start && off <= fb_end) ||
321 (off >= gart_start && off <= gart_end));
322 }
323
324 /* radeon_cp.c */
325 extern int radeon_cp_init(DRM_IOCTL_ARGS);
326 extern int radeon_cp_start(DRM_IOCTL_ARGS);
327 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
328 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
329 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
330 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
331 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
332 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
333 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
334
335 extern void radeon_freelist_reset(drm_device_t * dev);
336 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
337
338 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
339
340 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
341
342 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
343 extern int radeon_presetup(struct drm_device *dev);
344 extern int radeon_driver_postcleanup(struct drm_device *dev);
345
346 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
347 extern int radeon_mem_free(DRM_IOCTL_ARGS);
348 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
349 extern void radeon_mem_takedown(struct mem_block **heap);
350 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
351
352 /* radeon_irq.c */
353 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
354 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
355
356 extern void radeon_do_release(drm_device_t * dev);
357 extern int radeon_driver_vblank_wait(drm_device_t * dev,
358 unsigned int *sequence);
359 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
360 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
361 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
362 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
363
364 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
365 extern int radeon_driver_unload(struct drm_device *dev);
366 extern int radeon_driver_firstopen(struct drm_device *dev);
367 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
368 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
369 extern void radeon_driver_lastclose(drm_device_t * dev);
370 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
371 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
372 unsigned long arg);
373
374 /* r300_cmdbuf.c */
375 extern void r300_init_reg_flags(void);
376
377 extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
378 drm_file_t * filp_priv,
379 drm_radeon_kcmd_buffer_t * cmdbuf);
380
381 /* Flags for stats.boxes
382 */
383 #define RADEON_BOX_DMA_IDLE 0x1
384 #define RADEON_BOX_RING_FULL 0x2
385 #define RADEON_BOX_FLIP 0x4
386 #define RADEON_BOX_WAIT_IDLE 0x8
387 #define RADEON_BOX_TEXTURE_LOAD 0x10
388
389 /* Register definitions, register access macros and drmAddMap constants
390 * for Radeon kernel driver.
391 */
392
393 #define RADEON_AGP_COMMAND 0x0f60
394 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
395 # define RADEON_AGP_ENABLE (1<<8)
396 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
397 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
398 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
399 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
400 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
401 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
402 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
403
404 #define RADEON_BUS_CNTL 0x0030
405 # define RADEON_BUS_MASTER_DIS (1 << 6)
406
407 #define RADEON_CLOCK_CNTL_DATA 0x000c
408 # define RADEON_PLL_WR_EN (1 << 7)
409 #define RADEON_CLOCK_CNTL_INDEX 0x0008
410 #define RADEON_CONFIG_APER_SIZE 0x0108
411 #define RADEON_CONFIG_MEMSIZE 0x00f8
412 #define RADEON_CRTC_OFFSET 0x0224
413 #define RADEON_CRTC_OFFSET_CNTL 0x0228
414 # define RADEON_CRTC_TILE_EN (1 << 15)
415 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
416 #define RADEON_CRTC2_OFFSET 0x0324
417 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
418
419 #define RADEON_PCIE_INDEX 0x0030
420 #define RADEON_PCIE_DATA 0x0034
421 #define RADEON_PCIE_TX_GART_CNTL 0x10
422 # define RADEON_PCIE_TX_GART_EN (1 << 0)
423 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
424 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
425 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
426 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
427 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
428 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
429 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
430 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
431 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
432 #define RADEON_PCIE_TX_GART_BASE 0x13
433 #define RADEON_PCIE_TX_GART_START_LO 0x14
434 #define RADEON_PCIE_TX_GART_START_HI 0x15
435 #define RADEON_PCIE_TX_GART_END_LO 0x16
436 #define RADEON_PCIE_TX_GART_END_HI 0x17
437
438 #define RADEON_IGPGART_INDEX 0x168
439 #define RADEON_IGPGART_DATA 0x16c
440 #define RADEON_IGPGART_UNK_18 0x18
441 #define RADEON_IGPGART_CTRL 0x2b
442 #define RADEON_IGPGART_BASE_ADDR 0x2c
443 #define RADEON_IGPGART_FLUSH 0x2e
444 #define RADEON_IGPGART_ENABLE 0x38
445 #define RADEON_IGPGART_UNK_39 0x39
446
447 #define RADEON_MPP_TB_CONFIG 0x01c0
448 #define RADEON_MEM_CNTL 0x0140
449 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
450 #define RADEON_AGP_BASE 0x0170
451
452 #define RADEON_RB3D_COLOROFFSET 0x1c40
453 #define RADEON_RB3D_COLORPITCH 0x1c48
454
455 #define RADEON_SRC_X_Y 0x1590
456
457 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
458 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
459 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
460 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
461 # define RADEON_GMC_BRUSH_NONE (15 << 4)
462 # define RADEON_GMC_DST_16BPP (4 << 8)
463 # define RADEON_GMC_DST_24BPP (5 << 8)
464 # define RADEON_GMC_DST_32BPP (6 << 8)
465 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
466 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
467 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
468 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
469 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
470 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
471 # define RADEON_ROP3_S 0x00cc0000
472 # define RADEON_ROP3_P 0x00f00000
473 #define RADEON_DP_WRITE_MASK 0x16cc
474 #define RADEON_SRC_PITCH_OFFSET 0x1428
475 #define RADEON_DST_PITCH_OFFSET 0x142c
476 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
477 # define RADEON_DST_TILE_LINEAR (0 << 30)
478 # define RADEON_DST_TILE_MACRO (1 << 30)
479 # define RADEON_DST_TILE_MICRO (2 << 30)
480 # define RADEON_DST_TILE_BOTH (3 << 30)
481
482 #define RADEON_SCRATCH_REG0 0x15e0
483 #define RADEON_SCRATCH_REG1 0x15e4
484 #define RADEON_SCRATCH_REG2 0x15e8
485 #define RADEON_SCRATCH_REG3 0x15ec
486 #define RADEON_SCRATCH_REG4 0x15f0
487 #define RADEON_SCRATCH_REG5 0x15f4
488 #define RADEON_SCRATCH_UMSK 0x0770
489 #define RADEON_SCRATCH_ADDR 0x0774
490
491 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
492
493 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
494 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
495 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
496
497 #define RADEON_GEN_INT_CNTL 0x0040
498 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
499 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
500 # define RADEON_SW_INT_ENABLE (1 << 25)
501
502 #define RADEON_GEN_INT_STATUS 0x0044
503 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
504 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
505 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
506 # define RADEON_SW_INT_TEST (1 << 25)
507 # define RADEON_SW_INT_TEST_ACK (1 << 25)
508 # define RADEON_SW_INT_FIRE (1 << 26)
509
510 #define RADEON_HOST_PATH_CNTL 0x0130
511 # define RADEON_HDP_SOFT_RESET (1 << 26)
512 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
513 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
514
515 #define RADEON_ISYNC_CNTL 0x1724
516 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
517 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
518 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
519 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
520 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
521 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
522
523 #define RADEON_RBBM_GUICNTL 0x172c
524 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
525 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
526 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
527 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
528
529 #define RADEON_MC_AGP_LOCATION 0x014c
530 #define RADEON_MC_FB_LOCATION 0x0148
531 #define RADEON_MCLK_CNTL 0x0012
532 # define RADEON_FORCEON_MCLKA (1 << 16)
533 # define RADEON_FORCEON_MCLKB (1 << 17)
534 # define RADEON_FORCEON_YCLKA (1 << 18)
535 # define RADEON_FORCEON_YCLKB (1 << 19)
536 # define RADEON_FORCEON_MC (1 << 20)
537 # define RADEON_FORCEON_AIC (1 << 21)
538
539 #define RADEON_PP_BORDER_COLOR_0 0x1d40
540 #define RADEON_PP_BORDER_COLOR_1 0x1d44
541 #define RADEON_PP_BORDER_COLOR_2 0x1d48
542 #define RADEON_PP_CNTL 0x1c38
543 # define RADEON_SCISSOR_ENABLE (1 << 1)
544 #define RADEON_PP_LUM_MATRIX 0x1d00
545 #define RADEON_PP_MISC 0x1c14
546 #define RADEON_PP_ROT_MATRIX_0 0x1d58
547 #define RADEON_PP_TXFILTER_0 0x1c54
548 #define RADEON_PP_TXOFFSET_0 0x1c5c
549 #define RADEON_PP_TXFILTER_1 0x1c6c
550 #define RADEON_PP_TXFILTER_2 0x1c84
551
552 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
553 # define RADEON_RB2D_DC_FLUSH (3 << 0)
554 # define RADEON_RB2D_DC_FREE (3 << 2)
555 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
556 # define RADEON_RB2D_DC_BUSY (1 << 31)
557 #define RADEON_RB3D_CNTL 0x1c3c
558 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
559 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
560 # define RADEON_DITHER_ENABLE (1 << 2)
561 # define RADEON_ROUND_ENABLE (1 << 3)
562 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
563 # define RADEON_DITHER_INIT (1 << 5)
564 # define RADEON_ROP_ENABLE (1 << 6)
565 # define RADEON_STENCIL_ENABLE (1 << 7)
566 # define RADEON_Z_ENABLE (1 << 8)
567 # define RADEON_ZBLOCK16 (1 << 15)
568 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
569 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
570 #define RADEON_RB3D_DEPTHPITCH 0x1c28
571 #define RADEON_RB3D_PLANEMASK 0x1d84
572 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
573 #define RADEON_RB3D_ZCACHE_MODE 0x3250
574 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
575 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
576 # define RADEON_RB3D_ZC_FREE (1 << 2)
577 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
578 # define RADEON_RB3D_ZC_BUSY (1 << 31)
579 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
580 # define RADEON_RB3D_DC_FLUSH (3 << 0)
581 # define RADEON_RB3D_DC_FREE (3 << 2)
582 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
583 # define RADEON_RB3D_DC_BUSY (1 << 31)
584 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
585 # define RADEON_Z_TEST_MASK (7 << 4)
586 # define RADEON_Z_TEST_ALWAYS (7 << 4)
587 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
588 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
589 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
590 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
591 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
592 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
593 # define RADEON_FORCE_Z_DIRTY (1 << 29)
594 # define RADEON_Z_WRITE_ENABLE (1 << 30)
595 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
596 #define RADEON_RBBM_SOFT_RESET 0x00f0
597 # define RADEON_SOFT_RESET_CP (1 << 0)
598 # define RADEON_SOFT_RESET_HI (1 << 1)
599 # define RADEON_SOFT_RESET_SE (1 << 2)
600 # define RADEON_SOFT_RESET_RE (1 << 3)
601 # define RADEON_SOFT_RESET_PP (1 << 4)
602 # define RADEON_SOFT_RESET_E2 (1 << 5)
603 # define RADEON_SOFT_RESET_RB (1 << 6)
604 # define RADEON_SOFT_RESET_HDP (1 << 7)
605 #define RADEON_RBBM_STATUS 0x0e40
606 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
607 # define RADEON_RBBM_ACTIVE (1 << 31)
608 #define RADEON_RE_LINE_PATTERN 0x1cd0
609 #define RADEON_RE_MISC 0x26c4
610 #define RADEON_RE_TOP_LEFT 0x26c0
611 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
612 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
613 #define RADEON_RE_STIPPLE_DATA 0x1ccc
614
615 #define RADEON_SCISSOR_TL_0 0x1cd8
616 #define RADEON_SCISSOR_BR_0 0x1cdc
617 #define RADEON_SCISSOR_TL_1 0x1ce0
618 #define RADEON_SCISSOR_BR_1 0x1ce4
619 #define RADEON_SCISSOR_TL_2 0x1ce8
620 #define RADEON_SCISSOR_BR_2 0x1cec
621 #define RADEON_SE_COORD_FMT 0x1c50
622 #define RADEON_SE_CNTL 0x1c4c
623 # define RADEON_FFACE_CULL_CW (0 << 0)
624 # define RADEON_BFACE_SOLID (3 << 1)
625 # define RADEON_FFACE_SOLID (3 << 3)
626 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
627 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
628 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
629 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
630 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
631 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
632 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
633 # define RADEON_FOG_SHADE_FLAT (1 << 14)
634 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
635 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
636 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
637 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
638 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
639 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
640 #define RADEON_SE_CNTL_STATUS 0x2140
641 #define RADEON_SE_LINE_WIDTH 0x1db8
642 #define RADEON_SE_VPORT_XSCALE 0x1d98
643 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
644 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
645 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
646 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
647 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
648 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
649 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
650 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
651 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
652 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
653 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
654 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
655 #define RADEON_SURFACE_CNTL 0x0b00
656 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
657 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
658 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
659 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
660 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
661 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
662 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
663 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
664 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
665 #define RADEON_SURFACE0_INFO 0x0b0c
666 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
667 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
668 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
669 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
670 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
671 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
672 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
673 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
674 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
675 #define RADEON_SURFACE1_INFO 0x0b1c
676 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
677 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
678 #define RADEON_SURFACE2_INFO 0x0b2c
679 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
680 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
681 #define RADEON_SURFACE3_INFO 0x0b3c
682 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
683 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
684 #define RADEON_SURFACE4_INFO 0x0b4c
685 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
686 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
687 #define RADEON_SURFACE5_INFO 0x0b5c
688 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
689 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
690 #define RADEON_SURFACE6_INFO 0x0b6c
691 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
692 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
693 #define RADEON_SURFACE7_INFO 0x0b7c
694 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
695 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
696 #define RADEON_SW_SEMAPHORE 0x013c
697
698 #define RADEON_WAIT_UNTIL 0x1720
699 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
700 # define RADEON_WAIT_2D_IDLE (1 << 14)
701 # define RADEON_WAIT_3D_IDLE (1 << 15)
702 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
703 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
704 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
705
706 #define RADEON_RB3D_ZMASKOFFSET 0x3234
707 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
708 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
709 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
710
711 /* CP registers */
712 #define RADEON_CP_ME_RAM_ADDR 0x07d4
713 #define RADEON_CP_ME_RAM_RADDR 0x07d8
714 #define RADEON_CP_ME_RAM_DATAH 0x07dc
715 #define RADEON_CP_ME_RAM_DATAL 0x07e0
716
717 #define RADEON_CP_RB_BASE 0x0700
718 #define RADEON_CP_RB_CNTL 0x0704
719 # define RADEON_BUF_SWAP_32BIT (2 << 16)
720 # define RADEON_RB_NO_UPDATE (1 << 27)
721 #define RADEON_CP_RB_RPTR_ADDR 0x070c
722 #define RADEON_CP_RB_RPTR 0x0710
723 #define RADEON_CP_RB_WPTR 0x0714
724
725 #define RADEON_CP_RB_WPTR_DELAY 0x0718
726 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
727 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
728
729 #define RADEON_CP_IB_BASE 0x0738
730
731 #define RADEON_CP_CSQ_CNTL 0x0740
732 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
733 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
734 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
735 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
736 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
737 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
738 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
739
740 #define RADEON_AIC_CNTL 0x01d0
741 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
742 #define RADEON_AIC_STAT 0x01d4
743 #define RADEON_AIC_PT_BASE 0x01d8
744 #define RADEON_AIC_LO_ADDR 0x01dc
745 #define RADEON_AIC_HI_ADDR 0x01e0
746 #define RADEON_AIC_TLB_ADDR 0x01e4
747 #define RADEON_AIC_TLB_DATA 0x01e8
748
749 /* CP command packets */
750 #define RADEON_CP_PACKET0 0x00000000
751 # define RADEON_ONE_REG_WR (1 << 15)
752 #define RADEON_CP_PACKET1 0x40000000
753 #define RADEON_CP_PACKET2 0x80000000
754 #define RADEON_CP_PACKET3 0xC0000000
755 # define RADEON_CP_NOP 0x00001000
756 # define RADEON_CP_NEXT_CHAR 0x00001900
757 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
758 # define RADEON_CP_SET_SCISSORS 0x00001E00
759 /* GEN_INDX_PRIM is unsupported starting with R300 */
760 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
761 # define RADEON_WAIT_FOR_IDLE 0x00002600
762 # define RADEON_3D_DRAW_VBUF 0x00002800
763 # define RADEON_3D_DRAW_IMMD 0x00002900
764 # define RADEON_3D_DRAW_INDX 0x00002A00
765 # define RADEON_CP_LOAD_PALETTE 0x00002C00
766 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
767 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
768 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
769 # define RADEON_3D_CLEAR_ZMASK 0x00003200
770 # define RADEON_CP_INDX_BUFFER 0x00003300
771 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
772 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
773 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
774 # define RADEON_3D_CLEAR_HIZ 0x00003700
775 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
776 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
777 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
778 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
779 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
780
781 #define RADEON_CP_PACKET_MASK 0xC0000000
782 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
783 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
784 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
785 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
786
787 #define RADEON_VTX_Z_PRESENT (1 << 31)
788 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
789
790 #define RADEON_PRIM_TYPE_NONE (0 << 0)
791 #define RADEON_PRIM_TYPE_POINT (1 << 0)
792 #define RADEON_PRIM_TYPE_LINE (2 << 0)
793 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
794 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
795 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
796 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
797 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
798 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
799 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
800 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
801 #define RADEON_PRIM_TYPE_MASK 0xf
802 #define RADEON_PRIM_WALK_IND (1 << 4)
803 #define RADEON_PRIM_WALK_LIST (2 << 4)
804 #define RADEON_PRIM_WALK_RING (3 << 4)
805 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
806 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
807 #define RADEON_MAOS_ENABLE (1 << 7)
808 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
809 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
810 #define RADEON_NUM_VERTICES_SHIFT 16
811
812 #define RADEON_COLOR_FORMAT_CI8 2
813 #define RADEON_COLOR_FORMAT_ARGB1555 3
814 #define RADEON_COLOR_FORMAT_RGB565 4
815 #define RADEON_COLOR_FORMAT_ARGB8888 6
816 #define RADEON_COLOR_FORMAT_RGB332 7
817 #define RADEON_COLOR_FORMAT_RGB8 9
818 #define RADEON_COLOR_FORMAT_ARGB4444 15
819
820 #define RADEON_TXFORMAT_I8 0
821 #define RADEON_TXFORMAT_AI88 1
822 #define RADEON_TXFORMAT_RGB332 2
823 #define RADEON_TXFORMAT_ARGB1555 3
824 #define RADEON_TXFORMAT_RGB565 4
825 #define RADEON_TXFORMAT_ARGB4444 5
826 #define RADEON_TXFORMAT_ARGB8888 6
827 #define RADEON_TXFORMAT_RGBA8888 7
828 #define RADEON_TXFORMAT_Y8 8
829 #define RADEON_TXFORMAT_VYUY422 10
830 #define RADEON_TXFORMAT_YVYU422 11
831 #define RADEON_TXFORMAT_DXT1 12
832 #define RADEON_TXFORMAT_DXT23 14
833 #define RADEON_TXFORMAT_DXT45 15
834
835 #define R200_PP_TXCBLEND_0 0x2f00
836 #define R200_PP_TXCBLEND_1 0x2f10
837 #define R200_PP_TXCBLEND_2 0x2f20
838 #define R200_PP_TXCBLEND_3 0x2f30
839 #define R200_PP_TXCBLEND_4 0x2f40
840 #define R200_PP_TXCBLEND_5 0x2f50
841 #define R200_PP_TXCBLEND_6 0x2f60
842 #define R200_PP_TXCBLEND_7 0x2f70
843 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
844 #define R200_PP_TFACTOR_0 0x2ee0
845 #define R200_SE_VTX_FMT_0 0x2088
846 #define R200_SE_VAP_CNTL 0x2080
847 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
848 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
849 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
850 #define R200_PP_TXFILTER_5 0x2ca0
851 #define R200_PP_TXFILTER_4 0x2c80
852 #define R200_PP_TXFILTER_3 0x2c60
853 #define R200_PP_TXFILTER_2 0x2c40
854 #define R200_PP_TXFILTER_1 0x2c20
855 #define R200_PP_TXFILTER_0 0x2c00
856 #define R200_PP_TXOFFSET_5 0x2d78
857 #define R200_PP_TXOFFSET_4 0x2d60
858 #define R200_PP_TXOFFSET_3 0x2d48
859 #define R200_PP_TXOFFSET_2 0x2d30
860 #define R200_PP_TXOFFSET_1 0x2d18
861 #define R200_PP_TXOFFSET_0 0x2d00
862
863 #define R200_PP_CUBIC_FACES_0 0x2c18
864 #define R200_PP_CUBIC_FACES_1 0x2c38
865 #define R200_PP_CUBIC_FACES_2 0x2c58
866 #define R200_PP_CUBIC_FACES_3 0x2c78
867 #define R200_PP_CUBIC_FACES_4 0x2c98
868 #define R200_PP_CUBIC_FACES_5 0x2cb8
869 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
870 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
871 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
872 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
873 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
874 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
875 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
876 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
877 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
878 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
879 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
880 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
881 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
882 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
883 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
884 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
885 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
886 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
887 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
888 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
889 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
890 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
891 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
892 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
893 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
894 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
895 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
896 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
897 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
898 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
899
900 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
901 #define R200_SE_VTE_CNTL 0x20b0
902 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
903 #define R200_PP_TAM_DEBUG3 0x2d9c
904 #define R200_PP_CNTL_X 0x2cc4
905 #define R200_SE_VAP_CNTL_STATUS 0x2140
906 #define R200_RE_SCISSOR_TL_0 0x1cd8
907 #define R200_RE_SCISSOR_TL_1 0x1ce0
908 #define R200_RE_SCISSOR_TL_2 0x1ce8
909 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
910 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
911 #define R200_SE_VTX_STATE_CNTL 0x2180
912 #define R200_RE_POINTSIZE 0x2648
913 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
914
915 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
916 #define RADEON_PP_TEX_SIZE_1 0x1d0c
917 #define RADEON_PP_TEX_SIZE_2 0x1d14
918
919 #define RADEON_PP_CUBIC_FACES_0 0x1d24
920 #define RADEON_PP_CUBIC_FACES_1 0x1d28
921 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
922 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
923 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
924 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
925
926 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
927
928 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
929 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
930 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
931 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
932 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
933 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
934 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
935 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
936 #define R200_3D_DRAW_IMMD_2 0xC0003500
937 #define R200_SE_VTX_FMT_1 0x208c
938 #define R200_RE_CNTL 0x1c50
939
940 #define R200_RB3D_BLENDCOLOR 0x3218
941
942 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
943
944 #define R200_PP_TRI_PERF 0x2cf8
945
946 #define R200_PP_AFS_0 0x2f80
947 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
948
949 #define R200_VAP_PVS_CNTL_1 0x22D0
950
951 /* Constants */
952 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
953
954 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
955 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
956 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
957 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
958 #define RADEON_LAST_DISPATCH 1
959
960 #define RADEON_MAX_VB_AGE 0x7fffffff
961 #define RADEON_MAX_VB_VERTS (0xffff)
962
963 #define RADEON_RING_HIGH_MARK 128
964
965 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
966
967 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
968 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
969 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
970 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
971
972 #define RADEON_WRITE_PLL( addr, val ) \
973 do { \
974 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
975 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
976 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
977 } while (0)
978
979 #define RADEON_WRITE_IGPGART( addr, val ) \
980 do { \
981 RADEON_WRITE( RADEON_IGPGART_INDEX, \
982 ((addr) & 0x7f) | (1 << 8)); \
983 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
984 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
985 } while (0)
986
987 #define RADEON_WRITE_PCIE( addr, val ) \
988 do { \
989 RADEON_WRITE8( RADEON_PCIE_INDEX, \
990 ((addr) & 0xff)); \
991 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
992 } while (0)
993
994 #define CP_PACKET0( reg, n ) \
995 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
996 #define CP_PACKET0_TABLE( reg, n ) \
997 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
998 #define CP_PACKET1( reg0, reg1 ) \
999 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1000 #define CP_PACKET2() \
1001 (RADEON_CP_PACKET2)
1002 #define CP_PACKET3( pkt, n ) \
1003 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1004
1005 /* ================================================================
1006 * Engine control helper macros
1007 */
1008
1009 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1010 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1011 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1012 RADEON_WAIT_HOST_IDLECLEAN) ); \
1013 } while (0)
1014
1015 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1016 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1017 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1018 RADEON_WAIT_HOST_IDLECLEAN) ); \
1019 } while (0)
1020
1021 #define RADEON_WAIT_UNTIL_IDLE() do { \
1022 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1023 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1024 RADEON_WAIT_3D_IDLECLEAN | \
1025 RADEON_WAIT_HOST_IDLECLEAN) ); \
1026 } while (0)
1027
1028 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1029 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1030 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1031 } while (0)
1032
1033 #define RADEON_FLUSH_CACHE() do { \
1034 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1035 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1036 } while (0)
1037
1038 #define RADEON_PURGE_CACHE() do { \
1039 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1040 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1041 } while (0)
1042
1043 #define RADEON_FLUSH_ZCACHE() do { \
1044 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1045 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1046 } while (0)
1047
1048 #define RADEON_PURGE_ZCACHE() do { \
1049 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1050 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1051 } while (0)
1052
1053 /* ================================================================
1054 * Misc helper macros
1055 */
1056
1057 /* Perfbox functionality only.
1058 */
1059 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1060 do { \
1061 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1062 u32 head = GET_RING_HEAD( dev_priv ); \
1063 if (head == dev_priv->ring.tail) \
1064 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1065 } \
1066 } while (0)
1067
1068 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1069 do { \
1070 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1071 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1072 int __ret = radeon_do_cp_idle( dev_priv ); \
1073 if ( __ret ) return __ret; \
1074 sarea_priv->last_dispatch = 0; \
1075 radeon_freelist_reset( dev ); \
1076 } \
1077 } while (0)
1078
1079 #define RADEON_DISPATCH_AGE( age ) do { \
1080 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1081 OUT_RING( age ); \
1082 } while (0)
1083
1084 #define RADEON_FRAME_AGE( age ) do { \
1085 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1086 OUT_RING( age ); \
1087 } while (0)
1088
1089 #define RADEON_CLEAR_AGE( age ) do { \
1090 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1091 OUT_RING( age ); \
1092 } while (0)
1093
1094 /* ================================================================
1095 * Ring control
1096 */
1097
1098 #define RADEON_VERBOSE 0
1099
1100 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1101
1102 #define BEGIN_RING( n ) do { \
1103 if ( RADEON_VERBOSE ) { \
1104 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1105 n, __FUNCTION__ ); \
1106 } \
1107 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1108 COMMIT_RING(); \
1109 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1110 } \
1111 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1112 ring = dev_priv->ring.start; \
1113 write = dev_priv->ring.tail; \
1114 mask = dev_priv->ring.tail_mask; \
1115 } while (0)
1116
1117 #define ADVANCE_RING() do { \
1118 if ( RADEON_VERBOSE ) { \
1119 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1120 write, dev_priv->ring.tail ); \
1121 } \
1122 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1123 DRM_ERROR( \
1124 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1125 ((dev_priv->ring.tail + _nr) & mask), \
1126 write, __LINE__); \
1127 } else \
1128 dev_priv->ring.tail = write; \
1129 } while (0)
1130
1131 #define COMMIT_RING() do { \
1132 /* Flush writes to ring */ \
1133 DRM_MEMORYBARRIER(); \
1134 GET_RING_HEAD( dev_priv ); \
1135 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1136 /* read from PCI bus to ensure correct posting */ \
1137 RADEON_READ( RADEON_CP_RB_RPTR ); \
1138 } while (0)
1139
1140 #define OUT_RING( x ) do { \
1141 if ( RADEON_VERBOSE ) { \
1142 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1143 (unsigned int)(x), write ); \
1144 } \
1145 ring[write++] = (x); \
1146 write &= mask; \
1147 } while (0)
1148
1149 #define OUT_RING_REG( reg, val ) do { \
1150 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1151 OUT_RING( val ); \
1152 } while (0)
1153
1154 #define OUT_RING_TABLE( tab, sz ) do { \
1155 int _size = (sz); \
1156 int *_tab = (int *)(tab); \
1157 \
1158 if (write + _size > mask) { \
1159 int _i = (mask+1) - write; \
1160 _size -= _i; \
1161 while (_i > 0 ) { \
1162 *(int *)(ring + write) = *_tab++; \
1163 write++; \
1164 _i--; \
1165 } \
1166 write = 0; \
1167 _tab += _i; \
1168 } \
1169 while (_size > 0) { \
1170 *(ring + write) = *_tab++; \
1171 write++; \
1172 _size--; \
1173 } \
1174 write &= mask; \
1175 } while (0)
1176
1177 #endif /* __RADEON_DRV_H__ */
Tomato firmware and modifications.