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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / char / drm / r128_cce.c
blob1014602c43a71910e4f7eba390e123c47670c3f2
1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 */
4 /*
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "r128_drm.h"
35 #include "r128_drv.h"
36
37 #define R128_FIFO_DEBUG 0
38
39 /* CCE microcode (from ATI) */
40 static u32 r128_cce_microcode[] = {
41 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
42 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
43 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
44 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
45 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
46 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
47 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
48 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
49 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
50 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
51 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
52 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
53 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
54 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
55 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
56 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
57 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
58 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
59 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
60 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
61 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
62 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
63 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
64 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
65 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
66 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
67 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
68 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
69 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
70 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
71 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
72 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
73 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
74 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
75 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
76 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
82 };
83
84 static int R128_READ_PLL(drm_device_t * dev, int addr)
85 {
86 drm_r128_private_t *dev_priv = dev->dev_private;
87
88 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
89 return R128_READ(R128_CLOCK_CNTL_DATA);
90 }
91
92 #if R128_FIFO_DEBUG
93 static void r128_status(drm_r128_private_t * dev_priv)
94 {
95 printk("GUI_STAT = 0x%08x\n",
96 (unsigned int)R128_READ(R128_GUI_STAT));
97 printk("PM4_STAT = 0x%08x\n",
98 (unsigned int)R128_READ(R128_PM4_STAT));
99 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
100 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
101 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
102 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
103 printk("PM4_MICRO_CNTL = 0x%08x\n",
104 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
105 printk("PM4_BUFFER_CNTL = 0x%08x\n",
106 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
107 }
108 #endif
109
110 /* ================================================================
111 * Engine, FIFO control
112 */
113
114 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
115 {
116 u32 tmp;
117 int i;
118
119 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
120 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
121
122 for (i = 0; i < dev_priv->usec_timeout; i++) {
123 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
124 return 0;
125 }
126 DRM_UDELAY(1);
127 }
128
129 #if R128_FIFO_DEBUG
130 DRM_ERROR("failed!\n");
131 #endif
132 return DRM_ERR(EBUSY);
133 }
134
135 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
136 {
137 int i;
138
139 for (i = 0; i < dev_priv->usec_timeout; i++) {
140 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
141 if (slots >= entries)
142 return 0;
143 DRM_UDELAY(1);
144 }
145
146 #if R128_FIFO_DEBUG
147 DRM_ERROR("failed!\n");
148 #endif
149 return DRM_ERR(EBUSY);
150 }
151
152 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
153 {
154 int i, ret;
155
156 ret = r128_do_wait_for_fifo(dev_priv, 64);
157 if (ret)
158 return ret;
159
160 for (i = 0; i < dev_priv->usec_timeout; i++) {
161 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
162 r128_do_pixcache_flush(dev_priv);
163 return 0;
164 }
165 DRM_UDELAY(1);
166 }
167
168 #if R128_FIFO_DEBUG
169 DRM_ERROR("failed!\n");
170 #endif
171 return DRM_ERR(EBUSY);
172 }
173
174 /* ================================================================
175 * CCE control, initialization
176 */
177
178 /* Load the microcode for the CCE */
179 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
180 {
181 int i;
182
183 DRM_DEBUG("\n");
184
185 r128_do_wait_for_idle(dev_priv);
186
187 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
188 for (i = 0; i < 256; i++) {
189 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
190 R128_WRITE(R128_PM4_MICROCODE_DATAL,
191 r128_cce_microcode[i * 2 + 1]);
192 }
193 }
194
195 /* Flush any pending commands to the CCE. This should only be used just
196 * prior to a wait for idle, as it informs the engine that the command
197 * stream is ending.
198 */
199 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
200 {
201 u32 tmp;
202
203 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
204 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
205 }
206
207 /* Wait for the CCE to go idle.
208 */
209 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
210 {
211 int i;
212
213 for (i = 0; i < dev_priv->usec_timeout; i++) {
214 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
215 int pm4stat = R128_READ(R128_PM4_STAT);
216 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
217 dev_priv->cce_fifo_size) &&
218 !(pm4stat & (R128_PM4_BUSY |
219 R128_PM4_GUI_ACTIVE))) {
220 return r128_do_pixcache_flush(dev_priv);
221 }
222 }
223 DRM_UDELAY(1);
224 }
225
226 #if R128_FIFO_DEBUG
227 DRM_ERROR("failed!\n");
228 r128_status(dev_priv);
229 #endif
230 return DRM_ERR(EBUSY);
231 }
232
233 /* Start the Concurrent Command Engine.
234 */
235 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
236 {
237 r128_do_wait_for_idle(dev_priv);
238
239 R128_WRITE(R128_PM4_BUFFER_CNTL,
240 dev_priv->cce_mode | dev_priv->ring.size_l2qw
241 | R128_PM4_BUFFER_CNTL_NOUPDATE);
242 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
243 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
244
245 dev_priv->cce_running = 1;
246 }
247
248 /* Reset the Concurrent Command Engine. This will not flush any pending
249 * commands, so you must wait for the CCE command stream to complete
250 * before calling this routine.
251 */
252 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
253 {
254 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
255 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
256 dev_priv->ring.tail = 0;
257 }
258
259 /* Stop the Concurrent Command Engine. This will not flush any pending
260 * commands, so you must flush the command stream and wait for the CCE
261 * to go idle before calling this routine.
262 */
263 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
264 {
265 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
266 R128_WRITE(R128_PM4_BUFFER_CNTL,
267 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
268
269 dev_priv->cce_running = 0;
270 }
271
272 /* Reset the engine. This will stop the CCE if it is running.
273 */
274 static int r128_do_engine_reset(drm_device_t * dev)
275 {
276 drm_r128_private_t *dev_priv = dev->dev_private;
277 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
278
279 r128_do_pixcache_flush(dev_priv);
280
281 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
282 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
283
284 R128_WRITE_PLL(R128_MCLK_CNTL,
285 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
286
287 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
288
289 /* Taken from the sample code - do not change */
290 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
291 R128_READ(R128_GEN_RESET_CNTL);
292 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
293 R128_READ(R128_GEN_RESET_CNTL);
294
295 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
296 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
297 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
298
299 /* Reset the CCE ring */
300 r128_do_cce_reset(dev_priv);
301
302 /* The CCE is no longer running after an engine reset */
303 dev_priv->cce_running = 0;
304
305 /* Reset any pending vertex, indirect buffers */
306 r128_freelist_reset(dev);
307
308 return 0;
309 }
310
311 static void r128_cce_init_ring_buffer(drm_device_t * dev,
312 drm_r128_private_t * dev_priv)
313 {
314 u32 ring_start;
315 u32 tmp;
316
317 DRM_DEBUG("\n");
318
319 /* The manual (p. 2) says this address is in "VM space". This
320 * means it's an offset from the start of AGP space.
321 */
322 #if __OS_HAS_AGP
323 if (!dev_priv->is_pci)
324 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
325 else
326 #endif
327 ring_start = dev_priv->cce_ring->offset -
328 (unsigned long)dev->sg->virtual;
329
330 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
331
332 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
333 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
334
335 /* Set watermark control */
336 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
337 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
338 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
339 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
340 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
341
342 /* Force read. Why? Because it's in the examples... */
343 R128_READ(R128_PM4_BUFFER_ADDR);
344
345 /* Turn on bus mastering */
346 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
347 R128_WRITE(R128_BUS_CNTL, tmp);
348 }
349
350 static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
351 {
352 drm_r128_private_t *dev_priv;
353
354 DRM_DEBUG("\n");
355
356 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
357 if (dev_priv == NULL)
358 return DRM_ERR(ENOMEM);
359
360 memset(dev_priv, 0, sizeof(drm_r128_private_t));
361
362 dev_priv->is_pci = init->is_pci;
363
364 if (dev_priv->is_pci && !dev->sg) {
365 DRM_ERROR("PCI GART memory not allocated!\n");
366 dev->dev_private = (void *)dev_priv;
367 r128_do_cleanup_cce(dev);
368 return DRM_ERR(EINVAL);
369 }
370
371 dev_priv->usec_timeout = init->usec_timeout;
372 if (dev_priv->usec_timeout < 1 ||
373 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
374 DRM_DEBUG("TIMEOUT problem!\n");
375 dev->dev_private = (void *)dev_priv;
376 r128_do_cleanup_cce(dev);
377 return DRM_ERR(EINVAL);
378 }
379
380 dev_priv->cce_mode = init->cce_mode;
381
382 /* GH: Simple idle check.
383 */
384 atomic_set(&dev_priv->idle_count, 0);
385
386 /* We don't support anything other than bus-mastering ring mode,
387 * but the ring can be in either AGP or PCI space for the ring
388 * read pointer.
389 */
390 if ((init->cce_mode != R128_PM4_192BM) &&
391 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
392 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
393 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
394 DRM_DEBUG("Bad cce_mode!\n");
395 dev->dev_private = (void *)dev_priv;
396 r128_do_cleanup_cce(dev);
397 return DRM_ERR(EINVAL);
398 }
399
400 switch (init->cce_mode) {
401 case R128_PM4_NONPM4:
402 dev_priv->cce_fifo_size = 0;
403 break;
404 case R128_PM4_192PIO:
405 case R128_PM4_192BM:
406 dev_priv->cce_fifo_size = 192;
407 break;
408 case R128_PM4_128PIO_64INDBM:
409 case R128_PM4_128BM_64INDBM:
410 dev_priv->cce_fifo_size = 128;
411 break;
412 case R128_PM4_64PIO_128INDBM:
413 case R128_PM4_64BM_128INDBM:
414 case R128_PM4_64PIO_64VCBM_64INDBM:
415 case R128_PM4_64BM_64VCBM_64INDBM:
416 case R128_PM4_64PIO_64VCPIO_64INDPIO:
417 dev_priv->cce_fifo_size = 64;
418 break;
419 }
420
421 switch (init->fb_bpp) {
422 case 16:
423 dev_priv->color_fmt = R128_DATATYPE_RGB565;
424 break;
425 case 32:
426 default:
427 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
428 break;
429 }
430 dev_priv->front_offset = init->front_offset;
431 dev_priv->front_pitch = init->front_pitch;
432 dev_priv->back_offset = init->back_offset;
433 dev_priv->back_pitch = init->back_pitch;
434
435 switch (init->depth_bpp) {
436 case 16:
437 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
438 break;
439 case 24:
440 case 32:
441 default:
442 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
443 break;
444 }
445 dev_priv->depth_offset = init->depth_offset;
446 dev_priv->depth_pitch = init->depth_pitch;
447 dev_priv->span_offset = init->span_offset;
448
449 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
450 (dev_priv->front_offset >> 5));
451 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
452 (dev_priv->back_offset >> 5));
453 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
454 (dev_priv->depth_offset >> 5) |
455 R128_DST_TILE);
456 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
457 (dev_priv->span_offset >> 5));
458
459 DRM_GETSAREA();
460
461 if (!dev_priv->sarea) {
462 DRM_ERROR("could not find sarea!\n");
463 dev->dev_private = (void *)dev_priv;
464 r128_do_cleanup_cce(dev);
465 return DRM_ERR(EINVAL);
466 }
467
468 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
469 if (!dev_priv->mmio) {
470 DRM_ERROR("could not find mmio region!\n");
471 dev->dev_private = (void *)dev_priv;
472 r128_do_cleanup_cce(dev);
473 return DRM_ERR(EINVAL);
474 }
475 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
476 if (!dev_priv->cce_ring) {
477 DRM_ERROR("could not find cce ring region!\n");
478 dev->dev_private = (void *)dev_priv;
479 r128_do_cleanup_cce(dev);
480 return DRM_ERR(EINVAL);
481 }
482 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
483 if (!dev_priv->ring_rptr) {
484 DRM_ERROR("could not find ring read pointer!\n");
485 dev->dev_private = (void *)dev_priv;
486 r128_do_cleanup_cce(dev);
487 return DRM_ERR(EINVAL);
488 }
489 dev->agp_buffer_token = init->buffers_offset;
490 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
491 if (!dev->agp_buffer_map) {
492 DRM_ERROR("could not find dma buffer region!\n");
493 dev->dev_private = (void *)dev_priv;
494 r128_do_cleanup_cce(dev);
495 return DRM_ERR(EINVAL);
496 }
497
498 if (!dev_priv->is_pci) {
499 dev_priv->agp_textures =
500 drm_core_findmap(dev, init->agp_textures_offset);
501 if (!dev_priv->agp_textures) {
502 DRM_ERROR("could not find agp texture region!\n");
503 dev->dev_private = (void *)dev_priv;
504 r128_do_cleanup_cce(dev);
505 return DRM_ERR(EINVAL);
506 }
507 }
508
509 dev_priv->sarea_priv =
510 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
511 init->sarea_priv_offset);
512
513 #if __OS_HAS_AGP
514 if (!dev_priv->is_pci) {
515 drm_core_ioremap(dev_priv->cce_ring, dev);
516 drm_core_ioremap(dev_priv->ring_rptr, dev);
517 drm_core_ioremap(dev->agp_buffer_map, dev);
518 if (!dev_priv->cce_ring->handle ||
519 !dev_priv->ring_rptr->handle ||
520 !dev->agp_buffer_map->handle) {
521 DRM_ERROR("Could not ioremap agp regions!\n");
522 dev->dev_private = (void *)dev_priv;
523 r128_do_cleanup_cce(dev);
524 return DRM_ERR(ENOMEM);
525 }
526 } else
527 #endif
528 {
529 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
530 dev_priv->ring_rptr->handle =
531 (void *)dev_priv->ring_rptr->offset;
532 dev->agp_buffer_map->handle =
533 (void *)dev->agp_buffer_map->offset;
534 }
535
536 #if __OS_HAS_AGP
537 if (!dev_priv->is_pci)
538 dev_priv->cce_buffers_offset = dev->agp->base;
539 else
540 #endif
541 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
542
543 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
544 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
545 + init->ring_size / sizeof(u32));
546 dev_priv->ring.size = init->ring_size;
547 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
548
549 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
550
551 dev_priv->ring.high_mark = 128;
552
553 dev_priv->sarea_priv->last_frame = 0;
554 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
555
556 dev_priv->sarea_priv->last_dispatch = 0;
557 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
558
559 #if __OS_HAS_AGP
560 if (dev_priv->is_pci) {
561 #endif
562 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
563 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
564 dev_priv->gart_info.addr = NULL;
565 dev_priv->gart_info.bus_addr = 0;
566 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
567 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
568 DRM_ERROR("failed to init PCI GART!\n");
569 dev->dev_private = (void *)dev_priv;
570 r128_do_cleanup_cce(dev);
571 return DRM_ERR(ENOMEM);
572 }
573 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
574 #if __OS_HAS_AGP
575 }
576 #endif
577
578 r128_cce_init_ring_buffer(dev, dev_priv);
579 r128_cce_load_microcode(dev_priv);
580
581 dev->dev_private = (void *)dev_priv;
582
583 r128_do_engine_reset(dev);
584
585 return 0;
586 }
587
588 int r128_do_cleanup_cce(drm_device_t * dev)
589 {
590
591 /* Make sure interrupts are disabled here because the uninstall ioctl
592 * may not have been called from userspace and after dev_private
593 * is freed, it's too late.
594 */
595 if (dev->irq_enabled)
596 drm_irq_uninstall(dev);
597
598 if (dev->dev_private) {
599 drm_r128_private_t *dev_priv = dev->dev_private;
600
601 #if __OS_HAS_AGP
602 if (!dev_priv->is_pci) {
603 if (dev_priv->cce_ring != NULL)
604 drm_core_ioremapfree(dev_priv->cce_ring, dev);
605 if (dev_priv->ring_rptr != NULL)
606 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
607 if (dev->agp_buffer_map != NULL) {
608 drm_core_ioremapfree(dev->agp_buffer_map, dev);
609 dev->agp_buffer_map = NULL;
610 }
611 } else
612 #endif
613 {
614 if (dev_priv->gart_info.bus_addr)
615 if (!drm_ati_pcigart_cleanup(dev,
616 &dev_priv->gart_info))
617 DRM_ERROR
618 ("failed to cleanup PCI GART!\n");
619 }
620
621 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
622 DRM_MEM_DRIVER);
623 dev->dev_private = NULL;
624 }
625
626 return 0;
627 }
628
629 int r128_cce_init(DRM_IOCTL_ARGS)
630 {
631 DRM_DEVICE;
632 drm_r128_init_t init;
633
634 DRM_DEBUG("\n");
635
636 LOCK_TEST_WITH_RETURN(dev, filp);
637
638 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
639 sizeof(init));
640
641 switch (init.func) {
642 case R128_INIT_CCE:
643 return r128_do_init_cce(dev, &init);
644 case R128_CLEANUP_CCE:
645 return r128_do_cleanup_cce(dev);
646 }
647
648 return DRM_ERR(EINVAL);
649 }
650
651 int r128_cce_start(DRM_IOCTL_ARGS)
652 {
653 DRM_DEVICE;
654 drm_r128_private_t *dev_priv = dev->dev_private;
655 DRM_DEBUG("\n");
656
657 LOCK_TEST_WITH_RETURN(dev, filp);
658
659 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
660 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
661 return 0;
662 }
663
664 r128_do_cce_start(dev_priv);
665
666 return 0;
667 }
668
669 /* Stop the CCE. The engine must have been idled before calling this
670 * routine.
671 */
672 int r128_cce_stop(DRM_IOCTL_ARGS)
673 {
674 DRM_DEVICE;
675 drm_r128_private_t *dev_priv = dev->dev_private;
676 drm_r128_cce_stop_t stop;
677 int ret;
678 DRM_DEBUG("\n");
679
680 LOCK_TEST_WITH_RETURN(dev, filp);
681
682 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
683 sizeof(stop));
684
685 /* Flush any pending CCE commands. This ensures any outstanding
686 * commands are exectuted by the engine before we turn it off.
687 */
688 if (stop.flush) {
689 r128_do_cce_flush(dev_priv);
690 }
691
692 /* If we fail to make the engine go idle, we return an error
693 * code so that the DRM ioctl wrapper can try again.
694 */
695 if (stop.idle) {
696 ret = r128_do_cce_idle(dev_priv);
697 if (ret)
698 return ret;
699 }
700
701 /* Finally, we can turn off the CCE. If the engine isn't idle,
702 * we will get some dropped triangles as they won't be fully
703 * rendered before the CCE is shut down.
704 */
705 r128_do_cce_stop(dev_priv);
706
707 /* Reset the engine */
708 r128_do_engine_reset(dev);
709
710 return 0;
711 }
712
713 /* Just reset the CCE ring. Called as part of an X Server engine reset.
714 */
715 int r128_cce_reset(DRM_IOCTL_ARGS)
716 {
717 DRM_DEVICE;
718 drm_r128_private_t *dev_priv = dev->dev_private;
719 DRM_DEBUG("\n");
720
721 LOCK_TEST_WITH_RETURN(dev, filp);
722
723 if (!dev_priv) {
724 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
725 return DRM_ERR(EINVAL);
726 }
727
728 r128_do_cce_reset(dev_priv);
729
730 /* The CCE is no longer running after an engine reset */
731 dev_priv->cce_running = 0;
732
733 return 0;
734 }
735
736 int r128_cce_idle(DRM_IOCTL_ARGS)
737 {
738 DRM_DEVICE;
739 drm_r128_private_t *dev_priv = dev->dev_private;
740 DRM_DEBUG("\n");
741
742 LOCK_TEST_WITH_RETURN(dev, filp);
743
744 if (dev_priv->cce_running) {
745 r128_do_cce_flush(dev_priv);
746 }
747
748 return r128_do_cce_idle(dev_priv);
749 }
750
751 int r128_engine_reset(DRM_IOCTL_ARGS)
752 {
753 DRM_DEVICE;
754 DRM_DEBUG("\n");
755
756 LOCK_TEST_WITH_RETURN(dev, filp);
757
758 return r128_do_engine_reset(dev);
759 }
760
761 int r128_fullscreen(DRM_IOCTL_ARGS)
762 {
763 return DRM_ERR(EINVAL);
764 }
765
766 /* ================================================================
767 * Freelist management
768 */
769 #define R128_BUFFER_USED 0xffffffff
770 #define R128_BUFFER_FREE 0
771
772 #if 0
773 static int r128_freelist_init(drm_device_t * dev)
774 {
775 drm_device_dma_t *dma = dev->dma;
776 drm_r128_private_t *dev_priv = dev->dev_private;
777 drm_buf_t *buf;
778 drm_r128_buf_priv_t *buf_priv;
779 drm_r128_freelist_t *entry;
780 int i;
781
782 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
783 if (dev_priv->head == NULL)
784 return DRM_ERR(ENOMEM);
785
786 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
787 dev_priv->head->age = R128_BUFFER_USED;
788
789 for (i = 0; i < dma->buf_count; i++) {
790 buf = dma->buflist[i];
791 buf_priv = buf->dev_private;
792
793 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
794 if (!entry)
795 return DRM_ERR(ENOMEM);
796
797 entry->age = R128_BUFFER_FREE;
798 entry->buf = buf;
799 entry->prev = dev_priv->head;
800 entry->next = dev_priv->head->next;
801 if (!entry->next)
802 dev_priv->tail = entry;
803
804 buf_priv->discard = 0;
805 buf_priv->dispatched = 0;
806 buf_priv->list_entry = entry;
807
808 dev_priv->head->next = entry;
809
810 if (dev_priv->head->next)
811 dev_priv->head->next->prev = entry;
812 }
813
814 return 0;
815
816 }
817 #endif
818
819 static drm_buf_t *r128_freelist_get(drm_device_t * dev)
820 {
821 drm_device_dma_t *dma = dev->dma;
822 drm_r128_private_t *dev_priv = dev->dev_private;
823 drm_r128_buf_priv_t *buf_priv;
824 drm_buf_t *buf;
825 int i, t;
826
827 /* FIXME: Optimize -- use freelist code */
828
829 for (i = 0; i < dma->buf_count; i++) {
830 buf = dma->buflist[i];
831 buf_priv = buf->dev_private;
832 if (buf->filp == 0)
833 return buf;
834 }
835
836 for (t = 0; t < dev_priv->usec_timeout; t++) {
837 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
838
839 for (i = 0; i < dma->buf_count; i++) {
840 buf = dma->buflist[i];
841 buf_priv = buf->dev_private;
842 if (buf->pending && buf_priv->age <= done_age) {
843 /* The buffer has been processed, so it
844 * can now be used.
845 */
846 buf->pending = 0;
847 return buf;
848 }
849 }
850 DRM_UDELAY(1);
851 }
852
853 DRM_DEBUG("returning NULL!\n");
854 return NULL;
855 }
856
857 void r128_freelist_reset(drm_device_t * dev)
858 {
859 drm_device_dma_t *dma = dev->dma;
860 int i;
861
862 for (i = 0; i < dma->buf_count; i++) {
863 drm_buf_t *buf = dma->buflist[i];
864 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
865 buf_priv->age = 0;
866 }
867 }
868
869 /* ================================================================
870 * CCE command submission
871 */
872
873 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
874 {
875 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
876 int i;
877
878 for (i = 0; i < dev_priv->usec_timeout; i++) {
879 r128_update_ring_snapshot(dev_priv);
880 if (ring->space >= n)
881 return 0;
882 DRM_UDELAY(1);
883 }
884
885 /* FIXME: This is being ignored... */
886 DRM_ERROR("failed!\n");
887 return DRM_ERR(EBUSY);
888 }
889
890 static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
891 {
892 int i;
893 drm_buf_t *buf;
894
895 for (i = d->granted_count; i < d->request_count; i++) {
896 buf = r128_freelist_get(dev);
897 if (!buf)
898 return DRM_ERR(EAGAIN);
899
900 buf->filp = filp;
901
902 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
903 sizeof(buf->idx)))
904 return DRM_ERR(EFAULT);
905 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
906 sizeof(buf->total)))
907 return DRM_ERR(EFAULT);
908
909 d->granted_count++;
910 }
911 return 0;
912 }
913
914 int r128_cce_buffers(DRM_IOCTL_ARGS)
915 {
916 DRM_DEVICE;
917 drm_device_dma_t *dma = dev->dma;
918 int ret = 0;
919 drm_dma_t __user *argp = (void __user *)data;
920 drm_dma_t d;
921
922 LOCK_TEST_WITH_RETURN(dev, filp);
923
924 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
925
926 /* Please don't send us buffers.
927 */
928 if (d.send_count != 0) {
929 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
930 DRM_CURRENTPID, d.send_count);
931 return DRM_ERR(EINVAL);
932 }
933
934 /* We'll send you buffers.
935 */
936 if (d.request_count < 0 || d.request_count > dma->buf_count) {
937 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
938 DRM_CURRENTPID, d.request_count, dma->buf_count);
939 return DRM_ERR(EINVAL);
940 }
941
942 d.granted_count = 0;
943
944 if (d.request_count) {
945 ret = r128_cce_get_buffers(filp, dev, &d);
946 }
947
948 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
949
950 return ret;
951 }
Tomato firmware and modifications.