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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / char / agp / intel-agp.c
blobd06b652031a33535f2a95c0a91589862792db3bc
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
23 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
24 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
25 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
26 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
27 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
28 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
29 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
30 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
31 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
32 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
33
34 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
35 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
36 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
37 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
38 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
40
41 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
42 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
43 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
44
45 extern int agp_memory_reserved;
46
47
48 /* Intel 815 register */
49 #define INTEL_815_APCONT 0x51
50 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
51
52 /* Intel i820 registers */
53 #define INTEL_I820_RDCR 0x51
54 #define INTEL_I820_ERRSTS 0xc8
55
56 /* Intel i840 registers */
57 #define INTEL_I840_MCHCFG 0x50
58 #define INTEL_I840_ERRSTS 0xc8
59
60 /* Intel i850 registers */
61 #define INTEL_I850_MCHCFG 0x50
62 #define INTEL_I850_ERRSTS 0xc8
63
64 /* intel 915G registers */
65 #define I915_GMADDR 0x18
66 #define I915_MMADDR 0x10
67 #define I915_PTEADDR 0x1C
68 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
69 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
70 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
71 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
72
73 /* Intel 965G registers */
74 #define I965_MSAC 0x62
75
76 /* Intel 7505 registers */
77 #define INTEL_I7505_APSIZE 0x74
78 #define INTEL_I7505_NCAPID 0x60
79 #define INTEL_I7505_NISTAT 0x6c
80 #define INTEL_I7505_ATTBASE 0x78
81 #define INTEL_I7505_ERRSTS 0x42
82 #define INTEL_I7505_AGPCTRL 0x70
83 #define INTEL_I7505_MCHCFG 0x50
84
85 static const struct aper_size_info_fixed intel_i810_sizes[] =
86 {
87 {64, 16384, 4},
88 /* The 32M mode still requires a 64k gatt */
89 {32, 8192, 4}
90 };
91
92 #define AGP_DCACHE_MEMORY 1
93 #define AGP_PHYS_MEMORY 2
94 #define INTEL_AGP_CACHED_MEMORY 3
95
96 static struct gatt_mask intel_i810_masks[] =
97 {
98 {.mask = I810_PTE_VALID, .type = 0},
99 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
100 {.mask = I810_PTE_VALID, .type = 0},
101 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
102 .type = INTEL_AGP_CACHED_MEMORY}
103 };
104
105 static struct _intel_private {
106 struct pci_dev *pcidev; /* device one */
107 u8 __iomem *registers;
108 u32 __iomem *gtt; /* I915G */
109 int num_dcache_entries;
110 /* gtt_entries is the number of gtt entries that are already mapped
111 * to stolen memory. Stolen memory is larger than the memory mapped
112 * through gtt_entries, as it includes some reserved space for the BIOS
113 * popup and for the GTT.
114 */
115 int gtt_entries; /* i830+ */
116 } intel_private;
117
118 static int intel_i810_fetch_size(void)
119 {
120 u32 smram_miscc;
121 struct aper_size_info_fixed *values;
122
123 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
124 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
125
126 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
127 printk(KERN_WARNING PFX "i810 is disabled\n");
128 return 0;
129 }
130 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
131 agp_bridge->previous_size =
132 agp_bridge->current_size = (void *) (values + 1);
133 agp_bridge->aperture_size_idx = 1;
134 return values[1].size;
135 } else {
136 agp_bridge->previous_size =
137 agp_bridge->current_size = (void *) (values);
138 agp_bridge->aperture_size_idx = 0;
139 return values[0].size;
140 }
141
142 return 0;
143 }
144
145 static int intel_i810_configure(void)
146 {
147 struct aper_size_info_fixed *current_size;
148 u32 temp;
149 int i;
150
151 current_size = A_SIZE_FIX(agp_bridge->current_size);
152
153 if (!intel_private.registers) {
154 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
155 temp &= 0xfff80000;
156
157 intel_private.registers = ioremap(temp, 128 * 4096);
158 if (!intel_private.registers) {
159 printk(KERN_ERR PFX "Unable to remap memory.\n");
160 return -ENOMEM;
161 }
162 }
163
164 if ((readl(intel_private.registers+I810_DRAM_CTL)
165 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
166 /* This will need to be dynamically assigned */
167 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
168 intel_private.num_dcache_entries = 1024;
169 }
170 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
171 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
172 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
173 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
174
175 if (agp_bridge->driver->needs_scratch_page) {
176 for (i = 0; i < current_size->num_entries; i++) {
177 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
178 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
179 }
180 }
181 global_cache_flush();
182 return 0;
183 }
184
185 static void intel_i810_cleanup(void)
186 {
187 writel(0, intel_private.registers+I810_PGETBL_CTL);
188 readl(intel_private.registers); /* PCI Posting. */
189 iounmap(intel_private.registers);
190 }
191
192 static void intel_i810_tlbflush(struct agp_memory *mem)
193 {
194 return;
195 }
196
197 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
198 {
199 return;
200 }
201
202 /* Exists to support ARGB cursors */
203 static void *i8xx_alloc_pages(void)
204 {
205 struct page * page;
206
207 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
208 if (page == NULL)
209 return NULL;
210
211 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
212 change_page_attr(page, 4, PAGE_KERNEL);
213 global_flush_tlb();
214 __free_pages(page, 2);
215 return NULL;
216 }
217 global_flush_tlb();
218 get_page(page);
219 SetPageLocked(page);
220 atomic_inc(&agp_bridge->current_memory_agp);
221 return page_address(page);
222 }
223
224 static void i8xx_destroy_pages(void *addr)
225 {
226 struct page *page;
227
228 if (addr == NULL)
229 return;
230
231 page = virt_to_page(addr);
232 change_page_attr(page, 4, PAGE_KERNEL);
233 global_flush_tlb();
234 put_page(page);
235 unlock_page(page);
236 __free_pages(page, 2);
237 atomic_dec(&agp_bridge->current_memory_agp);
238 }
239
240 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
241 int type)
242 {
243 if (type < AGP_USER_TYPES)
244 return type;
245 else if (type == AGP_USER_CACHED_MEMORY)
246 return INTEL_AGP_CACHED_MEMORY;
247 else
248 return 0;
249 }
250
251 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
252 int type)
253 {
254 int i, j, num_entries;
255 void *temp;
256 int ret = -EINVAL;
257 int mask_type;
258
259 if (mem->page_count == 0)
260 goto out;
261
262 temp = agp_bridge->current_size;
263 num_entries = A_SIZE_FIX(temp)->num_entries;
264
265 if ((pg_start + mem->page_count) > num_entries)
266 goto out_err;
267
268
269 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
270 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
271 ret = -EBUSY;
272 goto out_err;
273 }
274 }
275
276 if (type != mem->type)
277 goto out_err;
278
279 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
280
281 switch (mask_type) {
282 case AGP_DCACHE_MEMORY:
283 if (!mem->is_flushed)
284 global_cache_flush();
285 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
286 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
287 intel_private.registers+I810_PTE_BASE+(i*4));
288 }
289 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
290 break;
291 case AGP_PHYS_MEMORY:
292 case AGP_NORMAL_MEMORY:
293 if (!mem->is_flushed)
294 global_cache_flush();
295 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
296 writel(agp_bridge->driver->mask_memory(agp_bridge,
297 mem->memory[i],
298 mask_type),
299 intel_private.registers+I810_PTE_BASE+(j*4));
300 }
301 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
302 break;
303 default:
304 goto out_err;
305 }
306
307 agp_bridge->driver->tlb_flush(mem);
308 out:
309 ret = 0;
310 out_err:
311 mem->is_flushed = 1;
312 return ret;
313 }
314
315 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
316 int type)
317 {
318 int i;
319
320 if (mem->page_count == 0)
321 return 0;
322
323 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
324 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
325 }
326 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
327
328 agp_bridge->driver->tlb_flush(mem);
329 return 0;
330 }
331
332 /*
333 * The i810/i830 requires a physical address to program its mouse
334 * pointer into hardware.
335 * However the Xserver still writes to it through the agp aperture.
336 */
337 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
338 {
339 struct agp_memory *new;
340 void *addr;
341
342 switch (pg_count) {
343 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
344 global_flush_tlb();
345 break;
346 case 4:
347 /* kludge to get 4 physical pages for ARGB cursor */
348 addr = i8xx_alloc_pages();
349 break;
350 default:
351 return NULL;
352 }
353
354 if (addr == NULL)
355 return NULL;
356
357 new = agp_create_memory(pg_count);
358 if (new == NULL)
359 return NULL;
360
361 new->memory[0] = virt_to_gart(addr);
362 if (pg_count == 4) {
363 /* kludge to get 4 physical pages for ARGB cursor */
364 new->memory[1] = new->memory[0] + PAGE_SIZE;
365 new->memory[2] = new->memory[1] + PAGE_SIZE;
366 new->memory[3] = new->memory[2] + PAGE_SIZE;
367 }
368 new->page_count = pg_count;
369 new->num_scratch_pages = pg_count;
370 new->type = AGP_PHYS_MEMORY;
371 new->physical = new->memory[0];
372 return new;
373 }
374
375 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
376 {
377 struct agp_memory *new;
378
379 if (type == AGP_DCACHE_MEMORY) {
380 if (pg_count != intel_private.num_dcache_entries)
381 return NULL;
382
383 new = agp_create_memory(1);
384 if (new == NULL)
385 return NULL;
386
387 new->type = AGP_DCACHE_MEMORY;
388 new->page_count = pg_count;
389 new->num_scratch_pages = 0;
390 agp_free_page_array(new);
391 return new;
392 }
393 if (type == AGP_PHYS_MEMORY)
394 return alloc_agpphysmem_i8xx(pg_count, type);
395 return NULL;
396 }
397
398 static void intel_i810_free_by_type(struct agp_memory *curr)
399 {
400 agp_free_key(curr->key);
401 if (curr->type == AGP_PHYS_MEMORY) {
402 if (curr->page_count == 4)
403 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
404 else {
405 agp_bridge->driver->agp_destroy_page(
406 gart_to_virt(curr->memory[0]));
407 global_flush_tlb();
408 }
409 agp_free_page_array(curr);
410 }
411 kfree(curr);
412 }
413
414 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
415 unsigned long addr, int type)
416 {
417 /* Type checking must be done elsewhere */
418 return addr | bridge->driver->masks[type].mask;
419 }
420
421 static struct aper_size_info_fixed intel_i830_sizes[] =
422 {
423 {128, 32768, 5},
424 /* The 64M mode still requires a 128k gatt */
425 {64, 16384, 5},
426 {256, 65536, 6},
427 {512, 131072, 7},
428 };
429
430 static void intel_i830_init_gtt_entries(void)
431 {
432 u16 gmch_ctrl;
433 int gtt_entries;
434 u8 rdct;
435 int local = 0;
436 static const int ddt[4] = { 0, 16, 32, 64 };
437 int size; /* reserved space (in kb) at the top of stolen memory */
438
439 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
440
441 if (IS_I965) {
442 u32 pgetbl_ctl;
443 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
444
445 /* The 965 has a field telling us the size of the GTT,
446 * which may be larger than what is necessary to map the
447 * aperture.
448 */
449 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
450 case I965_PGETBL_SIZE_128KB:
451 size = 128;
452 break;
453 case I965_PGETBL_SIZE_256KB:
454 size = 256;
455 break;
456 case I965_PGETBL_SIZE_512KB:
457 size = 512;
458 break;
459 default:
460 printk(KERN_INFO PFX "Unknown page table size, "
461 "assuming 512KB\n");
462 size = 512;
463 }
464 size += 4; /* add in BIOS popup space */
465 } else if (IS_G33) {
466 /* G33's GTT size defined in gmch_ctrl */
467 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
468 case G33_PGETBL_SIZE_1M:
469 size = 1024;
470 break;
471 case G33_PGETBL_SIZE_2M:
472 size = 2048;
473 break;
474 default:
475 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
476 "assuming 512KB\n",
477 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
478 size = 512;
479 }
480 size += 4;
481 } else {
482 /* On previous hardware, the GTT size was just what was
483 * required to map the aperture.
484 */
485 size = agp_bridge->driver->fetch_size() + 4;
486 }
487
488 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
489 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
490 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
491 case I830_GMCH_GMS_STOLEN_512:
492 gtt_entries = KB(512) - KB(size);
493 break;
494 case I830_GMCH_GMS_STOLEN_1024:
495 gtt_entries = MB(1) - KB(size);
496 break;
497 case I830_GMCH_GMS_STOLEN_8192:
498 gtt_entries = MB(8) - KB(size);
499 break;
500 case I830_GMCH_GMS_LOCAL:
501 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
502 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
503 MB(ddt[I830_RDRAM_DDT(rdct)]);
504 local = 1;
505 break;
506 default:
507 gtt_entries = 0;
508 break;
509 }
510 } else {
511 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
512 case I855_GMCH_GMS_STOLEN_1M:
513 gtt_entries = MB(1) - KB(size);
514 break;
515 case I855_GMCH_GMS_STOLEN_4M:
516 gtt_entries = MB(4) - KB(size);
517 break;
518 case I855_GMCH_GMS_STOLEN_8M:
519 gtt_entries = MB(8) - KB(size);
520 break;
521 case I855_GMCH_GMS_STOLEN_16M:
522 gtt_entries = MB(16) - KB(size);
523 break;
524 case I855_GMCH_GMS_STOLEN_32M:
525 gtt_entries = MB(32) - KB(size);
526 break;
527 case I915_GMCH_GMS_STOLEN_48M:
528 /* Check it's really I915G */
529 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
530 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
531 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
532 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
533 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
534 IS_I965 || IS_G33)
535 gtt_entries = MB(48) - KB(size);
536 else
537 gtt_entries = 0;
538 break;
539 case I915_GMCH_GMS_STOLEN_64M:
540 /* Check it's really I915G */
541 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
542 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
543 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
544 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
545 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
546 IS_I965 || IS_G33)
547 gtt_entries = MB(64) - KB(size);
548 else
549 gtt_entries = 0;
550 break;
551 case G33_GMCH_GMS_STOLEN_128M:
552 if (IS_G33)
553 gtt_entries = MB(128) - KB(size);
554 else
555 gtt_entries = 0;
556 break;
557 case G33_GMCH_GMS_STOLEN_256M:
558 if (IS_G33)
559 gtt_entries = MB(256) - KB(size);
560 else
561 gtt_entries = 0;
562 break;
563 default:
564 gtt_entries = 0;
565 break;
566 }
567 }
568 if (gtt_entries > 0)
569 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
570 gtt_entries / KB(1), local ? "local" : "stolen");
571 else
572 printk(KERN_INFO PFX
573 "No pre-allocated video memory detected.\n");
574 gtt_entries /= KB(4);
575
576 intel_private.gtt_entries = gtt_entries;
577 }
578
579 /* The intel i830 automatically initializes the agp aperture during POST.
580 * Use the memory already set aside for in the GTT.
581 */
582 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
583 {
584 int page_order;
585 struct aper_size_info_fixed *size;
586 int num_entries;
587 u32 temp;
588
589 size = agp_bridge->current_size;
590 page_order = size->page_order;
591 num_entries = size->num_entries;
592 agp_bridge->gatt_table_real = NULL;
593
594 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
595 temp &= 0xfff80000;
596
597 intel_private.registers = ioremap(temp,128 * 4096);
598 if (!intel_private.registers)
599 return -ENOMEM;
600
601 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
602 global_cache_flush(); /* FIXME: ?? */
603
604 /* we have to call this as early as possible after the MMIO base address is known */
605 intel_i830_init_gtt_entries();
606
607 agp_bridge->gatt_table = NULL;
608
609 agp_bridge->gatt_bus_addr = temp;
610
611 return 0;
612 }
613
614 /* Return the gatt table to a sane state. Use the top of stolen
615 * memory for the GTT.
616 */
617 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
618 {
619 return 0;
620 }
621
622 static int intel_i830_fetch_size(void)
623 {
624 u16 gmch_ctrl;
625 struct aper_size_info_fixed *values;
626
627 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
628
629 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
630 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
631 /* 855GM/852GM/865G has 128MB aperture size */
632 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
633 agp_bridge->aperture_size_idx = 0;
634 return values[0].size;
635 }
636
637 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
638
639 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
640 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
641 agp_bridge->aperture_size_idx = 0;
642 return values[0].size;
643 } else {
644 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
645 agp_bridge->aperture_size_idx = 1;
646 return values[1].size;
647 }
648
649 return 0;
650 }
651
652 static int intel_i830_configure(void)
653 {
654 struct aper_size_info_fixed *current_size;
655 u32 temp;
656 u16 gmch_ctrl;
657 int i;
658
659 current_size = A_SIZE_FIX(agp_bridge->current_size);
660
661 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
662 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
663
664 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
665 gmch_ctrl |= I830_GMCH_ENABLED;
666 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
667
668 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
669 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
670
671 if (agp_bridge->driver->needs_scratch_page) {
672 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
673 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
674 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
675 }
676 }
677
678 global_cache_flush();
679 return 0;
680 }
681
682 static void intel_i830_cleanup(void)
683 {
684 iounmap(intel_private.registers);
685 }
686
687 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
688 {
689 int i,j,num_entries;
690 void *temp;
691 int ret = -EINVAL;
692 int mask_type;
693
694 if (mem->page_count == 0)
695 goto out;
696
697 temp = agp_bridge->current_size;
698 num_entries = A_SIZE_FIX(temp)->num_entries;
699
700 if (pg_start < intel_private.gtt_entries) {
701 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
702 pg_start,intel_private.gtt_entries);
703
704 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
705 goto out_err;
706 }
707
708 if ((pg_start + mem->page_count) > num_entries)
709 goto out_err;
710
711 /* The i830 can't check the GTT for entries since its read only,
712 * depend on the caller to make the correct offset decisions.
713 */
714
715 if (type != mem->type)
716 goto out_err;
717
718 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
719
720 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
721 mask_type != INTEL_AGP_CACHED_MEMORY)
722 goto out_err;
723
724 if (!mem->is_flushed)
725 global_cache_flush();
726
727 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
728 writel(agp_bridge->driver->mask_memory(agp_bridge,
729 mem->memory[i], mask_type),
730 intel_private.registers+I810_PTE_BASE+(j*4));
731 }
732 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
733 agp_bridge->driver->tlb_flush(mem);
734
735 out:
736 ret = 0;
737 out_err:
738 mem->is_flushed = 1;
739 return ret;
740 }
741
742 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
743 int type)
744 {
745 int i;
746
747 if (mem->page_count == 0)
748 return 0;
749
750 if (pg_start < intel_private.gtt_entries) {
751 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
752 return -EINVAL;
753 }
754
755 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
756 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
757 }
758 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
759
760 agp_bridge->driver->tlb_flush(mem);
761 return 0;
762 }
763
764 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
765 {
766 if (type == AGP_PHYS_MEMORY)
767 return alloc_agpphysmem_i8xx(pg_count, type);
768 /* always return NULL for other allocation types for now */
769 return NULL;
770 }
771
772 static int intel_i915_configure(void)
773 {
774 struct aper_size_info_fixed *current_size;
775 u32 temp;
776 u16 gmch_ctrl;
777 int i;
778
779 current_size = A_SIZE_FIX(agp_bridge->current_size);
780
781 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
782
783 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
784
785 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
786 gmch_ctrl |= I830_GMCH_ENABLED;
787 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
788
789 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
790 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
791
792 if (agp_bridge->driver->needs_scratch_page) {
793 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
794 writel(agp_bridge->scratch_page, intel_private.gtt+i);
795 readl(intel_private.gtt+i); /* PCI Posting. */
796 }
797 }
798
799 global_cache_flush();
800 return 0;
801 }
802
803 static void intel_i915_cleanup(void)
804 {
805 iounmap(intel_private.gtt);
806 iounmap(intel_private.registers);
807 }
808
809 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
810 int type)
811 {
812 int i,j,num_entries;
813 void *temp;
814 int ret = -EINVAL;
815 int mask_type;
816
817 if (mem->page_count == 0)
818 goto out;
819
820 temp = agp_bridge->current_size;
821 num_entries = A_SIZE_FIX(temp)->num_entries;
822
823 if (pg_start < intel_private.gtt_entries) {
824 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
825 pg_start,intel_private.gtt_entries);
826
827 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
828 goto out_err;
829 }
830
831 if ((pg_start + mem->page_count) > num_entries)
832 goto out_err;
833
834 /* The i915 can't check the GTT for entries since its read only,
835 * depend on the caller to make the correct offset decisions.
836 */
837
838 if (type != mem->type)
839 goto out_err;
840
841 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
842
843 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
844 mask_type != INTEL_AGP_CACHED_MEMORY)
845 goto out_err;
846
847 if (!mem->is_flushed)
848 global_cache_flush();
849
850 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
851 writel(agp_bridge->driver->mask_memory(agp_bridge,
852 mem->memory[i], mask_type), intel_private.gtt+j);
853 }
854
855 readl(intel_private.gtt+j-1);
856 agp_bridge->driver->tlb_flush(mem);
857
858 out:
859 ret = 0;
860 out_err:
861 mem->is_flushed = 1;
862 return ret;
863 }
864
865 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
866 int type)
867 {
868 int i;
869
870 if (mem->page_count == 0)
871 return 0;
872
873 if (pg_start < intel_private.gtt_entries) {
874 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
875 return -EINVAL;
876 }
877
878 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
879 writel(agp_bridge->scratch_page, intel_private.gtt+i);
880 }
881 readl(intel_private.gtt+i-1);
882
883 agp_bridge->driver->tlb_flush(mem);
884 return 0;
885 }
886
887 /* Return the aperture size by just checking the resource length. The effect
888 * described in the spec of the MSAC registers is just changing of the
889 * resource size.
890 */
891 static int intel_i9xx_fetch_size(void)
892 {
893 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
894 int aper_size; /* size in megabytes */
895 int i;
896
897 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
898
899 for (i = 0; i < num_sizes; i++) {
900 if (aper_size == intel_i830_sizes[i].size) {
901 agp_bridge->current_size = intel_i830_sizes + i;
902 agp_bridge->previous_size = agp_bridge->current_size;
903 return aper_size;
904 }
905 }
906
907 return 0;
908 }
909
910 /* The intel i915 automatically initializes the agp aperture during POST.
911 * Use the memory already set aside for in the GTT.
912 */
913 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
914 {
915 int page_order;
916 struct aper_size_info_fixed *size;
917 int num_entries;
918 u32 temp, temp2;
919
920 size = agp_bridge->current_size;
921 page_order = size->page_order;
922 num_entries = size->num_entries;
923 agp_bridge->gatt_table_real = NULL;
924
925 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
926 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
927
928 intel_private.gtt = ioremap(temp2, 256 * 1024);
929 if (!intel_private.gtt)
930 return -ENOMEM;
931
932 temp &= 0xfff80000;
933
934 intel_private.registers = ioremap(temp,128 * 4096);
935 if (!intel_private.registers)
936 return -ENOMEM;
937
938 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
939 global_cache_flush(); /* FIXME: ? */
940
941 /* we have to call this as early as possible after the MMIO base address is known */
942 intel_i830_init_gtt_entries();
943
944 agp_bridge->gatt_table = NULL;
945
946 agp_bridge->gatt_bus_addr = temp;
947
948 return 0;
949 }
950
951 /*
952 * The i965 supports 36-bit physical addresses, but to keep
953 * the format of the GTT the same, the bits that don't fit
954 * in a 32-bit word are shifted down to bits 4..7.
955 *
956 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
957 * is always zero on 32-bit architectures, so no need to make
958 * this conditional.
959 */
960 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
961 unsigned long addr, int type)
962 {
963 /* Shift high bits down */
964 addr |= (addr >> 28) & 0xf0;
965
966 /* Type checking must be done elsewhere */
967 return addr | bridge->driver->masks[type].mask;
968 }
969
970 /* The intel i965 automatically initializes the agp aperture during POST.
971 * Use the memory already set aside for in the GTT.
972 */
973 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
974 {
975 int page_order;
976 struct aper_size_info_fixed *size;
977 int num_entries;
978 u32 temp;
979
980 size = agp_bridge->current_size;
981 page_order = size->page_order;
982 num_entries = size->num_entries;
983 agp_bridge->gatt_table_real = NULL;
984
985 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
986
987 temp &= 0xfff00000;
988 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
989
990 if (!intel_private.gtt)
991 return -ENOMEM;
992
993
994 intel_private.registers = ioremap(temp,128 * 4096);
995 if (!intel_private.registers)
996 return -ENOMEM;
997
998 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
999 global_cache_flush(); /* FIXME: ? */
1000
1001 /* we have to call this as early as possible after the MMIO base address is known */
1002 intel_i830_init_gtt_entries();
1003
1004 agp_bridge->gatt_table = NULL;
1005
1006 agp_bridge->gatt_bus_addr = temp;
1007
1008 return 0;
1009 }
1010
1011
1012 static int intel_fetch_size(void)
1013 {
1014 int i;
1015 u16 temp;
1016 struct aper_size_info_16 *values;
1017
1018 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1019 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1020
1021 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1022 if (temp == values[i].size_value) {
1023 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1024 agp_bridge->aperture_size_idx = i;
1025 return values[i].size;
1026 }
1027 }
1028
1029 return 0;
1030 }
1031
1032 static int __intel_8xx_fetch_size(u8 temp)
1033 {
1034 int i;
1035 struct aper_size_info_8 *values;
1036
1037 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1038
1039 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1040 if (temp == values[i].size_value) {
1041 agp_bridge->previous_size =
1042 agp_bridge->current_size = (void *) (values + i);
1043 agp_bridge->aperture_size_idx = i;
1044 return values[i].size;
1045 }
1046 }
1047 return 0;
1048 }
1049
1050 static int intel_8xx_fetch_size(void)
1051 {
1052 u8 temp;
1053
1054 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1055 return __intel_8xx_fetch_size(temp);
1056 }
1057
1058 static int intel_815_fetch_size(void)
1059 {
1060 u8 temp;
1061
1062 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1063 * one non-reserved bit, so mask the others out ... */
1064 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1065 temp &= (1 << 3);
1066
1067 return __intel_8xx_fetch_size(temp);
1068 }
1069
1070 static void intel_tlbflush(struct agp_memory *mem)
1071 {
1072 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1073 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1074 }
1075
1076
1077 static void intel_8xx_tlbflush(struct agp_memory *mem)
1078 {
1079 u32 temp;
1080 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1081 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1082 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1083 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1084 }
1085
1086
1087 static void intel_cleanup(void)
1088 {
1089 u16 temp;
1090 struct aper_size_info_16 *previous_size;
1091
1092 previous_size = A_SIZE_16(agp_bridge->previous_size);
1093 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1094 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1095 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1096 }
1097
1098
1099 static void intel_8xx_cleanup(void)
1100 {
1101 u16 temp;
1102 struct aper_size_info_8 *previous_size;
1103
1104 previous_size = A_SIZE_8(agp_bridge->previous_size);
1105 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1106 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1107 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1108 }
1109
1110
1111 static int intel_configure(void)
1112 {
1113 u32 temp;
1114 u16 temp2;
1115 struct aper_size_info_16 *current_size;
1116
1117 current_size = A_SIZE_16(agp_bridge->current_size);
1118
1119 /* aperture size */
1120 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1121
1122 /* address to map to */
1123 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1124 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1125
1126 /* attbase - aperture base */
1127 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1128
1129 /* agpctrl */
1130 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1131
1132 /* paccfg/nbxcfg */
1133 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1134 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1135 (temp2 & ~(1 << 10)) | (1 << 9));
1136 /* clear any possible error conditions */
1137 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1138 return 0;
1139 }
1140
1141 static int intel_815_configure(void)
1142 {
1143 u32 temp, addr;
1144 u8 temp2;
1145 struct aper_size_info_8 *current_size;
1146
1147 /* attbase - aperture base */
1148 /* the Intel 815 chipset spec. says that bits 29-31 in the
1149 * ATTBASE register are reserved -> try not to write them */
1150 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1151 printk (KERN_EMERG PFX "gatt bus addr too high");
1152 return -EINVAL;
1153 }
1154
1155 current_size = A_SIZE_8(agp_bridge->current_size);
1156
1157 /* aperture size */
1158 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1159 current_size->size_value);
1160
1161 /* address to map to */
1162 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1163 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1164
1165 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1166 addr &= INTEL_815_ATTBASE_MASK;
1167 addr |= agp_bridge->gatt_bus_addr;
1168 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1169
1170 /* agpctrl */
1171 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1172
1173 /* apcont */
1174 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1175 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1176
1177 /* clear any possible error conditions */
1178 /* Oddness : this chipset seems to have no ERRSTS register ! */
1179 return 0;
1180 }
1181
1182 static void intel_820_tlbflush(struct agp_memory *mem)
1183 {
1184 return;
1185 }
1186
1187 static void intel_820_cleanup(void)
1188 {
1189 u8 temp;
1190 struct aper_size_info_8 *previous_size;
1191
1192 previous_size = A_SIZE_8(agp_bridge->previous_size);
1193 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1194 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1195 temp & ~(1 << 1));
1196 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1197 previous_size->size_value);
1198 }
1199
1200
1201 static int intel_820_configure(void)
1202 {
1203 u32 temp;
1204 u8 temp2;
1205 struct aper_size_info_8 *current_size;
1206
1207 current_size = A_SIZE_8(agp_bridge->current_size);
1208
1209 /* aperture size */
1210 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1211
1212 /* address to map to */
1213 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1214 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1215
1216 /* attbase - aperture base */
1217 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1218
1219 /* agpctrl */
1220 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1221
1222 /* global enable aperture access */
1223 /* This flag is not accessed through MCHCFG register as in */
1224 /* i850 chipset. */
1225 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1226 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1227 /* clear any possible AGP-related error conditions */
1228 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1229 return 0;
1230 }
1231
1232 static int intel_840_configure(void)
1233 {
1234 u32 temp;
1235 u16 temp2;
1236 struct aper_size_info_8 *current_size;
1237
1238 current_size = A_SIZE_8(agp_bridge->current_size);
1239
1240 /* aperture size */
1241 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1242
1243 /* address to map to */
1244 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1245 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1246
1247 /* attbase - aperture base */
1248 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1249
1250 /* agpctrl */
1251 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1252
1253 /* mcgcfg */
1254 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1255 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1256 /* clear any possible error conditions */
1257 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1258 return 0;
1259 }
1260
1261 static int intel_845_configure(void)
1262 {
1263 u32 temp;
1264 u8 temp2;
1265 struct aper_size_info_8 *current_size;
1266
1267 current_size = A_SIZE_8(agp_bridge->current_size);
1268
1269 /* aperture size */
1270 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1271
1272 if (agp_bridge->apbase_config != 0) {
1273 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1274 agp_bridge->apbase_config);
1275 } else {
1276 /* address to map to */
1277 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1278 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1279 agp_bridge->apbase_config = temp;
1280 }
1281
1282 /* attbase - aperture base */
1283 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1284
1285 /* agpctrl */
1286 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1287
1288 /* agpm */
1289 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1290 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1291 /* clear any possible error conditions */
1292 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1293 return 0;
1294 }
1295
1296 static int intel_850_configure(void)
1297 {
1298 u32 temp;
1299 u16 temp2;
1300 struct aper_size_info_8 *current_size;
1301
1302 current_size = A_SIZE_8(agp_bridge->current_size);
1303
1304 /* aperture size */
1305 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1306
1307 /* address to map to */
1308 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1309 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1310
1311 /* attbase - aperture base */
1312 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1313
1314 /* agpctrl */
1315 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1316
1317 /* mcgcfg */
1318 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1319 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1320 /* clear any possible AGP-related error conditions */
1321 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1322 return 0;
1323 }
1324
1325 static int intel_860_configure(void)
1326 {
1327 u32 temp;
1328 u16 temp2;
1329 struct aper_size_info_8 *current_size;
1330
1331 current_size = A_SIZE_8(agp_bridge->current_size);
1332
1333 /* aperture size */
1334 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1335
1336 /* address to map to */
1337 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1338 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1339
1340 /* attbase - aperture base */
1341 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1342
1343 /* agpctrl */
1344 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1345
1346 /* mcgcfg */
1347 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1348 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1349 /* clear any possible AGP-related error conditions */
1350 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1351 return 0;
1352 }
1353
1354 static int intel_830mp_configure(void)
1355 {
1356 u32 temp;
1357 u16 temp2;
1358 struct aper_size_info_8 *current_size;
1359
1360 current_size = A_SIZE_8(agp_bridge->current_size);
1361
1362 /* aperture size */
1363 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1364
1365 /* address to map to */
1366 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1367 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1368
1369 /* attbase - aperture base */
1370 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1371
1372 /* agpctrl */
1373 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1374
1375 /* gmch */
1376 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1377 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1378 /* clear any possible AGP-related error conditions */
1379 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1380 return 0;
1381 }
1382
1383 static int intel_7505_configure(void)
1384 {
1385 u32 temp;
1386 u16 temp2;
1387 struct aper_size_info_8 *current_size;
1388
1389 current_size = A_SIZE_8(agp_bridge->current_size);
1390
1391 /* aperture size */
1392 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1393
1394 /* address to map to */
1395 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1396 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1397
1398 /* attbase - aperture base */
1399 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1400
1401 /* agpctrl */
1402 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1403
1404 /* mchcfg */
1405 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1406 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1407
1408 return 0;
1409 }
1410
1411 /* Setup function */
1412 static const struct gatt_mask intel_generic_masks[] =
1413 {
1414 {.mask = 0x00000017, .type = 0}
1415 };
1416
1417 static const struct aper_size_info_8 intel_815_sizes[2] =
1418 {
1419 {64, 16384, 4, 0},
1420 {32, 8192, 3, 8},
1421 };
1422
1423 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1424 {
1425 {256, 65536, 6, 0},
1426 {128, 32768, 5, 32},
1427 {64, 16384, 4, 48},
1428 {32, 8192, 3, 56},
1429 {16, 4096, 2, 60},
1430 {8, 2048, 1, 62},
1431 {4, 1024, 0, 63}
1432 };
1433
1434 static const struct aper_size_info_16 intel_generic_sizes[7] =
1435 {
1436 {256, 65536, 6, 0},
1437 {128, 32768, 5, 32},
1438 {64, 16384, 4, 48},
1439 {32, 8192, 3, 56},
1440 {16, 4096, 2, 60},
1441 {8, 2048, 1, 62},
1442 {4, 1024, 0, 63}
1443 };
1444
1445 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1446 {
1447 {256, 65536, 6, 0},
1448 {128, 32768, 5, 32},
1449 {64, 16384, 4, 48},
1450 {32, 8192, 3, 56}
1451 };
1452
1453 static const struct agp_bridge_driver intel_generic_driver = {
1454 .owner = THIS_MODULE,
1455 .aperture_sizes = intel_generic_sizes,
1456 .size_type = U16_APER_SIZE,
1457 .num_aperture_sizes = 7,
1458 .configure = intel_configure,
1459 .fetch_size = intel_fetch_size,
1460 .cleanup = intel_cleanup,
1461 .tlb_flush = intel_tlbflush,
1462 .mask_memory = agp_generic_mask_memory,
1463 .masks = intel_generic_masks,
1464 .agp_enable = agp_generic_enable,
1465 .cache_flush = global_cache_flush,
1466 .create_gatt_table = agp_generic_create_gatt_table,
1467 .free_gatt_table = agp_generic_free_gatt_table,
1468 .insert_memory = agp_generic_insert_memory,
1469 .remove_memory = agp_generic_remove_memory,
1470 .alloc_by_type = agp_generic_alloc_by_type,
1471 .free_by_type = agp_generic_free_by_type,
1472 .agp_alloc_page = agp_generic_alloc_page,
1473 .agp_destroy_page = agp_generic_destroy_page,
1474 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1475 };
1476
1477 static const struct agp_bridge_driver intel_810_driver = {
1478 .owner = THIS_MODULE,
1479 .aperture_sizes = intel_i810_sizes,
1480 .size_type = FIXED_APER_SIZE,
1481 .num_aperture_sizes = 2,
1482 .needs_scratch_page = TRUE,
1483 .configure = intel_i810_configure,
1484 .fetch_size = intel_i810_fetch_size,
1485 .cleanup = intel_i810_cleanup,
1486 .tlb_flush = intel_i810_tlbflush,
1487 .mask_memory = intel_i810_mask_memory,
1488 .masks = intel_i810_masks,
1489 .agp_enable = intel_i810_agp_enable,
1490 .cache_flush = global_cache_flush,
1491 .create_gatt_table = agp_generic_create_gatt_table,
1492 .free_gatt_table = agp_generic_free_gatt_table,
1493 .insert_memory = intel_i810_insert_entries,
1494 .remove_memory = intel_i810_remove_entries,
1495 .alloc_by_type = intel_i810_alloc_by_type,
1496 .free_by_type = intel_i810_free_by_type,
1497 .agp_alloc_page = agp_generic_alloc_page,
1498 .agp_destroy_page = agp_generic_destroy_page,
1499 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1500 };
1501
1502 static const struct agp_bridge_driver intel_815_driver = {
1503 .owner = THIS_MODULE,
1504 .aperture_sizes = intel_815_sizes,
1505 .size_type = U8_APER_SIZE,
1506 .num_aperture_sizes = 2,
1507 .configure = intel_815_configure,
1508 .fetch_size = intel_815_fetch_size,
1509 .cleanup = intel_8xx_cleanup,
1510 .tlb_flush = intel_8xx_tlbflush,
1511 .mask_memory = agp_generic_mask_memory,
1512 .masks = intel_generic_masks,
1513 .agp_enable = agp_generic_enable,
1514 .cache_flush = global_cache_flush,
1515 .create_gatt_table = agp_generic_create_gatt_table,
1516 .free_gatt_table = agp_generic_free_gatt_table,
1517 .insert_memory = agp_generic_insert_memory,
1518 .remove_memory = agp_generic_remove_memory,
1519 .alloc_by_type = agp_generic_alloc_by_type,
1520 .free_by_type = agp_generic_free_by_type,
1521 .agp_alloc_page = agp_generic_alloc_page,
1522 .agp_destroy_page = agp_generic_destroy_page,
1523 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1524 };
1525
1526 static const struct agp_bridge_driver intel_830_driver = {
1527 .owner = THIS_MODULE,
1528 .aperture_sizes = intel_i830_sizes,
1529 .size_type = FIXED_APER_SIZE,
1530 .num_aperture_sizes = 4,
1531 .needs_scratch_page = TRUE,
1532 .configure = intel_i830_configure,
1533 .fetch_size = intel_i830_fetch_size,
1534 .cleanup = intel_i830_cleanup,
1535 .tlb_flush = intel_i810_tlbflush,
1536 .mask_memory = intel_i810_mask_memory,
1537 .masks = intel_i810_masks,
1538 .agp_enable = intel_i810_agp_enable,
1539 .cache_flush = global_cache_flush,
1540 .create_gatt_table = intel_i830_create_gatt_table,
1541 .free_gatt_table = intel_i830_free_gatt_table,
1542 .insert_memory = intel_i830_insert_entries,
1543 .remove_memory = intel_i830_remove_entries,
1544 .alloc_by_type = intel_i830_alloc_by_type,
1545 .free_by_type = intel_i810_free_by_type,
1546 .agp_alloc_page = agp_generic_alloc_page,
1547 .agp_destroy_page = agp_generic_destroy_page,
1548 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1549 };
1550
1551 static const struct agp_bridge_driver intel_820_driver = {
1552 .owner = THIS_MODULE,
1553 .aperture_sizes = intel_8xx_sizes,
1554 .size_type = U8_APER_SIZE,
1555 .num_aperture_sizes = 7,
1556 .configure = intel_820_configure,
1557 .fetch_size = intel_8xx_fetch_size,
1558 .cleanup = intel_820_cleanup,
1559 .tlb_flush = intel_820_tlbflush,
1560 .mask_memory = agp_generic_mask_memory,
1561 .masks = intel_generic_masks,
1562 .agp_enable = agp_generic_enable,
1563 .cache_flush = global_cache_flush,
1564 .create_gatt_table = agp_generic_create_gatt_table,
1565 .free_gatt_table = agp_generic_free_gatt_table,
1566 .insert_memory = agp_generic_insert_memory,
1567 .remove_memory = agp_generic_remove_memory,
1568 .alloc_by_type = agp_generic_alloc_by_type,
1569 .free_by_type = agp_generic_free_by_type,
1570 .agp_alloc_page = agp_generic_alloc_page,
1571 .agp_destroy_page = agp_generic_destroy_page,
1572 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1573 };
1574
1575 static const struct agp_bridge_driver intel_830mp_driver = {
1576 .owner = THIS_MODULE,
1577 .aperture_sizes = intel_830mp_sizes,
1578 .size_type = U8_APER_SIZE,
1579 .num_aperture_sizes = 4,
1580 .configure = intel_830mp_configure,
1581 .fetch_size = intel_8xx_fetch_size,
1582 .cleanup = intel_8xx_cleanup,
1583 .tlb_flush = intel_8xx_tlbflush,
1584 .mask_memory = agp_generic_mask_memory,
1585 .masks = intel_generic_masks,
1586 .agp_enable = agp_generic_enable,
1587 .cache_flush = global_cache_flush,
1588 .create_gatt_table = agp_generic_create_gatt_table,
1589 .free_gatt_table = agp_generic_free_gatt_table,
1590 .insert_memory = agp_generic_insert_memory,
1591 .remove_memory = agp_generic_remove_memory,
1592 .alloc_by_type = agp_generic_alloc_by_type,
1593 .free_by_type = agp_generic_free_by_type,
1594 .agp_alloc_page = agp_generic_alloc_page,
1595 .agp_destroy_page = agp_generic_destroy_page,
1596 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1597 };
1598
1599 static const struct agp_bridge_driver intel_840_driver = {
1600 .owner = THIS_MODULE,
1601 .aperture_sizes = intel_8xx_sizes,
1602 .size_type = U8_APER_SIZE,
1603 .num_aperture_sizes = 7,
1604 .configure = intel_840_configure,
1605 .fetch_size = intel_8xx_fetch_size,
1606 .cleanup = intel_8xx_cleanup,
1607 .tlb_flush = intel_8xx_tlbflush,
1608 .mask_memory = agp_generic_mask_memory,
1609 .masks = intel_generic_masks,
1610 .agp_enable = agp_generic_enable,
1611 .cache_flush = global_cache_flush,
1612 .create_gatt_table = agp_generic_create_gatt_table,
1613 .free_gatt_table = agp_generic_free_gatt_table,
1614 .insert_memory = agp_generic_insert_memory,
1615 .remove_memory = agp_generic_remove_memory,
1616 .alloc_by_type = agp_generic_alloc_by_type,
1617 .free_by_type = agp_generic_free_by_type,
1618 .agp_alloc_page = agp_generic_alloc_page,
1619 .agp_destroy_page = agp_generic_destroy_page,
1620 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1621 };
1622
1623 static const struct agp_bridge_driver intel_845_driver = {
1624 .owner = THIS_MODULE,
1625 .aperture_sizes = intel_8xx_sizes,
1626 .size_type = U8_APER_SIZE,
1627 .num_aperture_sizes = 7,
1628 .configure = intel_845_configure,
1629 .fetch_size = intel_8xx_fetch_size,
1630 .cleanup = intel_8xx_cleanup,
1631 .tlb_flush = intel_8xx_tlbflush,
1632 .mask_memory = agp_generic_mask_memory,
1633 .masks = intel_generic_masks,
1634 .agp_enable = agp_generic_enable,
1635 .cache_flush = global_cache_flush,
1636 .create_gatt_table = agp_generic_create_gatt_table,
1637 .free_gatt_table = agp_generic_free_gatt_table,
1638 .insert_memory = agp_generic_insert_memory,
1639 .remove_memory = agp_generic_remove_memory,
1640 .alloc_by_type = agp_generic_alloc_by_type,
1641 .free_by_type = agp_generic_free_by_type,
1642 .agp_alloc_page = agp_generic_alloc_page,
1643 .agp_destroy_page = agp_generic_destroy_page,
1644 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1645 };
1646
1647 static const struct agp_bridge_driver intel_850_driver = {
1648 .owner = THIS_MODULE,
1649 .aperture_sizes = intel_8xx_sizes,
1650 .size_type = U8_APER_SIZE,
1651 .num_aperture_sizes = 7,
1652 .configure = intel_850_configure,
1653 .fetch_size = intel_8xx_fetch_size,
1654 .cleanup = intel_8xx_cleanup,
1655 .tlb_flush = intel_8xx_tlbflush,
1656 .mask_memory = agp_generic_mask_memory,
1657 .masks = intel_generic_masks,
1658 .agp_enable = agp_generic_enable,
1659 .cache_flush = global_cache_flush,
1660 .create_gatt_table = agp_generic_create_gatt_table,
1661 .free_gatt_table = agp_generic_free_gatt_table,
1662 .insert_memory = agp_generic_insert_memory,
1663 .remove_memory = agp_generic_remove_memory,
1664 .alloc_by_type = agp_generic_alloc_by_type,
1665 .free_by_type = agp_generic_free_by_type,
1666 .agp_alloc_page = agp_generic_alloc_page,
1667 .agp_destroy_page = agp_generic_destroy_page,
1668 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1669 };
1670
1671 static const struct agp_bridge_driver intel_860_driver = {
1672 .owner = THIS_MODULE,
1673 .aperture_sizes = intel_8xx_sizes,
1674 .size_type = U8_APER_SIZE,
1675 .num_aperture_sizes = 7,
1676 .configure = intel_860_configure,
1677 .fetch_size = intel_8xx_fetch_size,
1678 .cleanup = intel_8xx_cleanup,
1679 .tlb_flush = intel_8xx_tlbflush,
1680 .mask_memory = agp_generic_mask_memory,
1681 .masks = intel_generic_masks,
1682 .agp_enable = agp_generic_enable,
1683 .cache_flush = global_cache_flush,
1684 .create_gatt_table = agp_generic_create_gatt_table,
1685 .free_gatt_table = agp_generic_free_gatt_table,
1686 .insert_memory = agp_generic_insert_memory,
1687 .remove_memory = agp_generic_remove_memory,
1688 .alloc_by_type = agp_generic_alloc_by_type,
1689 .free_by_type = agp_generic_free_by_type,
1690 .agp_alloc_page = agp_generic_alloc_page,
1691 .agp_destroy_page = agp_generic_destroy_page,
1692 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1693 };
1694
1695 static const struct agp_bridge_driver intel_915_driver = {
1696 .owner = THIS_MODULE,
1697 .aperture_sizes = intel_i830_sizes,
1698 .size_type = FIXED_APER_SIZE,
1699 .num_aperture_sizes = 4,
1700 .needs_scratch_page = TRUE,
1701 .configure = intel_i915_configure,
1702 .fetch_size = intel_i9xx_fetch_size,
1703 .cleanup = intel_i915_cleanup,
1704 .tlb_flush = intel_i810_tlbflush,
1705 .mask_memory = intel_i810_mask_memory,
1706 .masks = intel_i810_masks,
1707 .agp_enable = intel_i810_agp_enable,
1708 .cache_flush = global_cache_flush,
1709 .create_gatt_table = intel_i915_create_gatt_table,
1710 .free_gatt_table = intel_i830_free_gatt_table,
1711 .insert_memory = intel_i915_insert_entries,
1712 .remove_memory = intel_i915_remove_entries,
1713 .alloc_by_type = intel_i830_alloc_by_type,
1714 .free_by_type = intel_i810_free_by_type,
1715 .agp_alloc_page = agp_generic_alloc_page,
1716 .agp_destroy_page = agp_generic_destroy_page,
1717 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1718 };
1719
1720 static const struct agp_bridge_driver intel_i965_driver = {
1721 .owner = THIS_MODULE,
1722 .aperture_sizes = intel_i830_sizes,
1723 .size_type = FIXED_APER_SIZE,
1724 .num_aperture_sizes = 4,
1725 .needs_scratch_page = TRUE,
1726 .configure = intel_i915_configure,
1727 .fetch_size = intel_i9xx_fetch_size,
1728 .cleanup = intel_i915_cleanup,
1729 .tlb_flush = intel_i810_tlbflush,
1730 .mask_memory = intel_i965_mask_memory,
1731 .masks = intel_i810_masks,
1732 .agp_enable = intel_i810_agp_enable,
1733 .cache_flush = global_cache_flush,
1734 .create_gatt_table = intel_i965_create_gatt_table,
1735 .free_gatt_table = intel_i830_free_gatt_table,
1736 .insert_memory = intel_i915_insert_entries,
1737 .remove_memory = intel_i915_remove_entries,
1738 .alloc_by_type = intel_i830_alloc_by_type,
1739 .free_by_type = intel_i810_free_by_type,
1740 .agp_alloc_page = agp_generic_alloc_page,
1741 .agp_destroy_page = agp_generic_destroy_page,
1742 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1743 };
1744
1745 static const struct agp_bridge_driver intel_7505_driver = {
1746 .owner = THIS_MODULE,
1747 .aperture_sizes = intel_8xx_sizes,
1748 .size_type = U8_APER_SIZE,
1749 .num_aperture_sizes = 7,
1750 .configure = intel_7505_configure,
1751 .fetch_size = intel_8xx_fetch_size,
1752 .cleanup = intel_8xx_cleanup,
1753 .tlb_flush = intel_8xx_tlbflush,
1754 .mask_memory = agp_generic_mask_memory,
1755 .masks = intel_generic_masks,
1756 .agp_enable = agp_generic_enable,
1757 .cache_flush = global_cache_flush,
1758 .create_gatt_table = agp_generic_create_gatt_table,
1759 .free_gatt_table = agp_generic_free_gatt_table,
1760 .insert_memory = agp_generic_insert_memory,
1761 .remove_memory = agp_generic_remove_memory,
1762 .alloc_by_type = agp_generic_alloc_by_type,
1763 .free_by_type = agp_generic_free_by_type,
1764 .agp_alloc_page = agp_generic_alloc_page,
1765 .agp_destroy_page = agp_generic_destroy_page,
1766 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1767 };
1768
1769 static const struct agp_bridge_driver intel_g33_driver = {
1770 .owner = THIS_MODULE,
1771 .aperture_sizes = intel_i830_sizes,
1772 .size_type = FIXED_APER_SIZE,
1773 .num_aperture_sizes = 4,
1774 .needs_scratch_page = TRUE,
1775 .configure = intel_i915_configure,
1776 .fetch_size = intel_i9xx_fetch_size,
1777 .cleanup = intel_i915_cleanup,
1778 .tlb_flush = intel_i810_tlbflush,
1779 .mask_memory = intel_i965_mask_memory,
1780 .masks = intel_i810_masks,
1781 .agp_enable = intel_i810_agp_enable,
1782 .cache_flush = global_cache_flush,
1783 .create_gatt_table = intel_i915_create_gatt_table,
1784 .free_gatt_table = intel_i830_free_gatt_table,
1785 .insert_memory = intel_i915_insert_entries,
1786 .remove_memory = intel_i915_remove_entries,
1787 .alloc_by_type = intel_i830_alloc_by_type,
1788 .free_by_type = intel_i810_free_by_type,
1789 .agp_alloc_page = agp_generic_alloc_page,
1790 .agp_destroy_page = agp_generic_destroy_page,
1791 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1792 };
1793
1794 static int find_gmch(u16 device)
1795 {
1796 struct pci_dev *gmch_device;
1797
1798 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1799 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1800 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1801 device, gmch_device);
1802 }
1803
1804 if (!gmch_device)
1805 return 0;
1806
1807 intel_private.pcidev = gmch_device;
1808 return 1;
1809 }
1810
1811 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1812 * driver and gmch_driver must be non-null, and find_gmch will determine
1813 * which one should be used if a gmch_chip_id is present.
1814 */
1815 static const struct intel_driver_description {
1816 unsigned int chip_id;
1817 unsigned int gmch_chip_id;
1818 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1819 char *name;
1820 const struct agp_bridge_driver *driver;
1821 const struct agp_bridge_driver *gmch_driver;
1822 } intel_agp_chipsets[] = {
1823 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1824 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1825 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1826 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1827 NULL, &intel_810_driver },
1828 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1829 NULL, &intel_810_driver },
1830 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1831 NULL, &intel_810_driver },
1832 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1833 &intel_815_driver, &intel_810_driver },
1834 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1835 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1836 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1837 &intel_830mp_driver, &intel_830_driver },
1838 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1839 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1840 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1841 &intel_845_driver, &intel_830_driver },
1842 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1843 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1844 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
1845 &intel_845_driver, &intel_830_driver },
1846 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1847 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
1848 &intel_845_driver, &intel_830_driver },
1849 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
1850 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
1851 NULL, &intel_915_driver },
1852 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
1853 NULL, &intel_915_driver },
1854 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
1855 NULL, &intel_915_driver },
1856 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
1857 NULL, &intel_915_driver },
1858 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
1859 NULL, &intel_915_driver },
1860 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
1861 NULL, &intel_i965_driver },
1862 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
1863 NULL, &intel_i965_driver },
1864 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
1865 NULL, &intel_i965_driver },
1866 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
1867 NULL, &intel_i965_driver },
1868 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
1869 NULL, &intel_i965_driver },
1870 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
1871 NULL, &intel_i965_driver },
1872 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1873 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1874 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
1875 NULL, &intel_g33_driver },
1876 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
1877 NULL, &intel_g33_driver },
1878 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
1879 NULL, &intel_g33_driver },
1880 { 0, 0, 0, NULL, NULL, NULL }
1881 };
1882
1883 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1884 const struct pci_device_id *ent)
1885 {
1886 struct agp_bridge_data *bridge;
1887 u8 cap_ptr = 0;
1888 struct resource *r;
1889 int i;
1890
1891 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1892
1893 bridge = agp_alloc_bridge();
1894 if (!bridge)
1895 return -ENOMEM;
1896
1897 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1898 /* In case that multiple models of gfx chip may
1899 stand on same host bridge type, this can be
1900 sure we detect the right IGD. */
1901 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1902 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1903 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1904 bridge->driver =
1905 intel_agp_chipsets[i].gmch_driver;
1906 break;
1907 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1908 continue;
1909 } else {
1910 bridge->driver = intel_agp_chipsets[i].driver;
1911 break;
1912 }
1913 }
1914 }
1915
1916 if (intel_agp_chipsets[i].name == NULL) {
1917 if (cap_ptr)
1918 printk(KERN_WARNING PFX "Unsupported Intel chipset"
1919 "(device id: %04x)\n", pdev->device);
1920 agp_put_bridge(bridge);
1921 return -ENODEV;
1922 }
1923
1924 if (bridge->driver == NULL) {
1925 /* bridge has no AGP and no IGD detected */
1926 if (cap_ptr)
1927 printk(KERN_WARNING PFX "Failed to find bridge device "
1928 "(chip_id: %04x)\n",
1929 intel_agp_chipsets[i].gmch_chip_id);
1930 agp_put_bridge(bridge);
1931 return -ENODEV;
1932 }
1933
1934 bridge->dev = pdev;
1935 bridge->capndx = cap_ptr;
1936 bridge->dev_private_data = &intel_private;
1937
1938 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1939 intel_agp_chipsets[i].name);
1940
1941 /*
1942 * The following fixes the case where the BIOS has "forgotten" to
1943 * provide an address range for the GART.
1944 * 20030610 - hamish@zot.org
1945 */
1946 r = &pdev->resource[0];
1947 if (!r->start && r->end) {
1948 if (pci_assign_resource(pdev, 0)) {
1949 printk(KERN_ERR PFX "could not assign resource 0\n");
1950 agp_put_bridge(bridge);
1951 return -ENODEV;
1952 }
1953 }
1954
1955 /*
1956 * If the device has not been properly setup, the following will catch
1957 * the problem and should stop the system from crashing.
1958 * 20030610 - hamish@zot.org
1959 */
1960 if (pci_enable_device(pdev)) {
1961 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1962 agp_put_bridge(bridge);
1963 return -ENODEV;
1964 }
1965
1966 /* Fill in the mode register */
1967 if (cap_ptr) {
1968 pci_read_config_dword(pdev,
1969 bridge->capndx+PCI_AGP_STATUS,
1970 &bridge->mode);
1971 }
1972
1973 pci_set_drvdata(pdev, bridge);
1974 return agp_add_bridge(bridge);
1975 }
1976
1977 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1978 {
1979 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1980
1981 agp_remove_bridge(bridge);
1982
1983 if (intel_private.pcidev)
1984 pci_dev_put(intel_private.pcidev);
1985
1986 agp_put_bridge(bridge);
1987 }
1988
1989 #ifdef CONFIG_PM
1990 static int agp_intel_resume(struct pci_dev *pdev)
1991 {
1992 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1993
1994 pci_restore_state(pdev);
1995
1996 /* We should restore our graphics device's config space,
1997 * as host bridge (00:00) resumes before graphics device (02:00),
1998 * then our access to its pci space can work right.
1999 */
2000 if (intel_private.pcidev)
2001 pci_restore_state(intel_private.pcidev);
2002
2003 if (bridge->driver == &intel_generic_driver)
2004 intel_configure();
2005 else if (bridge->driver == &intel_850_driver)
2006 intel_850_configure();
2007 else if (bridge->driver == &intel_845_driver)
2008 intel_845_configure();
2009 else if (bridge->driver == &intel_830mp_driver)
2010 intel_830mp_configure();
2011 else if (bridge->driver == &intel_915_driver)
2012 intel_i915_configure();
2013 else if (bridge->driver == &intel_830_driver)
2014 intel_i830_configure();
2015 else if (bridge->driver == &intel_810_driver)
2016 intel_i810_configure();
2017 else if (bridge->driver == &intel_i965_driver)
2018 intel_i915_configure();
2019
2020 return 0;
2021 }
2022 #endif
2023
2024 static struct pci_device_id agp_intel_pci_table[] = {
2025 #define ID(x) \
2026 { \
2027 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2028 .class_mask = ~0, \
2029 .vendor = PCI_VENDOR_ID_INTEL, \
2030 .device = x, \
2031 .subvendor = PCI_ANY_ID, \
2032 .subdevice = PCI_ANY_ID, \
2033 }
2034 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2035 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2036 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2037 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2038 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2039 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2040 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2041 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2042 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2043 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2044 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2045 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2046 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2047 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2048 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2049 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2050 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2051 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2052 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2053 ID(PCI_DEVICE_ID_INTEL_7505_0),
2054 ID(PCI_DEVICE_ID_INTEL_7205_0),
2055 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2056 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2057 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2058 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2059 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2060 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2061 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2062 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2063 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2064 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2065 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2066 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2067 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2068 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2069 { }
2070 };
2071
2072 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2073
2074 static struct pci_driver agp_intel_pci_driver = {
2075 .name = "agpgart-intel",
2076 .id_table = agp_intel_pci_table,
2077 .probe = agp_intel_probe,
2078 .remove = __devexit_p(agp_intel_remove),
2079 #ifdef CONFIG_PM
2080 .resume = agp_intel_resume,
2081 #endif
2082 };
2083
2084 static int __init agp_intel_init(void)
2085 {
2086 if (agp_off)
2087 return -EINVAL;
2088 return pci_register_driver(&agp_intel_pci_driver);
2089 }
2090
2091 static void __exit agp_intel_cleanup(void)
2092 {
2093 pci_unregister_driver(&agp_intel_pci_driver);
2094 }
2095
2096 module_init(agp_intel_init);
2097 module_exit(agp_intel_cleanup);
2098
2099 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2100 MODULE_LICENSE("GPL and additional rights");
Tomato firmware and modifications.