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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / ata / sata_promise.c
blob681b76a04e5ae2357fee26ff716cfeda515346f6
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.07"
49
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* register offsets */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL = 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR = (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
89 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
90 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
91 | PDC1_ERR_MASK | PDC2_ERR_MASK),
92
93 board_2037x = 0, /* FastTrak S150 TX2plus */
94 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
95 board_20319 = 2, /* FastTrak S150 TX4 */
96 board_20619 = 3, /* FastTrak TX4000 */
97 board_2057x = 4, /* SATAII150 Tx2plus */
98 board_2057x_pata = 5, /* SATAII150 Tx2plus */
99 board_40518 = 6, /* SATAII150 Tx4 */
100
101 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
102
103 /* Sequence counter control registers bit definitions */
104 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
105
106 /* Feature register values */
107 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
108 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
109
110 /* Device/Head register values */
111 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
112
113 /* PDC_CTLSTAT bit definitions */
114 PDC_DMA_ENABLE = (1 << 7),
115 PDC_IRQ_DISABLE = (1 << 10),
116 PDC_RESET = (1 << 11), /* HDMA reset */
117
118 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
119 ATA_FLAG_MMIO |
120 ATA_FLAG_PIO_POLLING,
121
122 /* ap->flags bits */
123 PDC_FLAG_GEN_II = (1 << 24),
124 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
125 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
126 };
127
128
129 struct pdc_port_priv {
130 u8 *pkt;
131 dma_addr_t pkt_dma;
132 };
133
134 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
135 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
136 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
137 static int pdc_common_port_start(struct ata_port *ap);
138 static int pdc_sata_port_start(struct ata_port *ap);
139 static void pdc_qc_prep(struct ata_queued_cmd *qc);
140 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
141 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
143 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
144 static void pdc_irq_clear(struct ata_port *ap);
145 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
146 static void pdc_freeze(struct ata_port *ap);
147 static void pdc_thaw(struct ata_port *ap);
148 static void pdc_pata_error_handler(struct ata_port *ap);
149 static void pdc_sata_error_handler(struct ata_port *ap);
150 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
151 static int pdc_pata_cable_detect(struct ata_port *ap);
152 static int pdc_sata_cable_detect(struct ata_port *ap);
153
154 static struct scsi_host_template pdc_ata_sht = {
155 .module = THIS_MODULE,
156 .name = DRV_NAME,
157 .ioctl = ata_scsi_ioctl,
158 .queuecommand = ata_scsi_queuecmd,
159 .can_queue = ATA_DEF_QUEUE,
160 .this_id = ATA_SHT_THIS_ID,
161 .sg_tablesize = PDC_MAX_PRD,
162 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
163 .emulated = ATA_SHT_EMULATED,
164 .use_clustering = ATA_SHT_USE_CLUSTERING,
165 .proc_name = DRV_NAME,
166 .dma_boundary = ATA_DMA_BOUNDARY,
167 .slave_configure = ata_scsi_slave_config,
168 .slave_destroy = ata_scsi_slave_destroy,
169 .bios_param = ata_std_bios_param,
170 };
171
172 static const struct ata_port_operations pdc_sata_ops = {
173 .port_disable = ata_port_disable,
174 .tf_load = pdc_tf_load_mmio,
175 .tf_read = ata_tf_read,
176 .check_status = ata_check_status,
177 .exec_command = pdc_exec_command_mmio,
178 .dev_select = ata_std_dev_select,
179 .check_atapi_dma = pdc_check_atapi_dma,
180
181 .qc_prep = pdc_qc_prep,
182 .qc_issue = pdc_qc_issue_prot,
183 .freeze = pdc_freeze,
184 .thaw = pdc_thaw,
185 .error_handler = pdc_sata_error_handler,
186 .post_internal_cmd = pdc_post_internal_cmd,
187 .cable_detect = pdc_sata_cable_detect,
188 .data_xfer = ata_data_xfer,
189 .irq_clear = pdc_irq_clear,
190 .irq_on = ata_irq_on,
191 .irq_ack = ata_irq_ack,
192
193 .scr_read = pdc_sata_scr_read,
194 .scr_write = pdc_sata_scr_write,
195 .port_start = pdc_sata_port_start,
196 };
197
198 /* First-generation chips need a more restrictive ->check_atapi_dma op */
199 static const struct ata_port_operations pdc_old_sata_ops = {
200 .port_disable = ata_port_disable,
201 .tf_load = pdc_tf_load_mmio,
202 .tf_read = ata_tf_read,
203 .check_status = ata_check_status,
204 .exec_command = pdc_exec_command_mmio,
205 .dev_select = ata_std_dev_select,
206 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
207
208 .qc_prep = pdc_qc_prep,
209 .qc_issue = pdc_qc_issue_prot,
210 .freeze = pdc_freeze,
211 .thaw = pdc_thaw,
212 .error_handler = pdc_sata_error_handler,
213 .post_internal_cmd = pdc_post_internal_cmd,
214 .cable_detect = pdc_sata_cable_detect,
215 .data_xfer = ata_data_xfer,
216 .irq_clear = pdc_irq_clear,
217 .irq_on = ata_irq_on,
218 .irq_ack = ata_irq_ack,
219
220 .scr_read = pdc_sata_scr_read,
221 .scr_write = pdc_sata_scr_write,
222 .port_start = pdc_sata_port_start,
223 };
224
225 static const struct ata_port_operations pdc_pata_ops = {
226 .port_disable = ata_port_disable,
227 .tf_load = pdc_tf_load_mmio,
228 .tf_read = ata_tf_read,
229 .check_status = ata_check_status,
230 .exec_command = pdc_exec_command_mmio,
231 .dev_select = ata_std_dev_select,
232 .check_atapi_dma = pdc_check_atapi_dma,
233
234 .qc_prep = pdc_qc_prep,
235 .qc_issue = pdc_qc_issue_prot,
236 .freeze = pdc_freeze,
237 .thaw = pdc_thaw,
238 .error_handler = pdc_pata_error_handler,
239 .post_internal_cmd = pdc_post_internal_cmd,
240 .cable_detect = pdc_pata_cable_detect,
241 .data_xfer = ata_data_xfer,
242 .irq_clear = pdc_irq_clear,
243 .irq_on = ata_irq_on,
244 .irq_ack = ata_irq_ack,
245
246 .port_start = pdc_common_port_start,
247 };
248
249 static const struct ata_port_info pdc_port_info[] = {
250 /* board_2037x */
251 {
252 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
253 PDC_FLAG_SATA_PATA,
254 .pio_mask = 0x1f, /* pio0-4 */
255 .mwdma_mask = 0x07, /* mwdma0-2 */
256 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
257 .port_ops = &pdc_old_sata_ops,
258 },
259
260 /* board_2037x_pata */
261 {
262 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
263 .pio_mask = 0x1f, /* pio0-4 */
264 .mwdma_mask = 0x07, /* mwdma0-2 */
265 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
266 .port_ops = &pdc_pata_ops,
267 },
268
269 /* board_20319 */
270 {
271 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
272 PDC_FLAG_4_PORTS,
273 .pio_mask = 0x1f, /* pio0-4 */
274 .mwdma_mask = 0x07, /* mwdma0-2 */
275 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
276 .port_ops = &pdc_old_sata_ops,
277 },
278
279 /* board_20619 */
280 {
281 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
282 PDC_FLAG_4_PORTS,
283 .pio_mask = 0x1f, /* pio0-4 */
284 .mwdma_mask = 0x07, /* mwdma0-2 */
285 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
286 .port_ops = &pdc_pata_ops,
287 },
288
289 /* board_2057x */
290 {
291 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
292 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
293 .pio_mask = 0x1f, /* pio0-4 */
294 .mwdma_mask = 0x07, /* mwdma0-2 */
295 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
296 .port_ops = &pdc_sata_ops,
297 },
298
299 /* board_2057x_pata */
300 {
301 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
302 PDC_FLAG_GEN_II,
303 .pio_mask = 0x1f, /* pio0-4 */
304 .mwdma_mask = 0x07, /* mwdma0-2 */
305 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
306 .port_ops = &pdc_pata_ops,
307 },
308
309 /* board_40518 */
310 {
311 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
312 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
313 .pio_mask = 0x1f, /* pio0-4 */
314 .mwdma_mask = 0x07, /* mwdma0-2 */
315 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
316 .port_ops = &pdc_sata_ops,
317 },
318 };
319
320 static const struct pci_device_id pdc_ata_pci_tbl[] = {
321 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
322 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
323 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
324 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
325 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
326 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
327 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
328 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
329 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
330 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
331
332 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
333 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
334 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
335 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
336 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
337 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
338
339 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
340
341 { } /* terminate list */
342 };
343
344
345 static struct pci_driver pdc_ata_pci_driver = {
346 .name = DRV_NAME,
347 .id_table = pdc_ata_pci_tbl,
348 .probe = pdc_ata_init_one,
349 .remove = ata_pci_remove_one,
350 };
351
352
353 static int pdc_common_port_start(struct ata_port *ap)
354 {
355 struct device *dev = ap->host->dev;
356 struct pdc_port_priv *pp;
357 int rc;
358
359 rc = ata_port_start(ap);
360 if (rc)
361 return rc;
362
363 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
364 if (!pp)
365 return -ENOMEM;
366
367 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
368 if (!pp->pkt)
369 return -ENOMEM;
370
371 ap->private_data = pp;
372
373 return 0;
374 }
375
376 static int pdc_sata_port_start(struct ata_port *ap)
377 {
378 int rc;
379
380 rc = pdc_common_port_start(ap);
381 if (rc)
382 return rc;
383
384 /* fix up PHYMODE4 align timing */
385 if (ap->flags & PDC_FLAG_GEN_II) {
386 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
387 unsigned int tmp;
388
389 tmp = readl(mmio + 0x014);
390 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
391 writel(tmp, mmio + 0x014);
392 }
393
394 return 0;
395 }
396
397 static void pdc_reset_port(struct ata_port *ap)
398 {
399 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
400 unsigned int i;
401 u32 tmp;
402
403 for (i = 11; i > 0; i--) {
404 tmp = readl(mmio);
405 if (tmp & PDC_RESET)
406 break;
407
408 udelay(100);
409
410 tmp |= PDC_RESET;
411 writel(tmp, mmio);
412 }
413
414 tmp &= ~PDC_RESET;
415 writel(tmp, mmio);
416 readl(mmio); /* flush */
417 }
418
419 static int pdc_pata_cable_detect(struct ata_port *ap)
420 {
421 u8 tmp;
422 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
423
424 tmp = readb(mmio);
425 if (tmp & 0x01)
426 return ATA_CBL_PATA40;
427 return ATA_CBL_PATA80;
428 }
429
430 static int pdc_sata_cable_detect(struct ata_port *ap)
431 {
432 return ATA_CBL_SATA;
433 }
434
435 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
436 {
437 if (sc_reg > SCR_CONTROL)
438 return 0xffffffffU;
439 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
440 }
441
442
443 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
444 u32 val)
445 {
446 if (sc_reg > SCR_CONTROL)
447 return;
448 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
449 }
450
451 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
452 {
453 struct ata_port *ap = qc->ap;
454 dma_addr_t sg_table = ap->prd_dma;
455 unsigned int cdb_len = qc->dev->cdb_len;
456 u8 *cdb = qc->cdb;
457 struct pdc_port_priv *pp = ap->private_data;
458 u8 *buf = pp->pkt;
459 u32 *buf32 = (u32 *) buf;
460 unsigned int dev_sel, feature, nbytes;
461
462 /* set control bits (byte 0), zero delay seq id (byte 3),
463 * and seq id (byte 2)
464 */
465 switch (qc->tf.protocol) {
466 case ATA_PROT_ATAPI_DMA:
467 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
468 buf32[0] = cpu_to_le32(PDC_PKT_READ);
469 else
470 buf32[0] = 0;
471 break;
472 case ATA_PROT_ATAPI_NODATA:
473 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
474 break;
475 default:
476 BUG();
477 break;
478 }
479 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
480 buf32[2] = 0; /* no next-packet */
481
482 /* select drive */
483 if (sata_scr_valid(ap)) {
484 dev_sel = PDC_DEVICE_SATA;
485 } else {
486 dev_sel = ATA_DEVICE_OBS;
487 if (qc->dev->devno != 0)
488 dev_sel |= ATA_DEV1;
489 }
490 buf[12] = (1 << 5) | ATA_REG_DEVICE;
491 buf[13] = dev_sel;
492 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
493 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
494
495 buf[16] = (1 << 5) | ATA_REG_NSECT;
496 buf[17] = 0x00;
497 buf[18] = (1 << 5) | ATA_REG_LBAL;
498 buf[19] = 0x00;
499
500 /* set feature and byte counter registers */
501 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
502 feature = PDC_FEATURE_ATAPI_PIO;
503 /* set byte counter register to real transfer byte count */
504 nbytes = qc->nbytes;
505 if (nbytes > 0xffff)
506 nbytes = 0xffff;
507 } else {
508 feature = PDC_FEATURE_ATAPI_DMA;
509 /* set byte counter register to 0 */
510 nbytes = 0;
511 }
512 buf[20] = (1 << 5) | ATA_REG_FEATURE;
513 buf[21] = feature;
514 buf[22] = (1 << 5) | ATA_REG_BYTEL;
515 buf[23] = nbytes & 0xFF;
516 buf[24] = (1 << 5) | ATA_REG_BYTEH;
517 buf[25] = (nbytes >> 8) & 0xFF;
518
519 /* send ATAPI packet command 0xA0 */
520 buf[26] = (1 << 5) | ATA_REG_CMD;
521 buf[27] = ATA_CMD_PACKET;
522
523 /* select drive and check DRQ */
524 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
525 buf[29] = dev_sel;
526
527 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
528 BUG_ON(cdb_len & ~0x1E);
529
530 /* append the CDB as the final part */
531 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
532 memcpy(buf+31, cdb, cdb_len);
533 }
534
535 /**
536 * pdc_fill_sg - Fill PCI IDE PRD table
537 * @qc: Metadata associated with taskfile to be transferred
538 *
539 * Fill PCI IDE PRD (scatter-gather) table with segments
540 * associated with the current disk command.
541 * Make sure hardware does not choke on it.
542 *
543 * LOCKING:
544 * spin_lock_irqsave(host lock)
545 *
546 */
547 static void pdc_fill_sg(struct ata_queued_cmd *qc)
548 {
549 struct ata_port *ap = qc->ap;
550 struct scatterlist *sg;
551 unsigned int idx;
552 const u32 SG_COUNT_ASIC_BUG = 41*4;
553
554 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
555 return;
556
557 WARN_ON(qc->__sg == NULL);
558 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
559
560 idx = 0;
561 ata_for_each_sg(sg, qc) {
562 u32 addr, offset;
563 u32 sg_len, len;
564
565 /* determine if physical DMA addr spans 64K boundary.
566 * Note h/w doesn't support 64-bit, so we unconditionally
567 * truncate dma_addr_t to u32.
568 */
569 addr = (u32) sg_dma_address(sg);
570 sg_len = sg_dma_len(sg);
571
572 while (sg_len) {
573 offset = addr & 0xffff;
574 len = sg_len;
575 if ((offset + sg_len) > 0x10000)
576 len = 0x10000 - offset;
577
578 ap->prd[idx].addr = cpu_to_le32(addr);
579 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
580 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
581
582 idx++;
583 sg_len -= len;
584 addr += len;
585 }
586 }
587
588 if (idx) {
589 u32 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
590
591 if (len > SG_COUNT_ASIC_BUG) {
592 u32 addr;
593
594 VPRINTK("Splitting last PRD.\n");
595
596 addr = le32_to_cpu(ap->prd[idx - 1].addr);
597 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
598 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
599
600 addr = addr + len - SG_COUNT_ASIC_BUG;
601 len = SG_COUNT_ASIC_BUG;
602 ap->prd[idx].addr = cpu_to_le32(addr);
603 ap->prd[idx].flags_len = cpu_to_le32(len);
604 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
605
606 idx++;
607 }
608
609 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
610 }
611 }
612
613 static void pdc_qc_prep(struct ata_queued_cmd *qc)
614 {
615 struct pdc_port_priv *pp = qc->ap->private_data;
616 unsigned int i;
617
618 VPRINTK("ENTER\n");
619
620 switch (qc->tf.protocol) {
621 case ATA_PROT_DMA:
622 pdc_fill_sg(qc);
623 /* fall through */
624
625 case ATA_PROT_NODATA:
626 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
627 qc->dev->devno, pp->pkt);
628
629 if (qc->tf.flags & ATA_TFLAG_LBA48)
630 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
631 else
632 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
633
634 pdc_pkt_footer(&qc->tf, pp->pkt, i);
635 break;
636
637 case ATA_PROT_ATAPI:
638 pdc_fill_sg(qc);
639 break;
640
641 case ATA_PROT_ATAPI_DMA:
642 pdc_fill_sg(qc);
643 /*FALLTHROUGH*/
644 case ATA_PROT_ATAPI_NODATA:
645 pdc_atapi_pkt(qc);
646 break;
647
648 default:
649 break;
650 }
651 }
652
653 static void pdc_freeze(struct ata_port *ap)
654 {
655 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
656 u32 tmp;
657
658 tmp = readl(mmio + PDC_CTLSTAT);
659 tmp |= PDC_IRQ_DISABLE;
660 tmp &= ~PDC_DMA_ENABLE;
661 writel(tmp, mmio + PDC_CTLSTAT);
662 readl(mmio + PDC_CTLSTAT); /* flush */
663 }
664
665 static void pdc_thaw(struct ata_port *ap)
666 {
667 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
668 u32 tmp;
669
670 /* clear IRQ */
671 readl(mmio + PDC_INT_SEQMASK);
672
673 /* turn IRQ back on */
674 tmp = readl(mmio + PDC_CTLSTAT);
675 tmp &= ~PDC_IRQ_DISABLE;
676 writel(tmp, mmio + PDC_CTLSTAT);
677 readl(mmio + PDC_CTLSTAT); /* flush */
678 }
679
680 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
681 {
682 if (!(ap->pflags & ATA_PFLAG_FROZEN))
683 pdc_reset_port(ap);
684
685 /* perform recovery */
686 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
687 ata_std_postreset);
688 }
689
690 static void pdc_pata_error_handler(struct ata_port *ap)
691 {
692 pdc_common_error_handler(ap, NULL);
693 }
694
695 static void pdc_sata_error_handler(struct ata_port *ap)
696 {
697 pdc_common_error_handler(ap, sata_std_hardreset);
698 }
699
700 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
701 {
702 struct ata_port *ap = qc->ap;
703
704 /* make DMA engine forget about the failed command */
705 if (qc->flags & ATA_QCFLAG_FAILED)
706 pdc_reset_port(ap);
707 }
708
709 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
710 u32 port_status, u32 err_mask)
711 {
712 struct ata_eh_info *ehi = &ap->eh_info;
713 unsigned int ac_err_mask = 0;
714
715 ata_ehi_clear_desc(ehi);
716 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
717 port_status &= err_mask;
718
719 if (port_status & PDC_DRIVE_ERR)
720 ac_err_mask |= AC_ERR_DEV;
721 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
722 ac_err_mask |= AC_ERR_HSM;
723 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
724 ac_err_mask |= AC_ERR_ATA_BUS;
725 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
726 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
727 ac_err_mask |= AC_ERR_HOST_BUS;
728
729 if (sata_scr_valid(ap))
730 ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR);
731
732 qc->err_mask |= ac_err_mask;
733
734 pdc_reset_port(ap);
735
736 ata_port_abort(ap);
737 }
738
739 static inline unsigned int pdc_host_intr( struct ata_port *ap,
740 struct ata_queued_cmd *qc)
741 {
742 unsigned int handled = 0;
743 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
744 u32 port_status, err_mask;
745
746 err_mask = PDC_ERR_MASK;
747 if (ap->flags & PDC_FLAG_GEN_II)
748 err_mask &= ~PDC1_ERR_MASK;
749 else
750 err_mask &= ~PDC2_ERR_MASK;
751 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
752 if (unlikely(port_status & err_mask)) {
753 pdc_error_intr(ap, qc, port_status, err_mask);
754 return 1;
755 }
756
757 switch (qc->tf.protocol) {
758 case ATA_PROT_DMA:
759 case ATA_PROT_NODATA:
760 case ATA_PROT_ATAPI_DMA:
761 case ATA_PROT_ATAPI_NODATA:
762 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
763 ata_qc_complete(qc);
764 handled = 1;
765 break;
766
767 default:
768 ap->stats.idle_irq++;
769 break;
770 }
771
772 return handled;
773 }
774
775 static void pdc_irq_clear(struct ata_port *ap)
776 {
777 struct ata_host *host = ap->host;
778 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
779
780 readl(mmio + PDC_INT_SEQMASK);
781 }
782
783 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
784 {
785 struct ata_host *host = dev_instance;
786 struct ata_port *ap;
787 u32 mask = 0;
788 unsigned int i, tmp;
789 unsigned int handled = 0;
790 void __iomem *mmio_base;
791
792 VPRINTK("ENTER\n");
793
794 if (!host || !host->iomap[PDC_MMIO_BAR]) {
795 VPRINTK("QUICK EXIT\n");
796 return IRQ_NONE;
797 }
798
799 mmio_base = host->iomap[PDC_MMIO_BAR];
800
801 /* reading should also clear interrupts */
802 mask = readl(mmio_base + PDC_INT_SEQMASK);
803
804 if (mask == 0xffffffff) {
805 VPRINTK("QUICK EXIT 2\n");
806 return IRQ_NONE;
807 }
808
809 spin_lock(&host->lock);
810
811 mask &= 0xffff; /* only 16 tags possible */
812 if (!mask) {
813 VPRINTK("QUICK EXIT 3\n");
814 goto done_irq;
815 }
816
817 writel(mask, mmio_base + PDC_INT_SEQMASK);
818
819 for (i = 0; i < host->n_ports; i++) {
820 VPRINTK("port %u\n", i);
821 ap = host->ports[i];
822 tmp = mask & (1 << (i + 1));
823 if (tmp && ap &&
824 !(ap->flags & ATA_FLAG_DISABLED)) {
825 struct ata_queued_cmd *qc;
826
827 qc = ata_qc_from_tag(ap, ap->active_tag);
828 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
829 handled += pdc_host_intr(ap, qc);
830 }
831 }
832
833 VPRINTK("EXIT\n");
834
835 done_irq:
836 spin_unlock(&host->lock);
837 return IRQ_RETVAL(handled);
838 }
839
840 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
841 {
842 struct ata_port *ap = qc->ap;
843 struct pdc_port_priv *pp = ap->private_data;
844 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
845 unsigned int port_no = ap->port_no;
846 u8 seq = (u8) (port_no + 1);
847
848 VPRINTK("ENTER, ap %p\n", ap);
849
850 writel(0x00000001, mmio + (seq * 4));
851 readl(mmio + (seq * 4)); /* flush */
852
853 pp->pkt[2] = seq;
854 wmb(); /* flush PRD, pkt writes */
855 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
856 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
857 }
858
859 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
860 {
861 switch (qc->tf.protocol) {
862 case ATA_PROT_ATAPI_NODATA:
863 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
864 break;
865 /*FALLTHROUGH*/
866 case ATA_PROT_NODATA:
867 if (qc->tf.flags & ATA_TFLAG_POLLING)
868 break;
869 /*FALLTHROUGH*/
870 case ATA_PROT_ATAPI_DMA:
871 case ATA_PROT_DMA:
872 pdc_packet_start(qc);
873 return 0;
874
875 default:
876 break;
877 }
878
879 return ata_qc_issue_prot(qc);
880 }
881
882 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
883 {
884 WARN_ON (tf->protocol == ATA_PROT_DMA ||
885 tf->protocol == ATA_PROT_ATAPI_DMA);
886 ata_tf_load(ap, tf);
887 }
888
889
890 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
891 {
892 WARN_ON (tf->protocol == ATA_PROT_DMA ||
893 tf->protocol == ATA_PROT_ATAPI_DMA);
894 ata_exec_command(ap, tf);
895 }
896
897 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
898 {
899 u8 *scsicmd = qc->scsicmd->cmnd;
900 int pio = 1; /* atapi dma off by default */
901
902 /* Whitelist commands that may use DMA. */
903 switch (scsicmd[0]) {
904 case WRITE_12:
905 case WRITE_10:
906 case WRITE_6:
907 case READ_12:
908 case READ_10:
909 case READ_6:
910 case 0xad: /* READ_DVD_STRUCTURE */
911 case 0xbe: /* READ_CD */
912 pio = 0;
913 }
914 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
915 if (scsicmd[0] == WRITE_10) {
916 unsigned int lba;
917 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
918 if (lba >= 0xFFFF4FA2)
919 pio = 1;
920 }
921 return pio;
922 }
923
924 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
925 {
926 /* First generation chips cannot use ATAPI DMA on SATA ports */
927 return 1;
928 }
929
930 static void pdc_ata_setup_port(struct ata_port *ap,
931 void __iomem *base, void __iomem *scr_addr)
932 {
933 ap->ioaddr.cmd_addr = base;
934 ap->ioaddr.data_addr = base;
935 ap->ioaddr.feature_addr =
936 ap->ioaddr.error_addr = base + 0x4;
937 ap->ioaddr.nsect_addr = base + 0x8;
938 ap->ioaddr.lbal_addr = base + 0xc;
939 ap->ioaddr.lbam_addr = base + 0x10;
940 ap->ioaddr.lbah_addr = base + 0x14;
941 ap->ioaddr.device_addr = base + 0x18;
942 ap->ioaddr.command_addr =
943 ap->ioaddr.status_addr = base + 0x1c;
944 ap->ioaddr.altstatus_addr =
945 ap->ioaddr.ctl_addr = base + 0x38;
946 ap->ioaddr.scr_addr = scr_addr;
947 }
948
949
950 static void pdc_host_init(struct ata_host *host)
951 {
952 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
953 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
954 int hotplug_offset;
955 u32 tmp;
956
957 if (is_gen2)
958 hotplug_offset = PDC2_SATA_PLUG_CSR;
959 else
960 hotplug_offset = PDC_SATA_PLUG_CSR;
961
962 /*
963 * Except for the hotplug stuff, this is voodoo from the
964 * Promise driver. Label this entire section
965 * "TODO: figure out why we do this"
966 */
967
968 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
969 tmp = readl(mmio + PDC_FLASH_CTL);
970 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
971 if (!is_gen2)
972 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
973 writel(tmp, mmio + PDC_FLASH_CTL);
974
975 /* clear plug/unplug flags for all ports */
976 tmp = readl(mmio + hotplug_offset);
977 writel(tmp | 0xff, mmio + hotplug_offset);
978
979 /* mask plug/unplug ints */
980 tmp = readl(mmio + hotplug_offset);
981 writel(tmp | 0xff0000, mmio + hotplug_offset);
982
983 /* don't initialise TBG or SLEW on 2nd generation chips */
984 if (is_gen2)
985 return;
986
987 /* reduce TBG clock to 133 Mhz. */
988 tmp = readl(mmio + PDC_TBG_MODE);
989 tmp &= ~0x30000; /* clear bit 17, 16*/
990 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
991 writel(tmp, mmio + PDC_TBG_MODE);
992
993 readl(mmio + PDC_TBG_MODE); /* flush */
994 msleep(10);
995
996 /* adjust slew rate control register. */
997 tmp = readl(mmio + PDC_SLEW_CTL);
998 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
999 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1000 writel(tmp, mmio + PDC_SLEW_CTL);
1001 }
1002
1003 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1004 {
1005 static int printed_version;
1006 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1007 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1008 struct ata_host *host;
1009 void __iomem *base;
1010 int n_ports, i, rc;
1011 int is_sataii_tx4;
1012
1013 if (!printed_version++)
1014 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1015
1016 /* enable and acquire resources */
1017 rc = pcim_enable_device(pdev);
1018 if (rc)
1019 return rc;
1020
1021 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1022 if (rc == -EBUSY)
1023 pcim_pin_device(pdev);
1024 if (rc)
1025 return rc;
1026 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1027
1028 /* determine port configuration and setup host */
1029 n_ports = 2;
1030 if (pi->flags & PDC_FLAG_4_PORTS)
1031 n_ports = 4;
1032 for (i = 0; i < n_ports; i++)
1033 ppi[i] = pi;
1034
1035 if (pi->flags & PDC_FLAG_SATA_PATA) {
1036 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1037 if (!(tmp & 0x80)) {
1038 ppi[n_ports++] = pi + 1;
1039 dev_printk(KERN_INFO, &pdev->dev, "PATA port found\n");
1040 }
1041 }
1042
1043 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1044 if (!host) {
1045 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1046 return -ENOMEM;
1047 }
1048 host->iomap = pcim_iomap_table(pdev);
1049
1050 is_sataii_tx4 = 0;
1051 if ((pi->flags & (PDC_FLAG_GEN_II|PDC_FLAG_4_PORTS)) == (PDC_FLAG_GEN_II|PDC_FLAG_4_PORTS)) {
1052 is_sataii_tx4 = 1;
1053 dev_printk(KERN_INFO, &pdev->dev, "applying SATAII TX4 port numbering workaround\n");
1054 }
1055 for (i = 0; i < host->n_ports; i++) {
1056 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
1057 int ata_nr;
1058
1059 ata_nr = i;
1060 if (is_sataii_tx4)
1061 ata_nr = sataii_tx4_port_remap[i];
1062
1063 pdc_ata_setup_port(host->ports[i],
1064 base + 0x200 + ata_nr * 0x80,
1065 base + 0x400 + ata_nr * 0x100);
1066 }
1067
1068 /* initialize adapter */
1069 pdc_host_init(host);
1070
1071 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1072 if (rc)
1073 return rc;
1074 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1075 if (rc)
1076 return rc;
1077
1078 /* start host, request IRQ and attach */
1079 pci_set_master(pdev);
1080 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1081 &pdc_ata_sht);
1082 }
1083
1084
1085 static int __init pdc_ata_init(void)
1086 {
1087 return pci_register_driver(&pdc_ata_pci_driver);
1088 }
1089
1090
1091 static void __exit pdc_ata_exit(void)
1092 {
1093 pci_unregister_driver(&pdc_ata_pci_driver);
1094 }
1095
1096
1097 MODULE_AUTHOR("Jeff Garzik");
1098 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1099 MODULE_LICENSE("GPL");
1100 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1101 MODULE_VERSION(DRV_VERSION);
1102
1103 module_init(pdc_ata_init);
1104 module_exit(pdc_ata_exit);
Tomato firmware and modifications.