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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / ata / ahci.c
blobe722f830cebc0a1f0c0ccae319fe12337fe9f920
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.2"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
83 board_ahci_sb600 = 4,
84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
144 PORT_IRQ_PHYRDY |
145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
152
153 /* PORT_CMD bits */
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
167
168 /* ap->flags bits */
169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
174
175 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
176 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
177 ATA_FLAG_SKIP_D2H_BSY |
178 ATA_FLAG_ACPI_SATA,
179 };
180
181 struct ahci_cmd_hdr {
182 u32 opts;
183 u32 status;
184 u32 tbl_addr;
185 u32 tbl_addr_hi;
186 u32 reserved[4];
187 };
188
189 struct ahci_sg {
190 u32 addr;
191 u32 addr_hi;
192 u32 reserved;
193 u32 flags_size;
194 };
195
196 struct ahci_host_priv {
197 u32 cap; /* cap to use */
198 u32 port_map; /* port map to use */
199 u32 saved_cap; /* saved initial cap */
200 u32 saved_port_map; /* saved initial port_map */
201 };
202
203 struct ahci_port_priv {
204 struct ahci_cmd_hdr *cmd_slot;
205 dma_addr_t cmd_slot_dma;
206 void *cmd_tbl;
207 dma_addr_t cmd_tbl_dma;
208 void *rx_fis;
209 dma_addr_t rx_fis_dma;
210 /* for NCQ spurious interrupt analysis */
211 unsigned int ncq_saw_d2h:1;
212 unsigned int ncq_saw_dmas:1;
213 unsigned int ncq_saw_sdb:1;
214 };
215
216 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
217 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
218 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
219 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
220 static void ahci_irq_clear(struct ata_port *ap);
221 static int ahci_port_start(struct ata_port *ap);
222 static void ahci_port_stop(struct ata_port *ap);
223 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
224 static void ahci_qc_prep(struct ata_queued_cmd *qc);
225 static u8 ahci_check_status(struct ata_port *ap);
226 static void ahci_freeze(struct ata_port *ap);
227 static void ahci_thaw(struct ata_port *ap);
228 static void ahci_error_handler(struct ata_port *ap);
229 static void ahci_vt8251_error_handler(struct ata_port *ap);
230 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
231 #ifdef CONFIG_PM
232 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
233 static int ahci_port_resume(struct ata_port *ap);
234 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
235 static int ahci_pci_device_resume(struct pci_dev *pdev);
236 #endif
237
238 static struct scsi_host_template ahci_sht = {
239 .module = THIS_MODULE,
240 .name = DRV_NAME,
241 .ioctl = ata_scsi_ioctl,
242 .queuecommand = ata_scsi_queuecmd,
243 .change_queue_depth = ata_scsi_change_queue_depth,
244 .can_queue = AHCI_MAX_CMDS - 1,
245 .this_id = ATA_SHT_THIS_ID,
246 .sg_tablesize = AHCI_MAX_SG,
247 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
248 .emulated = ATA_SHT_EMULATED,
249 .use_clustering = AHCI_USE_CLUSTERING,
250 .proc_name = DRV_NAME,
251 .dma_boundary = AHCI_DMA_BOUNDARY,
252 .slave_configure = ata_scsi_slave_config,
253 .slave_destroy = ata_scsi_slave_destroy,
254 .bios_param = ata_std_bios_param,
255 };
256
257 static const struct ata_port_operations ahci_ops = {
258 .port_disable = ata_port_disable,
259
260 .check_status = ahci_check_status,
261 .check_altstatus = ahci_check_status,
262 .dev_select = ata_noop_dev_select,
263
264 .tf_read = ahci_tf_read,
265
266 .qc_prep = ahci_qc_prep,
267 .qc_issue = ahci_qc_issue,
268
269 .irq_clear = ahci_irq_clear,
270 .irq_on = ata_dummy_irq_on,
271 .irq_ack = ata_dummy_irq_ack,
272
273 .scr_read = ahci_scr_read,
274 .scr_write = ahci_scr_write,
275
276 .freeze = ahci_freeze,
277 .thaw = ahci_thaw,
278
279 .error_handler = ahci_error_handler,
280 .post_internal_cmd = ahci_post_internal_cmd,
281
282 #ifdef CONFIG_PM
283 .port_suspend = ahci_port_suspend,
284 .port_resume = ahci_port_resume,
285 #endif
286
287 .port_start = ahci_port_start,
288 .port_stop = ahci_port_stop,
289 };
290
291 static const struct ata_port_operations ahci_vt8251_ops = {
292 .port_disable = ata_port_disable,
293
294 .check_status = ahci_check_status,
295 .check_altstatus = ahci_check_status,
296 .dev_select = ata_noop_dev_select,
297
298 .tf_read = ahci_tf_read,
299
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .irq_clear = ahci_irq_clear,
304 .irq_on = ata_dummy_irq_on,
305 .irq_ack = ata_dummy_irq_ack,
306
307 .scr_read = ahci_scr_read,
308 .scr_write = ahci_scr_write,
309
310 .freeze = ahci_freeze,
311 .thaw = ahci_thaw,
312
313 .error_handler = ahci_vt8251_error_handler,
314 .post_internal_cmd = ahci_post_internal_cmd,
315
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320
321 .port_start = ahci_port_start,
322 .port_stop = ahci_port_stop,
323 };
324
325 static const struct ata_port_info ahci_port_info[] = {
326 /* board_ahci */
327 {
328 .flags = AHCI_FLAG_COMMON,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
332 },
333 /* board_ahci_pi */
334 {
335 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
336 .pio_mask = 0x1f, /* pio0-4 */
337 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
338 .port_ops = &ahci_ops,
339 },
340 /* board_ahci_vt8251 */
341 {
342 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
343 AHCI_FLAG_NO_NCQ,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
346 .port_ops = &ahci_vt8251_ops,
347 },
348 /* board_ahci_ign_iferr */
349 {
350 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
353 .port_ops = &ahci_ops,
354 },
355 /* board_ahci_sb600 */
356 {
357 .flags = AHCI_FLAG_COMMON |
358 AHCI_FLAG_IGN_SERR_INTERNAL |
359 AHCI_FLAG_32BIT_ONLY,
360 .pio_mask = 0x1f, /* pio0-4 */
361 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
362 .port_ops = &ahci_ops,
363 },
364 };
365
366 static const struct pci_device_id ahci_pci_tbl[] = {
367 /* Intel */
368 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
369 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
370 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
371 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
372 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
373 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
374 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
375 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
376 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
377 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
378 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
379 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
380 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
381 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
382 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
383 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
384 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
385 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
386 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
387 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
388 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
389 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
390 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
391 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
392 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
393 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
395
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
399
400 /* ATI */
401 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
402 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 IDE */
403 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700 AHCI */
404 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700 nraid5 */
405 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700 raid5 */
406
407 /* VIA */
408 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
409 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
410
411 /* NVIDIA */
412 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
418 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
433 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
434 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
435 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
436 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
437 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
438 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
439 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
440 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
441 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
442 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
443 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
444 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
445 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
446 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
447 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
448 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
449 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
450 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
451 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
452 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
453 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
454 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
455 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
456
457 /* SiS */
458 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
459 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
460 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
461
462 /* Generic, PCI class code for AHCI */
463 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
465
466 { } /* terminate list */
467 };
468
469
470 static struct pci_driver ahci_pci_driver = {
471 .name = DRV_NAME,
472 .id_table = ahci_pci_tbl,
473 .probe = ahci_init_one,
474 .remove = ata_pci_remove_one,
475 #ifdef CONFIG_PM
476 .suspend = ahci_pci_device_suspend,
477 .resume = ahci_pci_device_resume,
478 #endif
479 };
480
481
482 static inline int ahci_nr_ports(u32 cap)
483 {
484 return (cap & 0x1f) + 1;
485 }
486
487 static inline void __iomem *ahci_port_base(struct ata_port *ap)
488 {
489 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
490
491 return mmio + 0x100 + (ap->port_no * 0x80);
492 }
493
494 /**
495 * ahci_save_initial_config - Save and fixup initial config values
496 * @pdev: target PCI device
497 * @pi: associated ATA port info
498 * @hpriv: host private area to store config values
499 *
500 * Some registers containing configuration info might be setup by
501 * BIOS and might be cleared on reset. This function saves the
502 * initial values of those registers into @hpriv such that they
503 * can be restored after controller reset.
504 *
505 * If inconsistent, config values are fixed up by this function.
506 *
507 * LOCKING:
508 * None.
509 */
510 static void ahci_save_initial_config(struct pci_dev *pdev,
511 const struct ata_port_info *pi,
512 struct ahci_host_priv *hpriv)
513 {
514 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
515 u32 cap, port_map;
516 int i;
517
518 /* Values prefixed with saved_ are written back to host after
519 * reset. Values without are used for driver operation.
520 */
521 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
522 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
523
524 /* some chips lie about 64bit support */
525 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
526 dev_printk(KERN_INFO, &pdev->dev,
527 "controller can't do 64bit DMA, forcing 32bit\n");
528 cap &= ~HOST_CAP_64;
529 }
530
531 /* fixup zero port_map */
532 if (!port_map) {
533 port_map = (1 << ahci_nr_ports(cap)) - 1;
534 dev_printk(KERN_WARNING, &pdev->dev,
535 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
536
537 /* write the fixed up value to the PI register */
538 hpriv->saved_port_map = port_map;
539 }
540
541 /* cross check port_map and cap.n_ports */
542 if (pi->flags & AHCI_FLAG_HONOR_PI) {
543 u32 tmp_port_map = port_map;
544 int n_ports = ahci_nr_ports(cap);
545
546 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
547 if (tmp_port_map & (1 << i)) {
548 n_ports--;
549 tmp_port_map &= ~(1 << i);
550 }
551 }
552
553 /* Whine if inconsistent. No need to update cap.
554 * port_map is used to determine number of ports.
555 */
556 if (n_ports || tmp_port_map)
557 dev_printk(KERN_WARNING, &pdev->dev,
558 "nr_ports (%u) and implemented port map "
559 "(0x%x) don't match\n",
560 ahci_nr_ports(cap), port_map);
561 } else {
562 /* fabricate port_map from cap.nr_ports */
563 port_map = (1 << ahci_nr_ports(cap)) - 1;
564 }
565
566 /* record values to use during operation */
567 hpriv->cap = cap;
568 hpriv->port_map = port_map;
569 }
570
571 /**
572 * ahci_restore_initial_config - Restore initial config
573 * @host: target ATA host
574 *
575 * Restore initial config stored by ahci_save_initial_config().
576 *
577 * LOCKING:
578 * None.
579 */
580 static void ahci_restore_initial_config(struct ata_host *host)
581 {
582 struct ahci_host_priv *hpriv = host->private_data;
583 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
584
585 writel(hpriv->saved_cap, mmio + HOST_CAP);
586 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
587 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
588 }
589
590 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
591 {
592 unsigned int sc_reg;
593
594 switch (sc_reg_in) {
595 case SCR_STATUS: sc_reg = 0; break;
596 case SCR_CONTROL: sc_reg = 1; break;
597 case SCR_ERROR: sc_reg = 2; break;
598 case SCR_ACTIVE: sc_reg = 3; break;
599 default:
600 return 0xffffffffU;
601 }
602
603 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
604 }
605
606
607 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
608 u32 val)
609 {
610 unsigned int sc_reg;
611
612 switch (sc_reg_in) {
613 case SCR_STATUS: sc_reg = 0; break;
614 case SCR_CONTROL: sc_reg = 1; break;
615 case SCR_ERROR: sc_reg = 2; break;
616 case SCR_ACTIVE: sc_reg = 3; break;
617 default:
618 return;
619 }
620
621 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
622 }
623
624 static void ahci_start_engine(struct ata_port *ap)
625 {
626 void __iomem *port_mmio = ahci_port_base(ap);
627 u32 tmp;
628
629 /* start DMA */
630 tmp = readl(port_mmio + PORT_CMD);
631 tmp |= PORT_CMD_START;
632 writel(tmp, port_mmio + PORT_CMD);
633 readl(port_mmio + PORT_CMD); /* flush */
634 }
635
636 static int ahci_stop_engine(struct ata_port *ap)
637 {
638 void __iomem *port_mmio = ahci_port_base(ap);
639 u32 tmp;
640
641 tmp = readl(port_mmio + PORT_CMD);
642
643 /* check if the HBA is idle */
644 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
645 return 0;
646
647 /* setting HBA to idle */
648 tmp &= ~PORT_CMD_START;
649 writel(tmp, port_mmio + PORT_CMD);
650
651 /* wait for engine to stop. This could be as long as 500 msec */
652 tmp = ata_wait_register(port_mmio + PORT_CMD,
653 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
654 if (tmp & PORT_CMD_LIST_ON)
655 return -EIO;
656
657 return 0;
658 }
659
660 static void ahci_start_fis_rx(struct ata_port *ap)
661 {
662 void __iomem *port_mmio = ahci_port_base(ap);
663 struct ahci_host_priv *hpriv = ap->host->private_data;
664 struct ahci_port_priv *pp = ap->private_data;
665 u32 tmp;
666
667 /* set FIS registers */
668 if (hpriv->cap & HOST_CAP_64)
669 writel((pp->cmd_slot_dma >> 16) >> 16,
670 port_mmio + PORT_LST_ADDR_HI);
671 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
672
673 if (hpriv->cap & HOST_CAP_64)
674 writel((pp->rx_fis_dma >> 16) >> 16,
675 port_mmio + PORT_FIS_ADDR_HI);
676 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
677
678 /* enable FIS reception */
679 tmp = readl(port_mmio + PORT_CMD);
680 tmp |= PORT_CMD_FIS_RX;
681 writel(tmp, port_mmio + PORT_CMD);
682
683 /* flush */
684 readl(port_mmio + PORT_CMD);
685 }
686
687 static int ahci_stop_fis_rx(struct ata_port *ap)
688 {
689 void __iomem *port_mmio = ahci_port_base(ap);
690 u32 tmp;
691
692 /* disable FIS reception */
693 tmp = readl(port_mmio + PORT_CMD);
694 tmp &= ~PORT_CMD_FIS_RX;
695 writel(tmp, port_mmio + PORT_CMD);
696
697 /* wait for completion, spec says 500ms, give it 1000 */
698 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
699 PORT_CMD_FIS_ON, 10, 1000);
700 if (tmp & PORT_CMD_FIS_ON)
701 return -EBUSY;
702
703 return 0;
704 }
705
706 static void ahci_power_up(struct ata_port *ap)
707 {
708 struct ahci_host_priv *hpriv = ap->host->private_data;
709 void __iomem *port_mmio = ahci_port_base(ap);
710 u32 cmd;
711
712 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
713
714 /* spin up device */
715 if (hpriv->cap & HOST_CAP_SSS) {
716 cmd |= PORT_CMD_SPIN_UP;
717 writel(cmd, port_mmio + PORT_CMD);
718 }
719
720 /* wake up link */
721 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
722 }
723
724 #ifdef CONFIG_PM
725 static void ahci_power_down(struct ata_port *ap)
726 {
727 struct ahci_host_priv *hpriv = ap->host->private_data;
728 void __iomem *port_mmio = ahci_port_base(ap);
729 u32 cmd, scontrol;
730
731 if (!(hpriv->cap & HOST_CAP_SSS))
732 return;
733
734 /* put device into listen mode, first set PxSCTL.DET to 0 */
735 scontrol = readl(port_mmio + PORT_SCR_CTL);
736 scontrol &= ~0xf;
737 writel(scontrol, port_mmio + PORT_SCR_CTL);
738
739 /* then set PxCMD.SUD to 0 */
740 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
741 cmd &= ~PORT_CMD_SPIN_UP;
742 writel(cmd, port_mmio + PORT_CMD);
743 }
744 #endif
745
746 static void ahci_init_port(struct ata_port *ap)
747 {
748 /* enable FIS reception */
749 ahci_start_fis_rx(ap);
750
751 /* enable DMA */
752 ahci_start_engine(ap);
753 }
754
755 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
756 {
757 int rc;
758
759 /* disable DMA */
760 rc = ahci_stop_engine(ap);
761 if (rc) {
762 *emsg = "failed to stop engine";
763 return rc;
764 }
765
766 /* disable FIS reception */
767 rc = ahci_stop_fis_rx(ap);
768 if (rc) {
769 *emsg = "failed stop FIS RX";
770 return rc;
771 }
772
773 return 0;
774 }
775
776 static int ahci_reset_controller(struct ata_host *host)
777 {
778 struct pci_dev *pdev = to_pci_dev(host->dev);
779 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
780 u32 tmp;
781
782 /* global controller reset */
783 tmp = readl(mmio + HOST_CTL);
784 if ((tmp & HOST_RESET) == 0) {
785 writel(tmp | HOST_RESET, mmio + HOST_CTL);
786 readl(mmio + HOST_CTL); /* flush */
787 }
788
789 /* reset must complete within 1 second, or
790 * the hardware should be considered fried.
791 */
792 ssleep(1);
793
794 tmp = readl(mmio + HOST_CTL);
795 if (tmp & HOST_RESET) {
796 dev_printk(KERN_ERR, host->dev,
797 "controller reset failed (0x%x)\n", tmp);
798 return -EIO;
799 }
800
801 /* turn on AHCI mode */
802 writel(HOST_AHCI_EN, mmio + HOST_CTL);
803 (void) readl(mmio + HOST_CTL); /* flush */
804
805 /* some registers might be cleared on reset. restore initial values */
806 ahci_restore_initial_config(host);
807
808 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
809 u16 tmp16;
810
811 /* configure PCS */
812 pci_read_config_word(pdev, 0x92, &tmp16);
813 tmp16 |= 0xf;
814 pci_write_config_word(pdev, 0x92, tmp16);
815 }
816
817 return 0;
818 }
819
820 static void ahci_init_controller(struct ata_host *host)
821 {
822 struct pci_dev *pdev = to_pci_dev(host->dev);
823 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
824 int i, rc;
825 u32 tmp;
826
827 for (i = 0; i < host->n_ports; i++) {
828 struct ata_port *ap = host->ports[i];
829 void __iomem *port_mmio = ahci_port_base(ap);
830 const char *emsg = NULL;
831
832 if (ata_port_is_dummy(ap))
833 continue;
834
835 /* make sure port is not active */
836 rc = ahci_deinit_port(ap, &emsg);
837 if (rc)
838 dev_printk(KERN_WARNING, &pdev->dev,
839 "%s (%d)\n", emsg, rc);
840
841 /* clear SError */
842 tmp = readl(port_mmio + PORT_SCR_ERR);
843 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
844 writel(tmp, port_mmio + PORT_SCR_ERR);
845
846 /* clear port IRQ */
847 tmp = readl(port_mmio + PORT_IRQ_STAT);
848 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
849 if (tmp)
850 writel(tmp, port_mmio + PORT_IRQ_STAT);
851
852 writel(1 << i, mmio + HOST_IRQ_STAT);
853 }
854
855 tmp = readl(mmio + HOST_CTL);
856 VPRINTK("HOST_CTL 0x%x\n", tmp);
857 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
858 tmp = readl(mmio + HOST_CTL);
859 VPRINTK("HOST_CTL 0x%x\n", tmp);
860 }
861
862 static unsigned int ahci_dev_classify(struct ata_port *ap)
863 {
864 void __iomem *port_mmio = ahci_port_base(ap);
865 struct ata_taskfile tf;
866 u32 tmp;
867
868 tmp = readl(port_mmio + PORT_SIG);
869 tf.lbah = (tmp >> 24) & 0xff;
870 tf.lbam = (tmp >> 16) & 0xff;
871 tf.lbal = (tmp >> 8) & 0xff;
872 tf.nsect = (tmp) & 0xff;
873
874 return ata_dev_classify(&tf);
875 }
876
877 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
878 u32 opts)
879 {
880 dma_addr_t cmd_tbl_dma;
881
882 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
883
884 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
885 pp->cmd_slot[tag].status = 0;
886 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
887 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
888 }
889
890 static int ahci_clo(struct ata_port *ap)
891 {
892 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
893 struct ahci_host_priv *hpriv = ap->host->private_data;
894 u32 tmp;
895
896 if (!(hpriv->cap & HOST_CAP_CLO))
897 return -EOPNOTSUPP;
898
899 tmp = readl(port_mmio + PORT_CMD);
900 tmp |= PORT_CMD_CLO;
901 writel(tmp, port_mmio + PORT_CMD);
902
903 tmp = ata_wait_register(port_mmio + PORT_CMD,
904 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
905 if (tmp & PORT_CMD_CLO)
906 return -EIO;
907
908 return 0;
909 }
910
911 static int ahci_softreset(struct ata_port *ap, unsigned int *class,
912 unsigned long deadline)
913 {
914 struct ahci_port_priv *pp = ap->private_data;
915 void __iomem *port_mmio = ahci_port_base(ap);
916 const u32 cmd_fis_len = 5; /* five dwords */
917 const char *reason = NULL;
918 struct ata_taskfile tf;
919 u32 tmp;
920 u8 *fis;
921 int rc;
922
923 DPRINTK("ENTER\n");
924
925 if (ata_port_offline(ap)) {
926 DPRINTK("PHY reports no device\n");
927 *class = ATA_DEV_NONE;
928 return 0;
929 }
930
931 /* prepare for SRST (AHCI-1.1 10.4.1) */
932 rc = ahci_stop_engine(ap);
933 if (rc) {
934 reason = "failed to stop engine";
935 goto fail_restart;
936 }
937
938 /* check BUSY/DRQ, perform Command List Override if necessary */
939 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
940 rc = ahci_clo(ap);
941
942 if (rc == -EOPNOTSUPP) {
943 reason = "port busy but CLO unavailable";
944 goto fail_restart;
945 } else if (rc) {
946 reason = "port busy but CLO failed";
947 goto fail_restart;
948 }
949 }
950
951 /* restart engine */
952 ahci_start_engine(ap);
953
954 ata_tf_init(ap->device, &tf);
955 fis = pp->cmd_tbl;
956
957 /* issue the first D2H Register FIS */
958 ahci_fill_cmd_slot(pp, 0,
959 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
960
961 tf.ctl |= ATA_SRST;
962 ata_tf_to_fis(&tf, fis, 0);
963 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
964
965 writel(1, port_mmio + PORT_CMD_ISSUE);
966
967 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
968 if (tmp & 0x1) {
969 rc = -EIO;
970 reason = "1st FIS failed";
971 goto fail;
972 }
973
974 /* spec says at least 5us, but be generous and sleep for 1ms */
975 msleep(1);
976
977 /* issue the second D2H Register FIS */
978 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
979
980 tf.ctl &= ~ATA_SRST;
981 ata_tf_to_fis(&tf, fis, 0);
982 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
983
984 writel(1, port_mmio + PORT_CMD_ISSUE);
985 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
986
987 /* spec mandates ">= 2ms" before checking status.
988 * We wait 150ms, because that was the magic delay used for
989 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
990 * between when the ATA command register is written, and then
991 * status is checked. Because waiting for "a while" before
992 * checking status is fine, post SRST, we perform this magic
993 * delay here as well.
994 */
995 msleep(150);
996
997 rc = ata_wait_ready(ap, deadline);
998 /* link occupied, -ENODEV too is an error */
999 if (rc) {
1000 reason = "device not ready";
1001 goto fail;
1002 }
1003 *class = ahci_dev_classify(ap);
1004
1005 DPRINTK("EXIT, class=%u\n", *class);
1006 return 0;
1007
1008 fail_restart:
1009 ahci_start_engine(ap);
1010 fail:
1011 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
1012 return rc;
1013 }
1014
1015 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1016 unsigned long deadline)
1017 {
1018 struct ahci_port_priv *pp = ap->private_data;
1019 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1020 struct ata_taskfile tf;
1021 int rc;
1022
1023 DPRINTK("ENTER\n");
1024
1025 ahci_stop_engine(ap);
1026
1027 /* clear D2H reception area to properly wait for D2H FIS */
1028 ata_tf_init(ap->device, &tf);
1029 tf.command = 0x80;
1030 ata_tf_to_fis(&tf, d2h_fis, 0);
1031
1032 rc = sata_std_hardreset(ap, class, deadline);
1033
1034 ahci_start_engine(ap);
1035
1036 if (rc == 0 && ata_port_online(ap))
1037 *class = ahci_dev_classify(ap);
1038 if (*class == ATA_DEV_UNKNOWN)
1039 *class = ATA_DEV_NONE;
1040
1041 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1042 return rc;
1043 }
1044
1045 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1046 unsigned long deadline)
1047 {
1048 int rc;
1049
1050 DPRINTK("ENTER\n");
1051
1052 ahci_stop_engine(ap);
1053
1054 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1055 deadline);
1056
1057 /* vt8251 needs SError cleared for the port to operate */
1058 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1059
1060 ahci_start_engine(ap);
1061
1062 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1063
1064 /* vt8251 doesn't clear BSY on signature FIS reception,
1065 * request follow-up softreset.
1066 */
1067 return rc ?: -EAGAIN;
1068 }
1069
1070 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1071 {
1072 void __iomem *port_mmio = ahci_port_base(ap);
1073 u32 new_tmp, tmp;
1074
1075 ata_std_postreset(ap, class);
1076
1077 /* Make sure port's ATAPI bit is set appropriately */
1078 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1079 if (*class == ATA_DEV_ATAPI)
1080 new_tmp |= PORT_CMD_ATAPI;
1081 else
1082 new_tmp &= ~PORT_CMD_ATAPI;
1083 if (new_tmp != tmp) {
1084 writel(new_tmp, port_mmio + PORT_CMD);
1085 readl(port_mmio + PORT_CMD); /* flush */
1086 }
1087 }
1088
1089 static u8 ahci_check_status(struct ata_port *ap)
1090 {
1091 void __iomem *mmio = ap->ioaddr.cmd_addr;
1092
1093 return readl(mmio + PORT_TFDATA) & 0xFF;
1094 }
1095
1096 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1097 {
1098 struct ahci_port_priv *pp = ap->private_data;
1099 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1100
1101 ata_tf_from_fis(d2h_fis, tf);
1102 }
1103
1104 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1105 {
1106 struct scatterlist *sg;
1107 struct ahci_sg *ahci_sg;
1108 unsigned int n_sg = 0;
1109
1110 VPRINTK("ENTER\n");
1111
1112 /*
1113 * Next, the S/G list.
1114 */
1115 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1116 ata_for_each_sg(sg, qc) {
1117 dma_addr_t addr = sg_dma_address(sg);
1118 u32 sg_len = sg_dma_len(sg);
1119
1120 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1121 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1122 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1123
1124 ahci_sg++;
1125 n_sg++;
1126 }
1127
1128 return n_sg;
1129 }
1130
1131 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1132 {
1133 struct ata_port *ap = qc->ap;
1134 struct ahci_port_priv *pp = ap->private_data;
1135 int is_atapi = is_atapi_taskfile(&qc->tf);
1136 void *cmd_tbl;
1137 u32 opts;
1138 const u32 cmd_fis_len = 5; /* five dwords */
1139 unsigned int n_elem;
1140
1141 /*
1142 * Fill in command table information. First, the header,
1143 * a SATA Register - Host to Device command FIS.
1144 */
1145 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1146
1147 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1148 if (is_atapi) {
1149 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1150 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1151 }
1152
1153 n_elem = 0;
1154 if (qc->flags & ATA_QCFLAG_DMAMAP)
1155 n_elem = ahci_fill_sg(qc, cmd_tbl);
1156
1157 /*
1158 * Fill in command slot information.
1159 */
1160 opts = cmd_fis_len | n_elem << 16;
1161 if (qc->tf.flags & ATA_TFLAG_WRITE)
1162 opts |= AHCI_CMD_WRITE;
1163 if (is_atapi)
1164 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1165
1166 ahci_fill_cmd_slot(pp, qc->tag, opts);
1167 }
1168
1169 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1170 {
1171 struct ahci_port_priv *pp = ap->private_data;
1172 struct ata_eh_info *ehi = &ap->eh_info;
1173 unsigned int err_mask = 0, action = 0;
1174 struct ata_queued_cmd *qc;
1175 u32 serror;
1176
1177 ata_ehi_clear_desc(ehi);
1178
1179 /* AHCI needs SError cleared; otherwise, it might lock up */
1180 serror = ahci_scr_read(ap, SCR_ERROR);
1181 ahci_scr_write(ap, SCR_ERROR, serror);
1182
1183 /* analyze @irq_stat */
1184 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1185
1186 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1187 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1188 irq_stat &= ~PORT_IRQ_IF_ERR;
1189
1190 if (irq_stat & PORT_IRQ_TF_ERR) {
1191 err_mask |= AC_ERR_DEV;
1192 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1193 serror &= ~SERR_INTERNAL;
1194 }
1195
1196 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1197 err_mask |= AC_ERR_HOST_BUS;
1198 action |= ATA_EH_SOFTRESET;
1199 }
1200
1201 if (irq_stat & PORT_IRQ_IF_ERR) {
1202 err_mask |= AC_ERR_ATA_BUS;
1203 action |= ATA_EH_SOFTRESET;
1204 ata_ehi_push_desc(ehi, ", interface fatal error");
1205 }
1206
1207 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1208 ata_ehi_hotplugged(ehi);
1209 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1210 "connection status changed" : "PHY RDY changed");
1211 }
1212
1213 if (irq_stat & PORT_IRQ_UNK_FIS) {
1214 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1215
1216 err_mask |= AC_ERR_HSM;
1217 action |= ATA_EH_SOFTRESET;
1218 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1219 unk[0], unk[1], unk[2], unk[3]);
1220 }
1221
1222 /* okay, let's hand over to EH */
1223 ehi->serror |= serror;
1224 ehi->action |= action;
1225
1226 qc = ata_qc_from_tag(ap, ap->active_tag);
1227 if (qc)
1228 qc->err_mask |= err_mask;
1229 else
1230 ehi->err_mask |= err_mask;
1231
1232 if (irq_stat & PORT_IRQ_FREEZE)
1233 ata_port_freeze(ap);
1234 else
1235 ata_port_abort(ap);
1236 }
1237
1238 static void ahci_host_intr(struct ata_port *ap)
1239 {
1240 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1241 struct ata_eh_info *ehi = &ap->eh_info;
1242 struct ahci_port_priv *pp = ap->private_data;
1243 u32 status, qc_active;
1244 int rc;
1245
1246 status = readl(port_mmio + PORT_IRQ_STAT);
1247 writel(status, port_mmio + PORT_IRQ_STAT);
1248
1249 if (unlikely(status & PORT_IRQ_ERROR)) {
1250 ahci_error_intr(ap, status);
1251 return;
1252 }
1253
1254 if (ap->sactive)
1255 qc_active = readl(port_mmio + PORT_SCR_ACT);
1256 else
1257 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1258
1259 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1260 if (rc < 0) {
1261 ehi->err_mask |= AC_ERR_HSM;
1262 ehi->action |= ATA_EH_SOFTRESET;
1263 ata_port_freeze(ap);
1264 }
1265 }
1266
1267 static void ahci_irq_clear(struct ata_port *ap)
1268 {
1269 /* TODO */
1270 }
1271
1272 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1273 {
1274 struct ata_host *host = dev_instance;
1275 struct ahci_host_priv *hpriv;
1276 unsigned int i, handled = 0;
1277 void __iomem *mmio;
1278 u32 irq_stat, irq_ack = 0;
1279
1280 VPRINTK("ENTER\n");
1281
1282 hpriv = host->private_data;
1283 mmio = host->iomap[AHCI_PCI_BAR];
1284
1285 /* sigh. 0xffffffff is a valid return from h/w */
1286 irq_stat = readl(mmio + HOST_IRQ_STAT);
1287 irq_stat &= hpriv->port_map;
1288 if (!irq_stat)
1289 return IRQ_NONE;
1290
1291 spin_lock(&host->lock);
1292
1293 for (i = 0; i < host->n_ports; i++) {
1294 struct ata_port *ap;
1295
1296 if (!(irq_stat & (1 << i)))
1297 continue;
1298
1299 ap = host->ports[i];
1300 if (ap) {
1301 ahci_host_intr(ap);
1302 VPRINTK("port %u\n", i);
1303 } else {
1304 VPRINTK("port %u (no irq)\n", i);
1305 if (ata_ratelimit())
1306 dev_printk(KERN_WARNING, host->dev,
1307 "interrupt on disabled port %u\n", i);
1308 }
1309
1310 irq_ack |= (1 << i);
1311 }
1312
1313 if (irq_ack) {
1314 writel(irq_ack, mmio + HOST_IRQ_STAT);
1315 handled = 1;
1316 }
1317
1318 spin_unlock(&host->lock);
1319
1320 VPRINTK("EXIT\n");
1321
1322 return IRQ_RETVAL(handled);
1323 }
1324
1325 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1326 {
1327 struct ata_port *ap = qc->ap;
1328 void __iomem *port_mmio = ahci_port_base(ap);
1329
1330 if (qc->tf.protocol == ATA_PROT_NCQ)
1331 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1332 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1333 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1334
1335 return 0;
1336 }
1337
1338 static void ahci_freeze(struct ata_port *ap)
1339 {
1340 void __iomem *port_mmio = ahci_port_base(ap);
1341
1342 /* turn IRQ off */
1343 writel(0, port_mmio + PORT_IRQ_MASK);
1344 }
1345
1346 static void ahci_thaw(struct ata_port *ap)
1347 {
1348 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1349 void __iomem *port_mmio = ahci_port_base(ap);
1350 u32 tmp;
1351
1352 /* clear IRQ */
1353 tmp = readl(port_mmio + PORT_IRQ_STAT);
1354 writel(tmp, port_mmio + PORT_IRQ_STAT);
1355 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1356
1357 /* turn IRQ back on */
1358 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1359 }
1360
1361 static void ahci_error_handler(struct ata_port *ap)
1362 {
1363 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1364 /* restart engine */
1365 ahci_stop_engine(ap);
1366 ahci_start_engine(ap);
1367 }
1368
1369 /* perform recovery */
1370 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1371 ahci_postreset);
1372 }
1373
1374 static void ahci_vt8251_error_handler(struct ata_port *ap)
1375 {
1376 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1377 /* restart engine */
1378 ahci_stop_engine(ap);
1379 ahci_start_engine(ap);
1380 }
1381
1382 /* perform recovery */
1383 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1384 ahci_postreset);
1385 }
1386
1387 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1388 {
1389 struct ata_port *ap = qc->ap;
1390
1391 if (qc->flags & ATA_QCFLAG_FAILED) {
1392 /* make DMA engine forget about the failed command */
1393 ahci_stop_engine(ap);
1394 ahci_start_engine(ap);
1395 }
1396 }
1397
1398 #ifdef CONFIG_PM
1399 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1400 {
1401 const char *emsg = NULL;
1402 int rc;
1403
1404 rc = ahci_deinit_port(ap, &emsg);
1405 if (rc == 0)
1406 ahci_power_down(ap);
1407 else {
1408 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1409 ahci_init_port(ap);
1410 }
1411
1412 return rc;
1413 }
1414
1415 static int ahci_port_resume(struct ata_port *ap)
1416 {
1417 ahci_power_up(ap);
1418 ahci_init_port(ap);
1419
1420 return 0;
1421 }
1422
1423 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1424 {
1425 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1426 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1427 u32 ctl;
1428
1429 if (mesg.event == PM_EVENT_SUSPEND) {
1430 /* AHCI spec rev1.1 section 8.3.3:
1431 * Software must disable interrupts prior to requesting a
1432 * transition of the HBA to D3 state.
1433 */
1434 ctl = readl(mmio + HOST_CTL);
1435 ctl &= ~HOST_IRQ_EN;
1436 writel(ctl, mmio + HOST_CTL);
1437 readl(mmio + HOST_CTL); /* flush */
1438 }
1439
1440 return ata_pci_device_suspend(pdev, mesg);
1441 }
1442
1443 static int ahci_pci_device_resume(struct pci_dev *pdev)
1444 {
1445 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1446 int rc;
1447
1448 rc = ata_pci_device_do_resume(pdev);
1449 if (rc)
1450 return rc;
1451
1452 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1453 rc = ahci_reset_controller(host);
1454 if (rc)
1455 return rc;
1456
1457 ahci_init_controller(host);
1458 }
1459
1460 ata_host_resume(host);
1461
1462 return 0;
1463 }
1464 #endif
1465
1466 static int ahci_port_start(struct ata_port *ap)
1467 {
1468 struct device *dev = ap->host->dev;
1469 struct ahci_port_priv *pp;
1470 void *mem;
1471 dma_addr_t mem_dma;
1472 int rc;
1473
1474 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1475 if (!pp)
1476 return -ENOMEM;
1477
1478 rc = ata_pad_alloc(ap, dev);
1479 if (rc)
1480 return rc;
1481
1482 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1483 GFP_KERNEL);
1484 if (!mem)
1485 return -ENOMEM;
1486 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1487
1488 /*
1489 * First item in chunk of DMA memory: 32-slot command table,
1490 * 32 bytes each in size
1491 */
1492 pp->cmd_slot = mem;
1493 pp->cmd_slot_dma = mem_dma;
1494
1495 mem += AHCI_CMD_SLOT_SZ;
1496 mem_dma += AHCI_CMD_SLOT_SZ;
1497
1498 /*
1499 * Second item: Received-FIS area
1500 */
1501 pp->rx_fis = mem;
1502 pp->rx_fis_dma = mem_dma;
1503
1504 mem += AHCI_RX_FIS_SZ;
1505 mem_dma += AHCI_RX_FIS_SZ;
1506
1507 /*
1508 * Third item: data area for storing a single command
1509 * and its scatter-gather table
1510 */
1511 pp->cmd_tbl = mem;
1512 pp->cmd_tbl_dma = mem_dma;
1513
1514 ap->private_data = pp;
1515
1516 /* power up port */
1517 ahci_power_up(ap);
1518
1519 /* initialize port */
1520 ahci_init_port(ap);
1521
1522 return 0;
1523 }
1524
1525 static void ahci_port_stop(struct ata_port *ap)
1526 {
1527 const char *emsg = NULL;
1528 int rc;
1529
1530 /* de-initialize port */
1531 rc = ahci_deinit_port(ap, &emsg);
1532 if (rc)
1533 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1534 }
1535
1536 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1537 {
1538 int rc;
1539
1540 if (using_dac &&
1541 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1542 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1543 if (rc) {
1544 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1545 if (rc) {
1546 dev_printk(KERN_ERR, &pdev->dev,
1547 "64-bit DMA enable failed\n");
1548 return rc;
1549 }
1550 }
1551 } else {
1552 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1553 if (rc) {
1554 dev_printk(KERN_ERR, &pdev->dev,
1555 "32-bit DMA enable failed\n");
1556 return rc;
1557 }
1558 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1559 if (rc) {
1560 dev_printk(KERN_ERR, &pdev->dev,
1561 "32-bit consistent DMA enable failed\n");
1562 return rc;
1563 }
1564 }
1565 return 0;
1566 }
1567
1568 static void ahci_print_info(struct ata_host *host)
1569 {
1570 struct ahci_host_priv *hpriv = host->private_data;
1571 struct pci_dev *pdev = to_pci_dev(host->dev);
1572 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1573 u32 vers, cap, impl, speed;
1574 const char *speed_s;
1575 u16 cc;
1576 const char *scc_s;
1577
1578 vers = readl(mmio + HOST_VERSION);
1579 cap = hpriv->cap;
1580 impl = hpriv->port_map;
1581
1582 speed = (cap >> 20) & 0xf;
1583 if (speed == 1)
1584 speed_s = "1.5";
1585 else if (speed == 2)
1586 speed_s = "3";
1587 else
1588 speed_s = "?";
1589
1590 pci_read_config_word(pdev, 0x0a, &cc);
1591 if (cc == PCI_CLASS_STORAGE_IDE)
1592 scc_s = "IDE";
1593 else if (cc == PCI_CLASS_STORAGE_SATA)
1594 scc_s = "SATA";
1595 else if (cc == PCI_CLASS_STORAGE_RAID)
1596 scc_s = "RAID";
1597 else
1598 scc_s = "unknown";
1599
1600 dev_printk(KERN_INFO, &pdev->dev,
1601 "AHCI %02x%02x.%02x%02x "
1602 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1603 ,
1604
1605 (vers >> 24) & 0xff,
1606 (vers >> 16) & 0xff,
1607 (vers >> 8) & 0xff,
1608 vers & 0xff,
1609
1610 ((cap >> 8) & 0x1f) + 1,
1611 (cap & 0x1f) + 1,
1612 speed_s,
1613 impl,
1614 scc_s);
1615
1616 dev_printk(KERN_INFO, &pdev->dev,
1617 "flags: "
1618 "%s%s%s%s%s%s"
1619 "%s%s%s%s%s%s%s\n"
1620 ,
1621
1622 cap & (1 << 31) ? "64bit " : "",
1623 cap & (1 << 30) ? "ncq " : "",
1624 cap & (1 << 28) ? "ilck " : "",
1625 cap & (1 << 27) ? "stag " : "",
1626 cap & (1 << 26) ? "pm " : "",
1627 cap & (1 << 25) ? "led " : "",
1628
1629 cap & (1 << 24) ? "clo " : "",
1630 cap & (1 << 19) ? "nz " : "",
1631 cap & (1 << 18) ? "only " : "",
1632 cap & (1 << 17) ? "pmp " : "",
1633 cap & (1 << 15) ? "pio " : "",
1634 cap & (1 << 14) ? "slum " : "",
1635 cap & (1 << 13) ? "part " : ""
1636 );
1637 }
1638
1639 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1640 {
1641 static int printed_version;
1642 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1643 const struct ata_port_info *ppi[] = { &pi, NULL };
1644 struct device *dev = &pdev->dev;
1645 struct ahci_host_priv *hpriv;
1646 struct ata_host *host;
1647 int i, rc;
1648
1649 VPRINTK("ENTER\n");
1650
1651 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1652
1653 if (!printed_version++)
1654 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1655
1656 /* acquire resources */
1657 rc = pcim_enable_device(pdev);
1658 if (rc)
1659 return rc;
1660
1661 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1662 if (rc == -EBUSY)
1663 pcim_pin_device(pdev);
1664 if (rc)
1665 return rc;
1666
1667 if (pci_enable_msi(pdev))
1668 pci_intx(pdev, 1);
1669
1670 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1671 if (!hpriv)
1672 return -ENOMEM;
1673
1674 /* save initial config */
1675 ahci_save_initial_config(pdev, &pi, hpriv);
1676
1677 /* prepare host */
1678 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1679 pi.flags |= ATA_FLAG_NCQ;
1680
1681 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1682 if (!host)
1683 return -ENOMEM;
1684 host->iomap = pcim_iomap_table(pdev);
1685 host->private_data = hpriv;
1686
1687 for (i = 0; i < host->n_ports; i++) {
1688 if (hpriv->port_map & (1 << i)) {
1689 struct ata_port *ap = host->ports[i];
1690 void __iomem *port_mmio = ahci_port_base(ap);
1691
1692 ap->ioaddr.cmd_addr = port_mmio;
1693 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1694 } else
1695 host->ports[i]->ops = &ata_dummy_port_ops;
1696 }
1697
1698 /* initialize adapter */
1699 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1700 if (rc)
1701 return rc;
1702
1703 rc = ahci_reset_controller(host);
1704 if (rc)
1705 return rc;
1706
1707 ahci_init_controller(host);
1708 ahci_print_info(host);
1709
1710 pci_set_master(pdev);
1711 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1712 &ahci_sht);
1713 }
1714
1715 static int __init ahci_init(void)
1716 {
1717 return pci_register_driver(&ahci_pci_driver);
1718 }
1719
1720 static void __exit ahci_exit(void)
1721 {
1722 pci_unregister_driver(&ahci_pci_driver);
1723 }
1724
1725
1726 MODULE_AUTHOR("Jeff Garzik");
1727 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1728 MODULE_LICENSE("GPL");
1729 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1730 MODULE_VERSION(DRV_VERSION);
1731
1732 module_init(ahci_init);
1733 module_exit(ahci_exit);
Tomato firmware and modifications.