release/src-rt-6.x/linux/linux-2.6/arch/sh/drivers/pci/ops-sh4.c

   1 /*
   2  * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
   3  *
   4  * Copyright (C) 2002 - 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License v2. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/pci.h>
  11 #include <asm/addrspace.h>
  12 #include <asm/io.h>
  13 #include "pci-sh4.h"
  14
  15 /*
  16  * Direct access to PCI hardware...
  17  */
  18 #define CONFIG_CMD(bus, devfn, where) \
  19         P1SEGADDR((bus->number << 16) | (devfn << 8) | (where & ~3))
  20
  21 static DEFINE_SPINLOCK(sh4_pci_lock);
  22
  23 /*
  24  * Functions for accessing PCI configuration space with type 1 accesses
  25  */
  26 static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
  27                            int where, int size, u32 *val)
  28 {
  29         unsigned long flags;
  30         u32 data;
  31
  32         /*
  33          * PCIPDR may only be accessed as 32 bit words,
  34          * so we must do byte alignment by hand
  35          */
  36         spin_lock_irqsave(&sh4_pci_lock, flags);
  37         pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
  38         data = pci_read_reg(SH4_PCIPDR);
  39         spin_unlock_irqrestore(&sh4_pci_lock, flags);
  40
  41         switch (size) {
  42         case 1:
  43                 *val = (data >> ((where & 3) << 3)) & 0xff;
  44                 break;
  45         case 2:
  46                 *val = (data >> ((where & 2) << 3)) & 0xffff;
  47                 break;
  48         case 4:
  49                 *val = data;
  50                 break;
  51         default:
  52                 return PCIBIOS_FUNC_NOT_SUPPORTED;
  53         }
  54
  55         return PCIBIOS_SUCCESSFUL;
  56 }
  57
  58 /*
  59  * Since SH4 only does 32bit access we'll have to do a read,
  60  * mask,write operation.
  61  * We'll allow an odd byte offset, though it should be illegal.
  62  */
  63 static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
  64                          int where, int size, u32 val)
  65 {
  66         unsigned long flags;
  67         int shift;
  68         u32 data;
  69
  70         spin_lock_irqsave(&sh4_pci_lock, flags);
  71         pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
  72         data = pci_read_reg(SH4_PCIPDR);
  73         spin_unlock_irqrestore(&sh4_pci_lock, flags);
  74
  75         switch (size) {
  76         case 1:
  77                 shift = (where & 3) << 3;
  78                 data &= ~(0xff << shift);
  79                 data |= ((val & 0xff) << shift);
  80                 break;
  81         case 2:
  82                 shift = (where & 2) << 3;
  83                 data &= ~(0xffff << shift);
  84                 data |= ((val & 0xffff) << shift);
  85                 break;
  86         case 4:
  87                 data = val;
  88                 break;
  89         default:
  90                 return PCIBIOS_FUNC_NOT_SUPPORTED;
  91         }
  92
  93         pci_write_reg(data, SH4_PCIPDR);
  94
  95         return PCIBIOS_SUCCESSFUL;
  96 }
  97
  98 struct pci_ops sh4_pci_ops = {
  99         .read           = sh4_pci_read,
 100         .write          = sh4_pci_write,
 101 };
 102
 103 /*
 104  * Not really related to pci_ops, but it's common and not worth shoving
 105  * somewhere else for now..
 106  */
 107 static unsigned int pci_probe = PCI_PROBE_CONF1;
 108
 109 int __init sh4_pci_check_direct(void)
 110 {
 111         /*
 112          * Check if configuration works.
 113          */
 114         if (pci_probe & PCI_PROBE_CONF1) {
 115                 unsigned int tmp = pci_read_reg(SH4_PCIPAR);
 116
 117                 pci_write_reg(P1SEG, SH4_PCIPAR);
 118
 119                 if (pci_read_reg(SH4_PCIPAR) == P1SEG) {
 120                         pci_write_reg(tmp, SH4_PCIPAR);
 121                         printk(KERN_INFO "PCI: Using configuration type 1\n");
 122                         request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1");
 123
 124                         return 0;
 125                 }
 126
 127                 pci_write_reg(tmp, SH4_PCIPAR);
 128         }
 129
 130         pr_debug("PCI: pci_check_direct failed\n");
 131         return -EINVAL;
 132 }
 133
 134 /* Handle generic fixups */
 135 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 136 {
 137         int i;
 138
 139         /*
 140          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 141          */
 142         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 143                 return;
 144         pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
 145         for(i = 0; i < 4; i++) {
 146                 struct resource *r = &d->resource[i];
 147
 148                 if ((r->start & ~0x80) == 0x374) {
 149                         r->start |= 2;
 150                         r->end = r->start;
 151                 }
 152         }
 153 }
 154 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
 155
 156 char * __init pcibios_setup(char *str)
 157 {
 158         if (!strcmp(str, "off")) {
 159                 pci_probe = 0;
 160                 return NULL;
 161         }
 162
 163         return str;
 164 }
 165
 166 int __attribute__((weak)) pci_fixup_pcic(void)
 167 {
 168         /* Nothing to do. */
 169         return 0;
 170 }