release/src-rt-6.x/linux/linux-2.6/arch/ppc/syslib/open_pic_defs.h

   1 /*
   2  *  Copyright (C) 1997 Geert Uytterhoeven
   3  *
   4  *  This file is based on the following documentation:
   5  *
   6  *      The Open Programmable Interrupt Controller (PIC)
   7  *      Register Interface Specification Revision 1.2
   8  *
   9  *      Issue Date: October 1995
  10  *
  11  *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
  12  *
  13  *      AMD is a registered trademark of Advanced Micro Devices, Inc.
  14  *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
  15  *      All Rights Reserved.
  16  *
  17  *  To receive a copy of this documentation, send an email to openpic@amd.com.
  18  *
  19  *  This file is subject to the terms and conditions of the GNU General Public
  20  *  License.  See the file COPYING in the main directory of this archive
  21  *  for more details.
  22  */
  23
  24 #ifndef _LINUX_OPENPIC_H
  25 #define _LINUX_OPENPIC_H
  26
  27 #ifdef __KERNEL__
  28
  29     /*
  30      *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
  31      */
  32
  33 #define OPENPIC_MAX_SOURCES     2048
  34 #define OPENPIC_MAX_PROCESSORS  32
  35 #define OPENPIC_MAX_ISU         16
  36
  37 #define OPENPIC_NUM_TIMERS      4
  38 #define OPENPIC_NUM_IPI         4
  39 #define OPENPIC_NUM_PRI         16
  40 #define OPENPIC_NUM_VECTORS     256
  41
  42
  43
  44     /*
  45      *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
  46      */
  47
  48 typedef struct _OpenPIC_Reg {
  49     u_int Reg;                                  /* Little endian! */
  50     char Pad[0xc];
  51 } OpenPIC_Reg;
  52
  53
  54     /*
  55      *  Per Processor Registers
  56      */
  57
  58 typedef struct _OpenPIC_Processor {
  59     /*
  60      *  Private Shadow Registers (for SLiC backwards compatibility)
  61      */
  62     u_int IPI0_Dispatch_Shadow;                 /* Write Only */
  63     char Pad1[0x4];
  64     u_int IPI0_Vector_Priority_Shadow;          /* Read/Write */
  65     char Pad2[0x34];
  66     /*
  67      *  Interprocessor Interrupt Command Ports
  68      */
  69     OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
  70     /*
  71      *  Current Task Priority Register
  72      */
  73     OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
  74     char Pad3[0x10];
  75     /*
  76      *  Interrupt Acknowledge Register
  77      */
  78     OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
  79     /*
  80      *  End of Interrupt (EOI) Register
  81      */
  82     OpenPIC_Reg _EOI;                           /* Read/Write */
  83     char Pad5[0xf40];
  84 } OpenPIC_Processor;
  85
  86
  87     /*
  88      *  Timer Registers
  89      */
  90
  91 typedef struct _OpenPIC_Timer {
  92     OpenPIC_Reg _Current_Count;                 /* Read Only */
  93     OpenPIC_Reg _Base_Count;                    /* Read/Write */
  94     OpenPIC_Reg _Vector_Priority;               /* Read/Write */
  95     OpenPIC_Reg _Destination;                   /* Read/Write */
  96 } OpenPIC_Timer;
  97
  98
  99     /*
 100      *  Global Registers
 101      */
 102
 103 typedef struct _OpenPIC_Global {
 104     /*
 105      *  Feature Reporting Registers
 106      */
 107     OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
 108     OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
 109     /*
 110      *  Global Configuration Registers
 111      */
 112     OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
 113     OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
 114     /*
 115      *  Vendor Specific Registers
 116      */
 117     OpenPIC_Reg _Vendor_Specific[4];
 118     /*
 119      *  Vendor Identification Register
 120      */
 121     OpenPIC_Reg _Vendor_Identification;         /* Read Only */
 122     /*
 123      *  Processor Initialization Register
 124      */
 125     OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
 126     /*
 127      *  IPI Vector/Priority Registers
 128      */
 129     OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
 130     /*
 131      *  Spurious Vector Register
 132      */
 133     OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
 134     /*
 135      *  Global Timer Registers
 136      */
 137     OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
 138     OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
 139     char Pad1[0xee00];
 140 } OpenPIC_Global;
 141
 142
 143     /*
 144      *  Interrupt Source Registers
 145      */
 146
 147 typedef struct _OpenPIC_Source {
 148     OpenPIC_Reg _Vector_Priority;               /* Read/Write */
 149     OpenPIC_Reg _Destination;                   /* Read/Write */
 150 } OpenPIC_Source, *OpenPIC_SourcePtr;
 151
 152
 153     /*
 154      *  OpenPIC Register Map
 155      */
 156
 157 struct OpenPIC {
 158     char Pad1[0x1000];
 159     /*
 160      *  Global Registers
 161      */
 162     OpenPIC_Global Global;
 163     /*
 164      *  Interrupt Source Configuration Registers
 165      */
 166     OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
 167     /*
 168      *  Per Processor Registers
 169      */
 170     OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
 171 };
 172
 173     /*
 174      *  Current Task Priority Register
 175      */
 176
 177 #define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
 178
 179     /*
 180      *  Who Am I Register
 181      */
 182
 183 #define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
 184
 185     /*
 186      *  Feature Reporting Register 0
 187      */
 188
 189 #define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
 190 #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
 191 #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
 192 #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
 193 #define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
 194
 195     /*
 196      *  Global Configuration Register 0
 197      */
 198
 199 #define OPENPIC_CONFIG_RESET                    0x80000000
 200 #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
 201 #define OPENPIC_CONFIG_BASE_MASK                0x000fffff
 202
 203     /*
 204      *  Global Configuration Register 1
 205      *  This is the EICR on EPICs.
 206      */
 207
 208 #define OPENPIC_EICR_S_CLK_MASK                 0x70000000
 209 #define OPENPIC_EICR_SIE                        0x08000000
 210
 211     /*
 212      *  Vendor Identification Register
 213      */
 214
 215 #define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
 216 #define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
 217 #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
 218 #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
 219 #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
 220
 221     /*
 222      *  Vector/Priority Registers
 223      */
 224
 225 #define OPENPIC_MASK                            0x80000000
 226 #define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
 227 #define OPENPIC_PRIORITY_MASK                   0x000f0000
 228 #define OPENPIC_PRIORITY_SHIFT                  16
 229 #define OPENPIC_VECTOR_MASK                     0x000000ff
 230
 231
 232     /*
 233      *  Interrupt Source Registers
 234      */
 235
 236 #define OPENPIC_POLARITY_POSITIVE               0x00800000
 237 #define OPENPIC_POLARITY_NEGATIVE               0x00000000
 238 #define OPENPIC_POLARITY_MASK                   0x00800000
 239 #define OPENPIC_SENSE_LEVEL                     0x00400000
 240 #define OPENPIC_SENSE_EDGE                      0x00000000
 241 #define OPENPIC_SENSE_MASK                      0x00400000
 242
 243
 244     /*
 245      *  Timer Registers
 246      */
 247
 248 #define OPENPIC_COUNT_MASK                      0x7fffffff
 249 #define OPENPIC_TIMER_TOGGLE                    0x80000000
 250 #define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
 251
 252
 253     /*
 254      *  Aliases to make life simpler
 255      */
 256
 257 /* Per Processor Registers */
 258 #define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
 259 #define Current_Task_Priority           _Current_Task_Priority.Reg
 260 #define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
 261 #define EOI                             _EOI.Reg
 262
 263 /* Global Registers */
 264 #define Feature_Reporting0              _Feature_Reporting0.Reg
 265 #define Feature_Reporting1              _Feature_Reporting1.Reg
 266 #define Global_Configuration0           _Global_Configuration0.Reg
 267 #define Global_Configuration1           _Global_Configuration1.Reg
 268 #define Vendor_Specific(i)              _Vendor_Specific[i].Reg
 269 #define Vendor_Identification           _Vendor_Identification.Reg
 270 #define Processor_Initialization        _Processor_Initialization.Reg
 271 #define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
 272 #define Spurious_Vector                 _Spurious_Vector.Reg
 273 #define Timer_Frequency                 _Timer_Frequency.Reg
 274
 275 /* Timer Registers */
 276 #define Current_Count                   _Current_Count.Reg
 277 #define Base_Count                      _Base_Count.Reg
 278 #define Vector_Priority                 _Vector_Priority.Reg
 279 #define Destination                     _Destination.Reg
 280
 281 /* Interrupt Source Registers */
 282 #define Vector_Priority                 _Vector_Priority.Reg
 283 #define Destination                     _Destination.Reg
 284
 285 #endif /* __KERNEL__ */
 286
 287 #endif /* _LINUX_OPENPIC_H */