release/src-rt-6.x/linux/linux-2.6/arch/ppc/platforms/fads.h

   1 /*
   2  * A collection of structures, addresses, and values associated with
   3  * the Motorola 860T FADS board.  Copied from the MBX stuff.
   4  *
   5  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
   6  *
   7  * Added MPC86XADS support.
   8  * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
   9  * for SW point of view". This is 99% correct.
  10  *
  11  * Author: MontaVista Software, Inc.
  12  *         source@mvista.com
  13  * 2005 (c) MontaVista Software, Inc.  This file is licensed under the
  14  * terms of the GNU General Public License version 2.  This program is licensed
  15  * "as is" without any warranty of any kind, whether express or implied.
  16  */
  17
  18 #ifdef __KERNEL__
  19 #ifndef __ASM_FADS_H__
  20 #define __ASM_FADS_H__
  21
  22
  23 #include <asm/ppcboot.h>
  24
  25 #if defined(CONFIG_MPC86XADS)
  26
  27 #define BOARD_CHIP_NAME "MPC86X"
  28
  29 /* U-Boot maps BCSR to 0xff080000 */
  30 #define BCSR_ADDR               ((uint)0xff080000)
  31
  32 /* MPC86XADS has one more CPLD and an additional BCSR.
  33  */
  34 #define CFG_PHYDEV_ADDR         ((uint)0xff0a0000)
  35 #define BCSR5                   ((uint)(CFG_PHYDEV_ADDR + 0x300))
  36
  37 #define BCSR5_T1_RST            0x10
  38 #define BCSR5_ATM155_RST        0x08
  39 #define BCSR5_ATM25_RST         0x04
  40 #define BCSR5_MII1_EN           0x02
  41 #define BCSR5_MII1_RST          0x01
  42
  43 /* There is no PHY link change interrupt */
  44 #define PHY_INTERRUPT   (-1)
  45
  46 #else /* FADS */
  47
  48 /* Memory map is configured by the PROM startup.
  49  * I tried to follow the FADS manual, although the startup PROM
  50  * dictates this and we simply have to move some of the physical
  51  * addresses for Linux.
  52  */
  53 #define BCSR_ADDR               ((uint)0xff010000)
  54
  55 /* PHY link change interrupt */
  56 #define PHY_INTERRUPT   SIU_IRQ2
  57
  58 #endif /* CONFIG_MPC86XADS */
  59
  60 #define BCSR_SIZE               ((uint)(64 * 1024))
  61 #define BCSR0                   ((uint)(BCSR_ADDR + 0x00))
  62 #define BCSR1                   ((uint)(BCSR_ADDR + 0x04))
  63 #define BCSR2                   ((uint)(BCSR_ADDR + 0x08))
  64 #define BCSR3                   ((uint)(BCSR_ADDR + 0x0c))
  65 #define BCSR4                   ((uint)(BCSR_ADDR + 0x10))
  66
  67 #define IMAP_ADDR               ((uint)0xff000000)
  68 #define IMAP_SIZE               ((uint)(64 * 1024))
  69
  70 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
  71 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
  72
  73 /* Bits of interest in the BCSRs.
  74  */
  75 #define BCSR1_ETHEN             ((uint)0x20000000)
  76 #define BCSR1_IRDAEN            ((uint)0x10000000)
  77 #define BCSR1_RS232EN_1         ((uint)0x01000000)
  78 #define BCSR1_PCCEN             ((uint)0x00800000)
  79 #define BCSR1_PCCVCC0           ((uint)0x00400000)
  80 #define BCSR1_PCCVPP0           ((uint)0x00200000)
  81 #define BCSR1_PCCVPP1           ((uint)0x00100000)
  82 #define BCSR1_PCCVPP_MASK       (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
  83 #define BCSR1_RS232EN_2         ((uint)0x00040000)
  84 #define BCSR1_PCCVCC1           ((uint)0x00010000)
  85 #define BCSR1_PCCVCC_MASK       (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
  86
  87 #define BCSR4_ETHLOOP           ((uint)0x80000000)      /* EEST Loopback */
  88 #define BCSR4_EEFDX             ((uint)0x40000000)      /* EEST FDX enable */
  89 #define BCSR4_FETH_EN           ((uint)0x08000000)      /* PHY enable */
  90 #define BCSR4_FETHCFG0          ((uint)0x04000000)      /* PHY autoneg mode */
  91 #define BCSR4_FETHCFG1          ((uint)0x00400000)      /* PHY autoneg mode */
  92 #define BCSR4_FETHFDE           ((uint)0x02000000)      /* PHY FDX advertise */
  93 #define BCSR4_FETHRST           ((uint)0x00200000)      /* PHY Reset */
  94
  95 /* IO_BASE definition for pcmcia.
  96  */
  97 #define _IO_BASE        0x80000000
  98 #define _IO_BASE_SIZE   0x1000
  99
 100 #ifdef CONFIG_IDE
 101 #define MAX_HWIFS 1
 102 #endif
 103
 104 /* Interrupt level assignments.
 105  */
 106 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 107
 108 /* We don't use the 8259.
 109  */
 110 #define NR_8259_INTS    0
 111
 112 /* CPM Ethernet through SCC1 or SCC2 */
 113
 114 #if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1)         /* Probably 860 variant */
 115 /* Bits in parallel I/O port registers that have to be set/cleared
 116  * to configure the pins for SCC1 use.
 117  * TCLK - CLK1, RCLK - CLK2.
 118  */
 119 #define PA_ENET_RXD     ((ushort)0x0001)
 120 #define PA_ENET_TXD     ((ushort)0x0002)
 121 #define PA_ENET_TCLK    ((ushort)0x0100)
 122 #define PA_ENET_RCLK    ((ushort)0x0200)
 123 #define PB_ENET_TENA    ((uint)0x00001000)
 124 #define PC_ENET_CLSN    ((ushort)0x0010)
 125 #define PC_ENET_RENA    ((ushort)0x0020)
 126
 127 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 128  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 129  */
 130 #define SICR_ENET_MASK  ((uint)0x000000ff)
 131 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 132 #endif /* CONFIG_SCC1_ENET */
 133
 134 #ifdef CONFIG_SCC2_ENET         /* Probably 823/850 variant */
 135 /* Bits in parallel I/O port registers that have to be set/cleared
 136  * to configure the pins for SCC1 use.
 137  * TCLK - CLK1, RCLK - CLK2.
 138  */
 139 #define PA_ENET_RXD     ((ushort)0x0004)
 140 #define PA_ENET_TXD     ((ushort)0x0008)
 141 #define PA_ENET_TCLK    ((ushort)0x0400)
 142 #define PA_ENET_RCLK    ((ushort)0x0200)
 143 #define PB_ENET_TENA    ((uint)0x00002000)
 144 #define PC_ENET_CLSN    ((ushort)0x0040)
 145 #define PC_ENET_RENA    ((ushort)0x0080)
 146
 147 /* Control bits in the SICR to route TCLK and RCLK to
 148  * SCC2.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 149  */
 150 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 151 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 152 #endif /* CONFIG_SCC2_ENET */
 153
 154 #endif /* __ASM_FADS_H__ */
 155 #endif /* __KERNEL__ */