release/src-rt-6.x/linux/linux-2.6/arch/ppc/platforms/apus_pci.c

   1 /*
   2  * Copyright (C) Michel Dänzer <michdaen@iiic.ethz.ch>
   3  *
   4  * APUS PCI routines.
   5  *
   6  * Currently, only B/CVisionPPC cards (Permedia2) are supported.
   7  *
   8  * Thanks to Geert Uytterhoeven for the idea:
   9  * Read values from given config space(s) for the first devices, -1 otherwise
  10  *
  11  */
  12
  13 #ifdef CONFIG_AMIGA
  14
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/pci-bridge.h>
  23 #include <asm/machdep.h>
  24
  25 #include "apus_pci.h"
  26
  27
  28 /* These definitions are mostly adapted from pm2fb.c */
  29
  30 #undef APUS_PCI_MASTER_DEBUG
  31 #ifdef APUS_PCI_MASTER_DEBUG
  32 #define DPRINTK(a,b...) printk(KERN_DEBUG "apus_pci: %s: " a, __FUNCTION__ , ## b)
  33 #else
  34 #define DPRINTK(a,b...)
  35 #endif
  36
  37 /*
  38  * The _DEFINITIVE_ memory mapping/unmapping functions.
  39  * This is due to the fact that they're changing soooo often...
  40  */
  41 #define DEFW()          wmb()
  42 #define DEFR()          rmb()
  43 #define DEFRW()         mb()
  44
  45 #define DEVNO(d)        ((d)>>3)
  46 #define FNNO(d)         ((d)&7)
  47
  48
  49 extern unsigned long powerup_PCI_present;
  50
  51 static struct pci_controller *apus_hose;
  52
  53
  54 void *pci_io_base(unsigned int bus)
  55 {
  56         return 0;
  57 }
  58
  59
  60 int
  61 apus_pcibios_read_config(struct pci_bus *bus, int devfn, int offset,
  62                          int len, u32 *val)
  63 {
  64         int fnno = FNNO(devfn);
  65         int devno = DEVNO(devfn);
  66         volatile unsigned char *cfg_data;
  67
  68         if (bus->number > 0 || devno != 1) {
  69                 *val = ~0;
  70                 return PCIBIOS_DEVICE_NOT_FOUND;
  71         }
  72         /* base address + function offset + offset ^ endianness conversion */
  73         /* XXX the fnno<<5 bit seems wacky  -- paulus */
  74         cfg_data = apus_hose->cfg_data + (fnno<<5) + (offset ^ (len - 1));
  75         switch (len) {
  76         case 1:
  77                 *val = readb(cfg_data);
  78                 break;
  79         case 2:
  80                 *val = readw(cfg_data);
  81                 break;
  82         default:
  83                 *val = readl(cfg_data);
  84                 break;
  85         }
  86
  87         DPRINTK("read b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, l: %d, v: 0x%x\n",
  88                 bus->number, devfn>>3, devfn&7, offset, len, *val);
  89         return PCIBIOS_SUCCESSFUL;
  90 }
  91
  92 int
  93 apus_pcibios_write_config(struct pci_bus *bus, int devfn, int offset,
  94                           int len, u32 *val)
  95 {
  96         int fnno = FNNO(devfn);
  97         int devno = DEVNO(devfn);
  98         volatile unsigned char *cfg_data;
  99
 100         if (bus->number > 0 || devno != 1) {
 101                 return PCIBIOS_DEVICE_NOT_FOUND;
 102         }
 103         /* base address + function offset + offset ^ endianness conversion */
 104         /* XXX the fnno<<5 bit seems wacky  -- paulus */
 105         cfg_data = apus_hose->cfg_data + (fnno<<5) + (offset ^ (len - 1));
 106         switch (len) {
 107         case 1:
 108                 writeb(val, cfg_data); DEFW();
 109                 break;
 110         case 2:
 111                 writew(val, cfg_data); DEFW();
 112                 break;
 113         default:
 114                 writel(val, cfg_data); DEFW();
 115                 break;
 116         }
 117
 118         DPRINTK("write b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, l: %d, v: 0x%x\n",
 119                 bus->number, devfn>>3, devfn&7, offset, len, val);
 120         return PCIBIOS_SUCCESSFUL;
 121 }
 122
 123 static struct pci_ops apus_pci_ops = {
 124         apus_pcibios_read_config,
 125         apus_pcibios_write_config
 126 };
 127
 128 static struct resource pci_mem = { "B/CVisionPPC PCI mem", CVPPC_FB_APERTURE_ONE, CVPPC_PCI_CONFIG, IORESOURCE_MEM };
 129
 130 void __init
 131 apus_pcibios_fixup(void)
 132 {
 133 /*      struct pci_dev *dev = pci_find_slot(0, 1<<3);
 134         unsigned int reg, val, offset;*/
 135
 136         /* FIXME: interrupt? */
 137         /*dev->interrupt = xxx;*/
 138
 139         request_resource(&iomem_resource, &pci_mem);
 140         printk("%s: PCI mem resource requested\n", __FUNCTION__);
 141 }
 142
 143 static void __init apus_pcibios_fixup_bus(struct pci_bus *bus)
 144 {
 145         bus->resource[1] = &pci_mem;
 146 }
 147
 148
 149 /*
 150  * This is from pm2fb.c again
 151  *
 152  * Check if PCI (B/CVisionPPC) is available, initialize it and set up
 153  * the pcibios_* pointers
 154  */
 155
 156
 157 void __init
 158 apus_setup_pci_ptrs(void)
 159 {
 160         if (!powerup_PCI_present) {
 161                 DPRINTK("no PCI bridge detected\n");
 162                 return;
 163         }
 164         DPRINTK("Phase5 B/CVisionPPC PCI bridge detected.\n");
 165
 166         apus_hose = pcibios_alloc_controller();
 167         if (!apus_hose) {
 168                 printk("apus_pci: Can't allocate PCI controller structure\n");
 169                 return;
 170         }
 171
 172         if (!(apus_hose->cfg_data = ioremap(CVPPC_PCI_CONFIG, 256))) {
 173                 printk("apus_pci: unable to map PCI config region\n");
 174                 return;
 175         }
 176
 177         if (!(apus_hose->cfg_addr = ioremap(CSPPC_PCI_BRIDGE, 256))) {
 178                 printk("apus_pci: unable to map PCI bridge\n");
 179                 return;
 180         }
 181
 182         writel(CSPPCF_BRIDGE_BIG_ENDIAN, apus_hose->cfg_addr + CSPPC_BRIDGE_ENDIAN);
 183         DEFW();
 184
 185         writel(CVPPC_REGS_REGION,  apus_hose->cfg_data+ PCI_BASE_ADDRESS_0);
 186         DEFW();
 187         writel(CVPPC_FB_APERTURE_ONE, apus_hose->cfg_data + PCI_BASE_ADDRESS_1);
 188         DEFW();
 189         writel(CVPPC_FB_APERTURE_TWO, apus_hose->cfg_data + PCI_BASE_ADDRESS_2);
 190         DEFW();
 191         writel(CVPPC_ROM_ADDRESS, apus_hose->cfg_data + PCI_ROM_ADDRESS);
 192         DEFW();
 193
 194         writel(0xef000000 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 195                 PCI_COMMAND_MASTER, apus_hose->cfg_data + PCI_COMMAND);
 196         DEFW();
 197
 198         apus_hose->first_busno = 0;
 199         apus_hose->last_busno = 0;
 200         apus_hose->ops = &apus_pci_ops;
 201         ppc_md.pcibios_fixup = apus_pcibios_fixup;
 202         ppc_md.pcibios_fixup_bus = apus_pcibios_fixup_bus;
 203
 204         return;
 205 }
 206
 207 #endif /* CONFIG_AMIGA */