release/src-rt-6.x/linux/linux-2.6/arch/powerpc/platforms/cell/spufs/backing_ops.c

   1 /* backing_ops.c - query/set operations on saved SPU context.
   2  *
   3  * Copyright (C) IBM 2005
   4  * Author: Mark Nutter <mnutter@us.ibm.com>
   5  *
   6  * These register operations allow SPUFS to operate on saved
   7  * SPU contexts rather than hardware.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2, or (at your option)
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/errno.h>
  26 #include <linux/sched.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/vmalloc.h>
  30 #include <linux/smp.h>
  31 #include <linux/stddef.h>
  32 #include <linux/unistd.h>
  33 #include <linux/poll.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/spu.h>
  37 #include <asm/spu_csa.h>
  38 #include <asm/spu_info.h>
  39 #include <asm/mmu_context.h>
  40 #include "spufs.h"
  41
  42 /*
  43  * Reads/writes to various problem and priv2 registers require
  44  * state changes, i.e.  generate SPU events, modify channel
  45  * counts, etc.
  46  */
  47
  48 static void gen_spu_event(struct spu_context *ctx, u32 event)
  49 {
  50         u64 ch0_cnt;
  51         u64 ch0_data;
  52         u64 ch1_data;
  53
  54         ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
  55         ch0_data = ctx->csa.spu_chnldata_RW[0];
  56         ch1_data = ctx->csa.spu_chnldata_RW[1];
  57         ctx->csa.spu_chnldata_RW[0] |= event;
  58         if ((ch0_cnt == 0) && !(ch0_data & event) && (ch1_data & event)) {
  59                 ctx->csa.spu_chnlcnt_RW[0] = 1;
  60         }
  61 }
  62
  63 static int spu_backing_mbox_read(struct spu_context *ctx, u32 * data)
  64 {
  65         u32 mbox_stat;
  66         int ret = 0;
  67
  68         spin_lock(&ctx->csa.register_lock);
  69         mbox_stat = ctx->csa.prob.mb_stat_R;
  70         if (mbox_stat & 0x0000ff) {
  71                 /* Read the first available word.
  72                  * Implementation note: the depth
  73                  * of pu_mb_R is currently 1.
  74                  */
  75                 *data = ctx->csa.prob.pu_mb_R;
  76                 ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
  77                 ctx->csa.spu_chnlcnt_RW[28] = 1;
  78                 gen_spu_event(ctx, MFC_PU_MAILBOX_AVAILABLE_EVENT);
  79                 ret = 4;
  80         }
  81         spin_unlock(&ctx->csa.register_lock);
  82         return ret;
  83 }
  84
  85 static u32 spu_backing_mbox_stat_read(struct spu_context *ctx)
  86 {
  87         return ctx->csa.prob.mb_stat_R;
  88 }
  89
  90 static unsigned int spu_backing_mbox_stat_poll(struct spu_context *ctx,
  91                                           unsigned int events)
  92 {
  93         int ret;
  94         u32 stat;
  95
  96         ret = 0;
  97         spin_lock_irq(&ctx->csa.register_lock);
  98         stat = ctx->csa.prob.mb_stat_R;
  99
 100         /* if the requested event is there, return the poll
 101            mask, otherwise enable the interrupt to get notified,
 102            but first mark any pending interrupts as done so
 103            we don't get woken up unnecessarily */
 104
 105         if (events & (POLLIN | POLLRDNORM)) {
 106                 if (stat & 0xff0000)
 107                         ret |= POLLIN | POLLRDNORM;
 108                 else {
 109                         ctx->csa.priv1.int_stat_class0_RW &= ~0x1;
 110                         ctx->csa.priv1.int_mask_class2_RW |= 0x1;
 111                 }
 112         }
 113         if (events & (POLLOUT | POLLWRNORM)) {
 114                 if (stat & 0x00ff00)
 115                         ret = POLLOUT | POLLWRNORM;
 116                 else {
 117                         ctx->csa.priv1.int_stat_class0_RW &= ~0x10;
 118                         ctx->csa.priv1.int_mask_class2_RW |= 0x10;
 119                 }
 120         }
 121         spin_unlock_irq(&ctx->csa.register_lock);
 122         return ret;
 123 }
 124
 125 static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data)
 126 {
 127         int ret;
 128
 129         spin_lock(&ctx->csa.register_lock);
 130         if (ctx->csa.prob.mb_stat_R & 0xff0000) {
 131                 /* Read the first available word.
 132                  * Implementation note: the depth
 133                  * of puint_mb_R is currently 1.
 134                  */
 135                 *data = ctx->csa.priv2.puint_mb_R;
 136                 ctx->csa.prob.mb_stat_R &= ~(0xff0000);
 137                 ctx->csa.spu_chnlcnt_RW[30] = 1;
 138                 gen_spu_event(ctx, MFC_PU_INT_MAILBOX_AVAILABLE_EVENT);
 139                 ret = 4;
 140         } else {
 141                 /* make sure we get woken up by the interrupt */
 142                 ctx->csa.priv1.int_mask_class2_RW |= 0x1UL;
 143                 ret = 0;
 144         }
 145         spin_unlock(&ctx->csa.register_lock);
 146         return ret;
 147 }
 148
 149 static int spu_backing_wbox_write(struct spu_context *ctx, u32 data)
 150 {
 151         int ret;
 152
 153         spin_lock(&ctx->csa.register_lock);
 154         if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
 155                 int slot = ctx->csa.spu_chnlcnt_RW[29];
 156                 int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
 157
 158                 /* We have space to write wbox_data.
 159                  * Implementation note: the depth
 160                  * of spu_mb_W is currently 4.
 161                  */
 162                 BUG_ON(avail != (4 - slot));
 163                 ctx->csa.spu_mailbox_data[slot] = data;
 164                 ctx->csa.spu_chnlcnt_RW[29] = ++slot;
 165                 ctx->csa.prob.mb_stat_R = (((4 - slot) & 0xff) << 8);
 166                 gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT);
 167                 ret = 4;
 168         } else {
 169                 /* make sure we get woken up by the interrupt when space
 170                    becomes available */
 171                 ctx->csa.priv1.int_mask_class2_RW |= 0x10;
 172                 ret = 0;
 173         }
 174         spin_unlock(&ctx->csa.register_lock);
 175         return ret;
 176 }
 177
 178 static u32 spu_backing_signal1_read(struct spu_context *ctx)
 179 {
 180         return ctx->csa.spu_chnldata_RW[3];
 181 }
 182
 183 static void spu_backing_signal1_write(struct spu_context *ctx, u32 data)
 184 {
 185         spin_lock(&ctx->csa.register_lock);
 186         if (ctx->csa.priv2.spu_cfg_RW & 0x1)
 187                 ctx->csa.spu_chnldata_RW[3] |= data;
 188         else
 189                 ctx->csa.spu_chnldata_RW[3] = data;
 190         ctx->csa.spu_chnlcnt_RW[3] = 1;
 191         gen_spu_event(ctx, MFC_SIGNAL_1_EVENT);
 192         spin_unlock(&ctx->csa.register_lock);
 193 }
 194
 195 static u32 spu_backing_signal2_read(struct spu_context *ctx)
 196 {
 197         return ctx->csa.spu_chnldata_RW[4];
 198 }
 199
 200 static void spu_backing_signal2_write(struct spu_context *ctx, u32 data)
 201 {
 202         spin_lock(&ctx->csa.register_lock);
 203         if (ctx->csa.priv2.spu_cfg_RW & 0x2)
 204                 ctx->csa.spu_chnldata_RW[4] |= data;
 205         else
 206                 ctx->csa.spu_chnldata_RW[4] = data;
 207         ctx->csa.spu_chnlcnt_RW[4] = 1;
 208         gen_spu_event(ctx, MFC_SIGNAL_2_EVENT);
 209         spin_unlock(&ctx->csa.register_lock);
 210 }
 211
 212 static void spu_backing_signal1_type_set(struct spu_context *ctx, u64 val)
 213 {
 214         u64 tmp;
 215
 216         spin_lock(&ctx->csa.register_lock);
 217         tmp = ctx->csa.priv2.spu_cfg_RW;
 218         if (val)
 219                 tmp |= 1;
 220         else
 221                 tmp &= ~1;
 222         ctx->csa.priv2.spu_cfg_RW = tmp;
 223         spin_unlock(&ctx->csa.register_lock);
 224 }
 225
 226 static u64 spu_backing_signal1_type_get(struct spu_context *ctx)
 227 {
 228         return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
 229 }
 230
 231 static void spu_backing_signal2_type_set(struct spu_context *ctx, u64 val)
 232 {
 233         u64 tmp;
 234
 235         spin_lock(&ctx->csa.register_lock);
 236         tmp = ctx->csa.priv2.spu_cfg_RW;
 237         if (val)
 238                 tmp |= 2;
 239         else
 240                 tmp &= ~2;
 241         ctx->csa.priv2.spu_cfg_RW = tmp;
 242         spin_unlock(&ctx->csa.register_lock);
 243 }
 244
 245 static u64 spu_backing_signal2_type_get(struct spu_context *ctx)
 246 {
 247         return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
 248 }
 249
 250 static u32 spu_backing_npc_read(struct spu_context *ctx)
 251 {
 252         return ctx->csa.prob.spu_npc_RW;
 253 }
 254
 255 static void spu_backing_npc_write(struct spu_context *ctx, u32 val)
 256 {
 257         ctx->csa.prob.spu_npc_RW = val;
 258 }
 259
 260 static u32 spu_backing_status_read(struct spu_context *ctx)
 261 {
 262         return ctx->csa.prob.spu_status_R;
 263 }
 264
 265 static char *spu_backing_get_ls(struct spu_context *ctx)
 266 {
 267         return ctx->csa.lscsa->ls;
 268 }
 269
 270 static u32 spu_backing_runcntl_read(struct spu_context *ctx)
 271 {
 272         return ctx->csa.prob.spu_runcntl_RW;
 273 }
 274
 275 static void spu_backing_runcntl_write(struct spu_context *ctx, u32 val)
 276 {
 277         spin_lock(&ctx->csa.register_lock);
 278         ctx->csa.prob.spu_runcntl_RW = val;
 279         if (val & SPU_RUNCNTL_RUNNABLE) {
 280                 ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
 281         } else {
 282                 ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
 283         }
 284         spin_unlock(&ctx->csa.register_lock);
 285 }
 286
 287 static void spu_backing_master_start(struct spu_context *ctx)
 288 {
 289         struct spu_state *csa = &ctx->csa;
 290         u64 sr1;
 291
 292         spin_lock(&csa->register_lock);
 293         sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
 294         csa->priv1.mfc_sr1_RW = sr1;
 295         spin_unlock(&csa->register_lock);
 296 }
 297
 298 static void spu_backing_master_stop(struct spu_context *ctx)
 299 {
 300         struct spu_state *csa = &ctx->csa;
 301         u64 sr1;
 302
 303         spin_lock(&csa->register_lock);
 304         sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
 305         csa->priv1.mfc_sr1_RW = sr1;
 306         spin_unlock(&csa->register_lock);
 307 }
 308
 309 static int spu_backing_set_mfc_query(struct spu_context * ctx, u32 mask,
 310                                         u32 mode)
 311 {
 312         struct spu_problem_collapsed *prob = &ctx->csa.prob;
 313         int ret;
 314
 315         spin_lock(&ctx->csa.register_lock);
 316         ret = -EAGAIN;
 317         if (prob->dma_querytype_RW)
 318                 goto out;
 319         ret = 0;
 320         /* FIXME: what are the side-effects of this? */
 321         prob->dma_querymask_RW = mask;
 322         prob->dma_querytype_RW = mode;
 323 out:
 324         spin_unlock(&ctx->csa.register_lock);
 325
 326         return ret;
 327 }
 328
 329 static u32 spu_backing_read_mfc_tagstatus(struct spu_context * ctx)
 330 {
 331         return ctx->csa.prob.dma_tagstatus_R;
 332 }
 333
 334 static u32 spu_backing_get_mfc_free_elements(struct spu_context *ctx)
 335 {
 336         return ctx->csa.prob.dma_qstatus_R;
 337 }
 338
 339 static int spu_backing_send_mfc_command(struct spu_context *ctx,
 340                                         struct mfc_dma_command *cmd)
 341 {
 342         int ret;
 343
 344         spin_lock(&ctx->csa.register_lock);
 345         ret = -EAGAIN;
 346         /* FIXME: set up priv2->puq */
 347         spin_unlock(&ctx->csa.register_lock);
 348
 349         return ret;
 350 }
 351
 352 static void spu_backing_restart_dma(struct spu_context *ctx)
 353 {
 354         /* nothing to do here */
 355 }
 356
 357 struct spu_context_ops spu_backing_ops = {
 358         .mbox_read = spu_backing_mbox_read,
 359         .mbox_stat_read = spu_backing_mbox_stat_read,
 360         .mbox_stat_poll = spu_backing_mbox_stat_poll,
 361         .ibox_read = spu_backing_ibox_read,
 362         .wbox_write = spu_backing_wbox_write,
 363         .signal1_read = spu_backing_signal1_read,
 364         .signal1_write = spu_backing_signal1_write,
 365         .signal2_read = spu_backing_signal2_read,
 366         .signal2_write = spu_backing_signal2_write,
 367         .signal1_type_set = spu_backing_signal1_type_set,
 368         .signal1_type_get = spu_backing_signal1_type_get,
 369         .signal2_type_set = spu_backing_signal2_type_set,
 370         .signal2_type_get = spu_backing_signal2_type_get,
 371         .npc_read = spu_backing_npc_read,
 372         .npc_write = spu_backing_npc_write,
 373         .status_read = spu_backing_status_read,
 374         .get_ls = spu_backing_get_ls,
 375         .runcntl_read = spu_backing_runcntl_read,
 376         .runcntl_write = spu_backing_runcntl_write,
 377         .master_start = spu_backing_master_start,
 378         .master_stop = spu_backing_master_stop,
 379         .set_mfc_query = spu_backing_set_mfc_query,
 380         .read_mfc_tagstatus = spu_backing_read_mfc_tagstatus,
 381         .get_mfc_free_elements = spu_backing_get_mfc_free_elements,
 382         .send_mfc_command = spu_backing_send_mfc_command,
 383         .restart_dma = spu_backing_restart_dma,
 384 };