RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / arch / powerpc / platforms / 52xx / mpc52xx_pm.c
blobfd40044d16cdd561672facb645f1c2d5f3817a38
1 #include <linux/init.h>
2 #include <linux/pm.h>
3 #include <linux/io.h>
4 #include <asm/time.h>
5 #include <asm/cacheflush.h>
6 #include <asm/mpc52xx.h>
8 #include "mpc52xx_pic.h"
11 /* these are defined in mpc52xx_sleep.S, and only used here */
12 extern void mpc52xx_deep_sleep(void *sram, void *sdram_regs,
13 struct mpc52xx_cdm *, struct mpc52xx_intr *);
14 extern void mpc52xx_ds_sram(void);
15 extern const long mpc52xx_ds_sram_size;
16 extern void mpc52xx_ds_cached(void);
17 extern const long mpc52xx_ds_cached_size;
19 static void __iomem *mbar;
20 static void __iomem *sdram;
21 static struct mpc52xx_cdm __iomem *cdm;
22 static struct mpc52xx_intr __iomem *intr;
23 static struct mpc52xx_gpio_wkup __iomem *gpiow;
24 static void *sram;
25 static int sram_size;
27 struct mpc52xx_suspend mpc52xx_suspend;
29 static int mpc52xx_pm_valid(suspend_state_t state)
31 switch (state) {
32 case PM_SUSPEND_STANDBY:
33 return 1;
34 default:
35 return 0;
39 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level)
41 u16 tmp;
43 /* enable gpio */
44 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin));
45 /* set as input */
46 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin));
47 /* enable deep sleep interrupt */
48 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin));
49 /* low/high level creates wakeup interrupt */
50 tmp = in_be16(&gpiow->wkup_itype);
51 tmp &= ~(0x3 << (pin * 2));
52 tmp |= (!level + 1) << (pin * 2);
53 out_be16(&gpiow->wkup_itype, tmp);
54 /* master enable */
55 out_8(&gpiow->wkup_maste, 1);
57 return 0;
60 int mpc52xx_pm_prepare(suspend_state_t state)
62 if (state != PM_SUSPEND_STANDBY)
63 return -EINVAL;
65 /* map the whole register space */
66 mbar = mpc52xx_find_and_map("mpc5200");
67 if (!mbar) {
68 printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
69 return -ENOSYS;
71 /* these offsets are from mpc5200 users manual */
72 sdram = mbar + 0x100;
73 cdm = mbar + 0x200;
74 intr = mbar + 0x500;
75 gpiow = mbar + 0xc00;
76 sram = mbar + 0x8000; /* Those will be handled by the */
77 sram_size = 0x4000; /* bestcomm driver soon */
79 /* call board suspend code, if applicable */
80 if (mpc52xx_suspend.board_suspend_prepare)
81 mpc52xx_suspend.board_suspend_prepare(mbar);
82 else {
83 printk(KERN_ALERT "%s: %i don't know how to wake up the board\n",
84 __func__, __LINE__);
85 goto out_unmap;
88 return 0;
90 out_unmap:
91 iounmap(mbar);
92 return -ENOSYS;
96 char saved_sram[0x4000];
98 int mpc52xx_pm_enter(suspend_state_t state)
100 u32 clk_enables;
101 u32 msr, hid0;
102 u32 intr_main_mask;
103 void __iomem * irq_0x500 = (void *)CONFIG_KERNEL_START + 0x500;
104 unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size;
105 char saved_0x500[mpc52xx_ds_cached_size];
107 /* disable all interrupts in PIC */
108 intr_main_mask = in_be32(&intr->main_mask);
109 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff);
111 /* don't let DEC expire any time soon */
112 mtspr(SPRN_DEC, 0x7fffffff);
114 /* save SRAM */
115 memcpy(saved_sram, sram, sram_size);
117 /* copy low level suspend code to sram */
118 memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size);
120 out_8(&cdm->ccs_sleep_enable, 1);
121 out_8(&cdm->osc_sleep_enable, 1);
122 out_8(&cdm->ccs_qreq_test, 1);
124 /* disable all but SDRAM and bestcomm (SRAM) clocks */
125 clk_enables = in_be32(&cdm->clk_enables);
126 out_be32(&cdm->clk_enables, clk_enables & 0x00088000);
128 /* disable power management */
129 msr = mfmsr();
130 mtmsr(msr & ~MSR_POW);
132 /* enable sleep mode, disable others */
133 hid0 = mfspr(SPRN_HID0);
134 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP);
136 /* save original, copy our irq handler, flush from dcache and invalidate icache */
137 memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size);
138 memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size);
139 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
141 /* call low-level sleep code */
142 mpc52xx_deep_sleep(sram, sdram, cdm, intr);
144 /* restore original irq handler */
145 memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size);
146 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
148 /* restore old power mode */
149 mtmsr(msr & ~MSR_POW);
150 mtspr(SPRN_HID0, hid0);
151 mtmsr(msr);
153 out_be32(&cdm->clk_enables, clk_enables);
154 out_8(&cdm->ccs_sleep_enable, 0);
155 out_8(&cdm->osc_sleep_enable, 0);
157 /* restore SRAM */
158 memcpy(sram, saved_sram, sram_size);
160 /* restart jiffies */
161 wakeup_decrementer();
163 /* reenable interrupts in PIC */
164 out_be32(&intr->main_mask, intr_main_mask);
166 return 0;
169 int mpc52xx_pm_finish(suspend_state_t state)
171 /* call board resume code */
172 if (mpc52xx_suspend.board_resume_finish)
173 mpc52xx_suspend.board_resume_finish(mbar);
175 iounmap(mbar);
177 return 0;
180 static struct pm_ops mpc52xx_pm_ops = {
181 .valid = mpc52xx_pm_valid,
182 .prepare = mpc52xx_pm_prepare,
183 .enter = mpc52xx_pm_enter,
184 .finish = mpc52xx_pm_finish,
187 int __init mpc52xx_pm_init(void)
189 pm_set_ops(&mpc52xx_pm_ops);
190 return 0;