release/src-rt-6.x/linux/linux-2.6/arch/mips/sni/a20r.c

   1 /*
   2  * A20R specific code
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15
  16 #include <asm/sni.h>
  17 #include <asm/time.h>
  18 #include <asm/ds1216.h>
  19
  20 #define PORT(_base,_irq)                                \
  21         {                                               \
  22                 .iobase         = _base,                \
  23                 .irq            = _irq,                 \
  24                 .uartclk        = 1843200,              \
  25                 .iotype         = UPIO_PORT,            \
  26                 .flags          = UPF_BOOT_AUTOCONF,    \
  27         }
  28
  29 static struct plat_serial8250_port a20r_data[] = {
  30         PORT(0x3f8, 4),
  31         PORT(0x2f8, 3),
  32         { },
  33 };
  34
  35 static struct platform_device a20r_serial8250_device = {
  36         .name                   = "serial8250",
  37         .id                     = PLAT8250_DEV_PLATFORM,
  38         .dev                    = {
  39                 .platform_data  = a20r_data,
  40         },
  41 };
  42
  43 static struct resource snirm_82596_rsrc[] = {
  44         {
  45                 .start = 0xb8000000,
  46                 .end   = 0xb8000004,
  47                 .flags = IORESOURCE_MEM
  48         },
  49         {
  50                 .start = 0xb8010000,
  51                 .end   = 0xb8010004,
  52                 .flags = IORESOURCE_MEM
  53         },
  54         {
  55                 .start = 0xbff00000,
  56                 .end   = 0xbff00020,
  57                 .flags = IORESOURCE_MEM
  58         },
  59         {
  60                 .start = 22,
  61                 .end   = 22,
  62                 .flags = IORESOURCE_IRQ
  63         },
  64         {
  65                 .flags = 0x01                /* 16bit mpu port access */
  66         }
  67 };
  68
  69 static struct platform_device snirm_82596_pdev = {
  70         .name           = "snirm_82596",
  71         .num_resources  = ARRAY_SIZE(snirm_82596_rsrc),
  72         .resource       = snirm_82596_rsrc
  73 };
  74
  75 static struct resource snirm_53c710_rsrc[] = {
  76         {
  77                 .start = 0xb9000000,
  78                 .end   = 0xb90fffff,
  79                 .flags = IORESOURCE_MEM
  80         },
  81         {
  82                 .start = 19,
  83                 .end   = 19,
  84                 .flags = IORESOURCE_IRQ
  85         }
  86 };
  87
  88 static struct platform_device snirm_53c710_pdev = {
  89         .name           = "snirm_53c710",
  90         .num_resources  = ARRAY_SIZE(snirm_53c710_rsrc),
  91         .resource       = snirm_53c710_rsrc
  92 };
  93
  94 static struct resource sc26xx_rsrc[] = {
  95         {
  96                 .start = 0xbc070000,
  97                 .end   = 0xbc0700ff,
  98                 .flags = IORESOURCE_MEM
  99         },
 100         {
 101                 .start = 20,
 102                 .end   = 20,
 103                 .flags = IORESOURCE_IRQ
 104         }
 105 };
 106
 107 static struct platform_device sc26xx_pdev = {
 108         .name           = "SC26xx",
 109         .num_resources  = ARRAY_SIZE(sc26xx_rsrc),
 110         .resource       = sc26xx_rsrc
 111 };
 112
 113 static u32 a20r_ack_hwint(void)
 114 {
 115         u32 status = read_c0_status();
 116
 117         write_c0_status (status | 0x00010000);
 118         asm volatile(
 119         "       .set    push                    \n"
 120         "       .set    noat                    \n"
 121         "       .set    noreorder               \n"
 122         "       lw      $1, 0(%0)               \n"
 123         "       sb      $0, 0(%1)               \n"
 124         "       sync                            \n"
 125         "       lb      %1, 0(%1)               \n"
 126         "       b       1f                      \n"
 127         "       ori     %1, $1, 2               \n"
 128         "       .align  8                       \n"
 129         "1:                                     \n"
 130         "       nop                             \n"
 131         "       sw      %1, 0(%0)               \n"
 132         "       sync                            \n"
 133         "       li      %1, 0x20                \n"
 134         "2:                                     \n"
 135         "       nop                             \n"
 136         "       bnez    %1,2b                   \n"
 137         "       addiu   %1, -1                  \n"
 138         "       sw      $1, 0(%0)               \n"
 139         "       sync                            \n"
 140                 ".set   pop                     \n"
 141         :
 142         : "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
 143         write_c0_status(status);
 144
 145         return status;
 146 }
 147
 148 static inline void unmask_a20r_irq(unsigned int irq)
 149 {
 150         set_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE));
 151         irq_enable_hazard();
 152 }
 153
 154 static inline void mask_a20r_irq(unsigned int irq)
 155 {
 156         clear_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE));
 157         irq_disable_hazard();
 158 }
 159
 160 static void end_a20r_irq(unsigned int irq)
 161 {
 162         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 163                 a20r_ack_hwint();
 164                 unmask_a20r_irq(irq);
 165         }
 166 }
 167
 168 static struct irq_chip a20r_irq_type = {
 169         .typename       = "A20R",
 170         .ack            = mask_a20r_irq,
 171         .mask           = mask_a20r_irq,
 172         .mask_ack       = mask_a20r_irq,
 173         .unmask         = unmask_a20r_irq,
 174         .end            = end_a20r_irq,
 175 };
 176
 177 /*
 178  * hwint 0 receive all interrupts
 179  */
 180 static void a20r_hwint(void)
 181 {
 182         u32 cause, status;
 183         int irq;
 184
 185         clear_c0_status (IE_IRQ0);
 186         status = a20r_ack_hwint();
 187         cause = read_c0_cause();
 188
 189         irq = ffs(((cause & status) >> 8) & 0xf8);
 190         if (likely(irq > 0))
 191                 do_IRQ(SNI_A20R_IRQ_BASE + irq - 1);
 192         set_c0_status(IE_IRQ0);
 193 }
 194
 195 void __init sni_a20r_irq_init(void)
 196 {
 197         int i;
 198
 199         for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
 200                 set_irq_chip(i, &a20r_irq_type);
 201         sni_hwint = a20r_hwint;
 202         change_c0_status(ST0_IM, IE_IRQ0);
 203         setup_irq (SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
 204 }
 205
 206 void sni_a20r_init(void)
 207 {
 208         ds1216_base = (volatile unsigned char *) SNI_DS1216_A20R_BASE;
 209         rtc_mips_get_time = ds1216_get_cmos_time;
 210 }
 211
 212 static int __init snirm_a20r_setup_devinit(void)
 213 {
 214         switch (sni_brd_type) {
 215         case SNI_BRD_TOWER_OASIC:
 216         case SNI_BRD_MINITOWER:
 217                 platform_device_register(&snirm_82596_pdev);
 218                 platform_device_register(&snirm_53c710_pdev);
 219                 platform_device_register(&sc26xx_pdev);
 220                 platform_device_register(&a20r_serial8250_device);
 221                 break;
 222         }
 223
 224         return 0;
 225 }
 226
 227 device_initcall(snirm_a20r_setup_devinit);