release/src-rt-6.x/linux/linux-2.6/arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/smp.h>
  24 #include <linux/mm.h>
  25 #include <linux/slab.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/errno.h>
  29 #include <asm/gdb-stub.h>
  30 #include <asm/signal.h>
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/sibyte/sb1250_regs.h>
  35 #include <asm/sibyte/sb1250_int.h>
  36 #include <asm/sibyte/sb1250_uart.h>
  37 #include <asm/sibyte/sb1250_scd.h>
  38 #include <asm/sibyte/sb1250.h>
  39
  40 /*
  41  * These are the routines that handle all the low level interrupt stuff.
  42  * Actions handled here are: initialization of the interrupt map, requesting of
  43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44  * for interrupt lines
  45  */
  46
  47
  48 static void end_sb1250_irq(unsigned int irq);
  49 static void enable_sb1250_irq(unsigned int irq);
  50 static void disable_sb1250_irq(unsigned int irq);
  51 static void ack_sb1250_irq(unsigned int irq);
  52 #ifdef CONFIG_SMP
  53 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
  54 #endif
  55
  56 #ifdef CONFIG_SIBYTE_HAS_LDT
  57 extern unsigned long ldt_eoi_space;
  58 #endif
  59
  60 #ifdef CONFIG_KGDB
  61 static int kgdb_irq;
  62
  63 /* Default to UART1 */
  64 int kgdb_port = 1;
  65 #ifdef CONFIG_SIBYTE_SB1250_DUART
  66 extern char sb1250_duart_present[];
  67 #endif
  68 #endif
  69
  70 static struct irq_chip sb1250_irq_type = {
  71         .name = "SB1250-IMR",
  72         .ack = ack_sb1250_irq,
  73         .mask = disable_sb1250_irq,
  74         .mask_ack = ack_sb1250_irq,
  75         .unmask = enable_sb1250_irq,
  76         .end = end_sb1250_irq,
  77 #ifdef CONFIG_SMP
  78         .set_affinity = sb1250_set_affinity
  79 #endif
  80 };
  81
  82 /* Store the CPU id (not the logical number) */
  83 int sb1250_irq_owner[SB1250_NR_IRQS];
  84
  85 DEFINE_SPINLOCK(sb1250_imr_lock);
  86
  87 void sb1250_mask_irq(int cpu, int irq)
  88 {
  89         unsigned long flags;
  90         u64 cur_ints;
  91
  92         spin_lock_irqsave(&sb1250_imr_lock, flags);
  93         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  94                                         R_IMR_INTERRUPT_MASK));
  95         cur_ints |= (((u64) 1) << irq);
  96         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  97                                         R_IMR_INTERRUPT_MASK));
  98         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
  99 }
 100
 101 void sb1250_unmask_irq(int cpu, int irq)
 102 {
 103         unsigned long flags;
 104         u64 cur_ints;
 105
 106         spin_lock_irqsave(&sb1250_imr_lock, flags);
 107         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 108                                         R_IMR_INTERRUPT_MASK));
 109         cur_ints &= ~(((u64) 1) << irq);
 110         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 111                                         R_IMR_INTERRUPT_MASK));
 112         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 113 }
 114
 115 #ifdef CONFIG_SMP
 116 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
 117 {
 118         int i = 0, old_cpu, cpu, int_on;
 119         u64 cur_ints;
 120         unsigned long flags;
 121
 122         i = first_cpu(mask);
 123
 124         /* Convert logical CPU to physical CPU */
 125         cpu = cpu_logical_map(i);
 126
 127         /* Protect against other affinity changers and IMR manipulation */
 128         spin_lock_irqsave(&sb1250_imr_lock, flags);
 129
 130         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 131         old_cpu = sb1250_irq_owner[irq];
 132         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 133                                         R_IMR_INTERRUPT_MASK));
 134         int_on = !(cur_ints & (((u64) 1) << irq));
 135         if (int_on) {
 136                 /* If it was on, mask it */
 137                 cur_ints |= (((u64) 1) << irq);
 138                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 139                                         R_IMR_INTERRUPT_MASK));
 140         }
 141         sb1250_irq_owner[irq] = cpu;
 142         if (int_on) {
 143                 /* unmask for the new CPU */
 144                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 145                                         R_IMR_INTERRUPT_MASK));
 146                 cur_ints &= ~(((u64) 1) << irq);
 147                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 148                                         R_IMR_INTERRUPT_MASK));
 149         }
 150         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 151 }
 152 #endif
 153
 154 /*****************************************************************************/
 155
 156 static void disable_sb1250_irq(unsigned int irq)
 157 {
 158         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 159 }
 160
 161 static void enable_sb1250_irq(unsigned int irq)
 162 {
 163         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 164 }
 165
 166
 167 static void ack_sb1250_irq(unsigned int irq)
 168 {
 169 #ifdef CONFIG_SIBYTE_HAS_LDT
 170         u64 pending;
 171
 172         /*
 173          * If the interrupt was an HT interrupt, now is the time to
 174          * clear it.  NOTE: we assume the HT bridge was set up to
 175          * deliver the interrupts to all CPUs (which makes affinity
 176          * changing easier for us)
 177          */
 178         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 179                                                     R_IMR_LDT_INTERRUPT)));
 180         pending &= ((u64)1 << (irq));
 181         if (pending) {
 182                 int i;
 183                 for (i=0; i<NR_CPUS; i++) {
 184                         int cpu;
 185 #ifdef CONFIG_SMP
 186                         cpu = cpu_logical_map(i);
 187 #else
 188                         cpu = i;
 189 #endif
 190                         /*
 191                          * Clear for all CPUs so an affinity switch
 192                          * doesn't find an old status
 193                          */
 194                         __raw_writeq(pending,
 195                                      IOADDR(A_IMR_REGISTER(cpu,
 196                                                 R_IMR_LDT_INTERRUPT_CLR)));
 197                 }
 198
 199                 /*
 200                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 201                  * Pass 2, the LDT world may be edge-triggered, but
 202                  * this EOI shouldn't hurt.  If they are
 203                  * level-sensitive, the EOI is required.
 204                  */
 205                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 206         }
 207 #endif
 208         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 209 }
 210
 211
 212 static void end_sb1250_irq(unsigned int irq)
 213 {
 214         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 215                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 216         }
 217 }
 218
 219
 220 void __init init_sb1250_irqs(void)
 221 {
 222         int i;
 223
 224         for (i = 0; i < SB1250_NR_IRQS; i++) {
 225                 set_irq_chip(i, &sb1250_irq_type);
 226                 sb1250_irq_owner[i] = 0;
 227         }
 228 }
 229
 230
 231 static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id)
 232 {
 233         return IRQ_NONE;
 234 }
 235
 236 static struct irqaction sb1250_dummy_action = {
 237         .handler = sb1250_dummy_handler,
 238         .flags   = 0,
 239         .mask    = CPU_MASK_NONE,
 240         .name    = "sb1250-private",
 241         .next    = NULL,
 242         .dev_id  = 0
 243 };
 244
 245 int sb1250_steal_irq(int irq)
 246 {
 247         struct irq_desc *desc = irq_desc + irq;
 248         unsigned long flags;
 249         int retval = 0;
 250
 251         if (irq >= SB1250_NR_IRQS)
 252                 return -EINVAL;
 253
 254         spin_lock_irqsave(&desc->lock,flags);
 255         /* Don't allow sharing at all for these */
 256         if (desc->action != NULL)
 257                 retval = -EBUSY;
 258         else {
 259                 desc->action = &sb1250_dummy_action;
 260                 desc->depth = 0;
 261         }
 262         spin_unlock_irqrestore(&desc->lock,flags);
 263         return 0;
 264 }
 265
 266 /*
 267  *  arch_init_irq is called early in the boot sequence from init/main.c via
 268  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 269  *  installing the handler that will be responsible for dispatching interrupts
 270  *  to the "right" place.
 271  */
 272 /*
 273  * For now, map all interrupts to IP[2].  We could save
 274  * some cycles by parceling out system interrupts to different
 275  * IP lines, but keep it simple for bringup.  We'll also direct
 276  * all interrupts to a single CPU; we should probably route
 277  * PCI and LDT to one cpu and everything else to the other
 278  * to balance the load a bit.
 279  *
 280  * On the second cpu, everything is set to IP5, which is
 281  * ignored, EXCEPT the mailbox interrupt.  That one is
 282  * set to IP[2] so it is handled.  This is needed so we
 283  * can do cross-cpu function calls, as requred by SMP
 284  */
 285
 286 #define IMR_IP2_VAL     K_INT_MAP_I0
 287 #define IMR_IP3_VAL     K_INT_MAP_I1
 288 #define IMR_IP4_VAL     K_INT_MAP_I2
 289 #define IMR_IP5_VAL     K_INT_MAP_I3
 290 #define IMR_IP6_VAL     K_INT_MAP_I4
 291
 292 void __init arch_init_irq(void)
 293 {
 294
 295         unsigned int i;
 296         u64 tmp;
 297         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 298                 STATUSF_IP1 | STATUSF_IP0;
 299
 300         /* Default everything to IP2 */
 301         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 302                 __raw_writeq(IMR_IP2_VAL,
 303                              IOADDR(A_IMR_REGISTER(0,
 304                                                    R_IMR_INTERRUPT_MAP_BASE) +
 305                                     (i << 3)));
 306                 __raw_writeq(IMR_IP2_VAL,
 307                              IOADDR(A_IMR_REGISTER(1,
 308                                                    R_IMR_INTERRUPT_MAP_BASE) +
 309                                     (i << 3)));
 310         }
 311
 312         init_sb1250_irqs();
 313
 314         /*
 315          * Map the high 16 bits of the mailbox registers to IP[3], for
 316          * inter-cpu messages
 317          */
 318         /* Was I1 */
 319         __raw_writeq(IMR_IP3_VAL,
 320                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 321                             (K_INT_MBOX_0 << 3)));
 322         __raw_writeq(IMR_IP3_VAL,
 323                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 324                             (K_INT_MBOX_0 << 3)));
 325
 326         /* Clear the mailboxes.  The firmware may leave them dirty */
 327         __raw_writeq(0xffffffffffffffffULL,
 328                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 329         __raw_writeq(0xffffffffffffffffULL,
 330                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 331
 332         /* Mask everything except the mailbox registers for both cpus */
 333         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 334         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 335         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 336
 337         sb1250_steal_irq(K_INT_MBOX_0);
 338
 339         /*
 340          * Note that the timer interrupts are also mapped, but this is
 341          * done in sb1250_time_init().  Also, the profiling driver
 342          * does its own management of IP7.
 343          */
 344
 345 #ifdef CONFIG_KGDB
 346         imask |= STATUSF_IP6;
 347 #endif
 348         /* Enable necessary IPs, disable the rest */
 349         change_c0_status(ST0_IM, imask);
 350
 351 #ifdef CONFIG_KGDB
 352         if (kgdb_flag) {
 353                 kgdb_irq = K_INT_UART_0 + kgdb_port;
 354
 355 #ifdef CONFIG_SIBYTE_SB1250_DUART
 356                 sb1250_duart_present[kgdb_port] = 0;
 357 #endif
 358                 /* Setup uart 1 settings, mapper */
 359                 __raw_writeq(M_DUART_IMR_BRK,
 360                              IOADDR(A_DUART_IMRREG(kgdb_port)));
 361
 362                 sb1250_steal_irq(kgdb_irq);
 363                 __raw_writeq(IMR_IP6_VAL,
 364                              IOADDR(A_IMR_REGISTER(0,
 365                                                    R_IMR_INTERRUPT_MAP_BASE) +
 366                                     (kgdb_irq << 3)));
 367                 sb1250_unmask_irq(0, kgdb_irq);
 368         }
 369 #endif
 370 }
 371
 372 #ifdef CONFIG_KGDB
 373
 374 #include <linux/delay.h>
 375
 376 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 377 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 378
 379 static void sb1250_kgdb_interrupt(void)
 380 {
 381         /*
 382          * Clear break-change status (allow some time for the remote
 383          * host to stop the break, since we would see another
 384          * interrupt on the end-of-break too)
 385          */
 386         kstat_this_cpu.irqs[kgdb_irq]++;
 387         mdelay(500);
 388         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 389                                 M_DUART_RX_EN | M_DUART_TX_EN);
 390         set_async_breakpoint(&get_irq_regs()->cp0_epc);
 391 }
 392
 393 #endif  /* CONFIG_KGDB */
 394
 395 extern void sb1250_timer_interrupt(void);
 396 extern void sb1250_mailbox_interrupt(void);
 397
 398 asmlinkage void plat_irq_dispatch(void)
 399 {
 400         unsigned int pending;
 401
 402 #ifdef CONFIG_SIBYTE_SB1250_PROF
 403         /* Set compare to count to silence count/compare timer interrupts */
 404         write_c0_compare(read_c0_count());
 405 #endif
 406
 407         /*
 408          * What a pain. We have to be really careful saving the upper 32 bits
 409          * of any * register across function calls if we don't want them
 410          * trashed--since were running in -o32, the calling routing never saves
 411          * the full 64 bits of a register across a function call.  Being the
 412          * interrupt handler, we're guaranteed that interrupts are disabled
 413          * during this code so we don't have to worry about random interrupts
 414          * blasting the high 32 bits.
 415          */
 416
 417         pending = read_c0_cause() & read_c0_status() & ST0_IM;
 418
 419 #ifdef CONFIG_SIBYTE_SB1250_PROF
 420         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
 421                 sbprof_cpu_intr();
 422         else
 423 #endif
 424
 425         if (pending & CAUSEF_IP4)
 426                 sb1250_timer_interrupt();
 427
 428 #ifdef CONFIG_SMP
 429         else if (pending & CAUSEF_IP3)
 430                 sb1250_mailbox_interrupt();
 431 #endif
 432
 433 #ifdef CONFIG_KGDB
 434         else if (pending & CAUSEF_IP6)                  /* KGDB (uart 1) */
 435                 sb1250_kgdb_interrupt();
 436 #endif
 437
 438         else if (pending & CAUSEF_IP2) {
 439                 unsigned long long mask;
 440
 441                 /*
 442                  * Default...we've hit an IP[2] interrupt, which means we've
 443                  * got to check the 1250 interrupt registers to figure out what
 444                  * to do.  Need to detect which CPU we're on, now that
 445                  * smp_affinity is supported.
 446                  */
 447                 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
 448                                               R_IMR_INTERRUPT_STATUS_BASE)));
 449                 if (mask)
 450                         do_IRQ(fls64(mask) - 1);
 451                 else
 452                         spurious_interrupt();
 453         } else
 454                 spurious_interrupt();
 455 }