release/src-rt-6.x/linux/linux-2.6/arch/mips/mm/tlb-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
   8  * Carsten Langgaard, carstenl@mips.com
   9  * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/mm.h>
  14
  15 #include <asm/cpu.h>
  16 #include <asm/bootinfo.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/system.h>
  20
  21 extern void build_tlb_refill_handler(void);
  22
  23 /*
  24  * Make sure all entries differ.  If they're not different
  25  * MIPS32 will take revenge ...
  26  */
  27 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
  28
  29 /* Atomicity and interruptability */
  30 #ifdef CONFIG_MIPS_MT_SMTC
  31
  32 #include <asm/smtc.h>
  33 #include <asm/mipsmtregs.h>
  34
  35 #define ENTER_CRITICAL(flags) \
  36         { \
  37         unsigned int mvpflags; \
  38         local_irq_save(flags);\
  39         mvpflags = dvpe()
  40 #define EXIT_CRITICAL(flags) \
  41         evpe(mvpflags); \
  42         local_irq_restore(flags); \
  43         }
  44 #else
  45
  46 #define ENTER_CRITICAL(flags) local_irq_save(flags)
  47 #define EXIT_CRITICAL(flags) local_irq_restore(flags)
  48
  49 #endif /* CONFIG_MIPS_MT_SMTC */
  50
  51 void local_flush_tlb_all(void)
  52 {
  53         unsigned long flags;
  54         unsigned long old_ctx;
  55         int entry;
  56
  57         ENTER_CRITICAL(flags);
  58         /* Save old context and create impossible VPN2 value */
  59         old_ctx = read_c0_entryhi();
  60         write_c0_entrylo0(0);
  61         write_c0_entrylo1(0);
  62
  63         entry = read_c0_wired();
  64
  65         /* Blast 'em all away. */
  66         while (entry < current_cpu_data.tlbsize) {
  67                 /* Make sure all entries differ. */
  68                 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
  69                 write_c0_index(entry);
  70                 mtc0_tlbw_hazard();
  71                 tlb_write_indexed();
  72                 entry++;
  73         }
  74         tlbw_use_hazard();
  75         write_c0_entryhi(old_ctx);
  76         EXIT_CRITICAL(flags);
  77 }
  78
  79 /* All entries common to a mm share an asid.  To effectively flush
  80    these entries, we just bump the asid. */
  81 void local_flush_tlb_mm(struct mm_struct *mm)
  82 {
  83         int cpu;
  84
  85         preempt_disable();
  86
  87         cpu = smp_processor_id();
  88
  89         if (cpu_context(cpu, mm) != 0) {
  90                 drop_mmu_context(mm, cpu);
  91         }
  92
  93         preempt_enable();
  94 }
  95
  96 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
  97         unsigned long end)
  98 {
  99         struct mm_struct *mm = vma->vm_mm;
 100         int cpu = smp_processor_id();
 101
 102         if (cpu_context(cpu, mm) != 0) {
 103                 unsigned long size, flags;
 104
 105                 ENTER_CRITICAL(flags);
 106                 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 107                 size = (size + 1) >> 1;
 108                 if (size <= current_cpu_data.tlbsize/2) {
 109                         int oldpid = read_c0_entryhi();
 110                         int newpid = cpu_asid(cpu, mm);
 111
 112                         start &= (PAGE_MASK << 1);
 113                         end += ((PAGE_SIZE << 1) - 1);
 114                         end &= (PAGE_MASK << 1);
 115                         while (start < end) {
 116                                 int idx;
 117
 118                                 write_c0_entryhi(start | newpid);
 119                                 start += (PAGE_SIZE << 1);
 120                                 mtc0_tlbw_hazard();
 121                                 tlb_probe();
 122                                 tlb_probe_hazard();
 123                                 idx = read_c0_index();
 124                                 write_c0_entrylo0(0);
 125                                 write_c0_entrylo1(0);
 126                                 if (idx < 0)
 127                                         continue;
 128                                 /* Make sure all entries differ. */
 129                                 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 130                                 mtc0_tlbw_hazard();
 131                                 tlb_write_indexed();
 132                         }
 133                         tlbw_use_hazard();
 134                         write_c0_entryhi(oldpid);
 135                 } else {
 136                         drop_mmu_context(mm, cpu);
 137                 }
 138                 EXIT_CRITICAL(flags);
 139         }
 140 }
 141
 142 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 143 {
 144         unsigned long size, flags;
 145
 146         ENTER_CRITICAL(flags);
 147         size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 148         size = (size + 1) >> 1;
 149         if (size <= current_cpu_data.tlbsize / 2) {
 150                 int pid = read_c0_entryhi();
 151
 152                 start &= (PAGE_MASK << 1);
 153                 end += ((PAGE_SIZE << 1) - 1);
 154                 end &= (PAGE_MASK << 1);
 155
 156                 while (start < end) {
 157                         int idx;
 158
 159                         write_c0_entryhi(start);
 160                         start += (PAGE_SIZE << 1);
 161                         mtc0_tlbw_hazard();
 162                         tlb_probe();
 163                         tlb_probe_hazard();
 164                         idx = read_c0_index();
 165                         write_c0_entrylo0(0);
 166                         write_c0_entrylo1(0);
 167                         if (idx < 0)
 168                                 continue;
 169                         /* Make sure all entries differ. */
 170                         write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 171                         mtc0_tlbw_hazard();
 172                         tlb_write_indexed();
 173                 }
 174                 tlbw_use_hazard();
 175                 write_c0_entryhi(pid);
 176         } else {
 177                 local_flush_tlb_all();
 178         }
 179         EXIT_CRITICAL(flags);
 180 }
 181
 182 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 183 {
 184         int cpu = smp_processor_id();
 185
 186         if (cpu_context(cpu, vma->vm_mm) != 0) {
 187                 unsigned long flags;
 188                 int oldpid, newpid, idx;
 189
 190                 newpid = cpu_asid(cpu, vma->vm_mm);
 191                 page &= (PAGE_MASK << 1);
 192                 ENTER_CRITICAL(flags);
 193                 oldpid = read_c0_entryhi();
 194                 write_c0_entryhi(page | newpid);
 195                 mtc0_tlbw_hazard();
 196                 tlb_probe();
 197                 tlb_probe_hazard();
 198                 idx = read_c0_index();
 199                 write_c0_entrylo0(0);
 200                 write_c0_entrylo1(0);
 201                 if (idx < 0)
 202                         goto finish;
 203                 /* Make sure all entries differ. */
 204                 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 205                 mtc0_tlbw_hazard();
 206                 tlb_write_indexed();
 207                 tlbw_use_hazard();
 208
 209         finish:
 210                 write_c0_entryhi(oldpid);
 211                 EXIT_CRITICAL(flags);
 212         }
 213 }
 214
 215 /*
 216  * This one is only used for pages with the global bit set so we don't care
 217  * much about the ASID.
 218  */
 219 void local_flush_tlb_one(unsigned long page)
 220 {
 221         unsigned long flags;
 222         int oldpid, idx;
 223
 224         ENTER_CRITICAL(flags);
 225         oldpid = read_c0_entryhi();
 226         page &= (PAGE_MASK << 1);
 227         write_c0_entryhi(page);
 228         mtc0_tlbw_hazard();
 229         tlb_probe();
 230         tlb_probe_hazard();
 231         idx = read_c0_index();
 232         write_c0_entrylo0(0);
 233         write_c0_entrylo1(0);
 234         if (idx >= 0) {
 235                 /* Make sure all entries differ. */
 236                 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 237                 mtc0_tlbw_hazard();
 238                 tlb_write_indexed();
 239                 tlbw_use_hazard();
 240         }
 241         write_c0_entryhi(oldpid);
 242
 243         EXIT_CRITICAL(flags);
 244 }
 245
 246 /*
 247  * We will need multiple versions of update_mmu_cache(), one that just
 248  * updates the TLB with the new pte(s), and another which also checks
 249  * for the R4k "end of page" hardware bug and does the needy.
 250  */
 251 void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 252 {
 253         unsigned long flags;
 254         pgd_t *pgdp;
 255         pud_t *pudp;
 256         pmd_t *pmdp;
 257         pte_t *ptep;
 258         int idx, pid;
 259
 260         /*
 261          * Handle debugger faulting in for debugee.
 262          */
 263         if (current->active_mm != vma->vm_mm)
 264                 return;
 265
 266         ENTER_CRITICAL(flags);
 267
 268         pid = read_c0_entryhi() & ASID_MASK;
 269         address &= (PAGE_MASK << 1);
 270         write_c0_entryhi(address | pid);
 271         pgdp = pgd_offset(vma->vm_mm, address);
 272         mtc0_tlbw_hazard();
 273         tlb_probe();
 274         tlb_probe_hazard();
 275         pudp = pud_offset(pgdp, address);
 276         pmdp = pmd_offset(pudp, address);
 277         idx = read_c0_index();
 278         ptep = pte_offset_map(pmdp, address);
 279
 280 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 281         write_c0_entrylo0(ptep->pte_high);
 282         ptep++;
 283         write_c0_entrylo1(ptep->pte_high);
 284 #else
 285         write_c0_entrylo0(pte_val(*ptep++) >> 6);
 286         write_c0_entrylo1(pte_val(*ptep) >> 6);
 287 #endif
 288         mtc0_tlbw_hazard();
 289         if (idx < 0)
 290                 tlb_write_random();
 291         else
 292                 tlb_write_indexed();
 293         tlbw_use_hazard();
 294         EXIT_CRITICAL(flags);
 295 }
 296
 297 #if 0
 298 static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
 299                                        unsigned long address, pte_t pte)
 300 {
 301         unsigned long flags;
 302         unsigned int asid;
 303         pgd_t *pgdp;
 304         pmd_t *pmdp;
 305         pte_t *ptep;
 306         int idx;
 307
 308         ENTER_CRITICAL(flags);
 309         address &= (PAGE_MASK << 1);
 310         asid = read_c0_entryhi() & ASID_MASK;
 311         write_c0_entryhi(address | asid);
 312         pgdp = pgd_offset(vma->vm_mm, address);
 313         mtc0_tlbw_hazard();
 314         tlb_probe();
 315         tlb_probe_hazard();
 316         pmdp = pmd_offset(pgdp, address);
 317         idx = read_c0_index();
 318         ptep = pte_offset_map(pmdp, address);
 319         write_c0_entrylo0(pte_val(*ptep++) >> 6);
 320         write_c0_entrylo1(pte_val(*ptep) >> 6);
 321         mtc0_tlbw_hazard();
 322         if (idx < 0)
 323                 tlb_write_random();
 324         else
 325                 tlb_write_indexed();
 326         tlbw_use_hazard();
 327         EXIT_CRITICAL(flags);
 328 }
 329 #endif
 330
 331 void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 332         unsigned long entryhi, unsigned long pagemask)
 333 {
 334         unsigned long flags;
 335         unsigned long wired;
 336         unsigned long old_pagemask;
 337         unsigned long old_ctx;
 338
 339         ENTER_CRITICAL(flags);
 340         /* Save old context and create impossible VPN2 value */
 341         old_ctx = read_c0_entryhi();
 342         old_pagemask = read_c0_pagemask();
 343         wired = read_c0_wired();
 344         write_c0_wired(wired + 1);
 345         write_c0_index(wired);
 346         tlbw_use_hazard();      /* What is the hazard here? */
 347         write_c0_pagemask(pagemask);
 348         write_c0_entryhi(entryhi);
 349         write_c0_entrylo0(entrylo0);
 350         write_c0_entrylo1(entrylo1);
 351         mtc0_tlbw_hazard();
 352         tlb_write_indexed();
 353         tlbw_use_hazard();
 354
 355         write_c0_entryhi(old_ctx);
 356         tlbw_use_hazard();      /* What is the hazard here? */
 357         write_c0_pagemask(old_pagemask);
 358         local_flush_tlb_all();
 359         EXIT_CRITICAL(flags);
 360 }
 361
 362 /*
 363  * Used for loading TLB entries before trap_init() has started, when we
 364  * don't actually want to add a wired entry which remains throughout the
 365  * lifetime of the system
 366  */
 367
 368 static int temp_tlb_entry __cpuinitdata;
 369
 370 __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 371                                unsigned long entryhi, unsigned long pagemask)
 372 {
 373         int ret = 0;
 374         unsigned long flags;
 375         unsigned long wired;
 376         unsigned long old_pagemask;
 377         unsigned long old_ctx;
 378
 379         ENTER_CRITICAL(flags);
 380         /* Save old context and create impossible VPN2 value */
 381         old_ctx = read_c0_entryhi();
 382         old_pagemask = read_c0_pagemask();
 383         wired = read_c0_wired();
 384         if (--temp_tlb_entry < wired) {
 385                 printk(KERN_WARNING
 386                        "No TLB space left for add_temporary_entry\n");
 387                 ret = -ENOSPC;
 388                 goto out;
 389         }
 390
 391         write_c0_index(temp_tlb_entry);
 392         write_c0_pagemask(pagemask);
 393         write_c0_entryhi(entryhi);
 394         write_c0_entrylo0(entrylo0);
 395         write_c0_entrylo1(entrylo1);
 396         mtc0_tlbw_hazard();
 397         tlb_write_indexed();
 398         tlbw_use_hazard();
 399
 400         write_c0_entryhi(old_ctx);
 401         write_c0_pagemask(old_pagemask);
 402 out:
 403         EXIT_CRITICAL(flags);
 404         return ret;
 405 }
 406
 407 static void __cpuinit probe_tlb(unsigned long config)
 408 {
 409         struct cpuinfo_mips *c = &current_cpu_data;
 410         unsigned int reg;
 411
 412         /*
 413          * If this isn't a MIPS32 / MIPS64 compliant CPU.  Config 1 register
 414          * is not supported, we assume R4k style.  Cpu probing already figured
 415          * out the number of tlb entries.
 416          */
 417         if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
 418                 return;
 419 #ifdef CONFIG_MIPS_MT_SMTC
 420         /*
 421          * If TLB is shared in SMTC system, total size already
 422          * has been calculated and written into cpu_data tlbsize
 423          */
 424         if((smtc_status & SMTC_TLB_SHARED) == SMTC_TLB_SHARED)
 425                 return;
 426 #endif /* CONFIG_MIPS_MT_SMTC */
 427
 428         reg = read_c0_config1();
 429         if (!((config >> 7) & 3))
 430                 panic("No TLB present");
 431
 432         c->tlbsize = ((reg >> 25) & 0x3f) + 1;
 433 }
 434
 435 static int __cpuinitdata ntlb = 0;
 436 static int __init set_ntlb(char *str)
 437 {
 438         get_option(&str, &ntlb);
 439         return 1;
 440 }
 441
 442 __setup("ntlb=", set_ntlb);
 443
 444 void __cpuinit tlb_init(void)
 445 {
 446         unsigned int config = read_c0_config();
 447
 448         /*
 449          * You should never change this register:
 450          *   - On R4600 1.7 the tlbp never hits for pages smaller than
 451          *     the value in the c0_pagemask register.
 452          *   - The entire mm handling assumes the c0_pagemask register to
 453          *     be set to fixed-size pages.
 454          */
 455         probe_tlb(config);
 456         write_c0_pagemask(PM_DEFAULT_MASK);
 457         write_c0_wired(0);
 458         if (current_cpu_data.cputype == CPU_R10000 ||
 459             current_cpu_data.cputype == CPU_R12000 ||
 460             current_cpu_data.cputype == CPU_R14000)
 461                 write_c0_framemask(0);
 462         temp_tlb_entry = current_cpu_data.tlbsize - 1;
 463
 464         /* From this point on the ARC firmware is dead.  */
 465         local_flush_tlb_all();
 466
 467         /* Did I tell you that ARC SUCKS?  */
 468
 469         if (ntlb) {
 470                 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
 471                         int wired = current_cpu_data.tlbsize - ntlb;
 472                         write_c0_wired(wired);
 473                         write_c0_index(wired-1);
 474                         printk ("Restricting TLB to %d entries\n", ntlb);
 475                 } else
 476                         printk("Ignoring invalid argument ntlb=%d\n", ntlb);
 477         }
 478
 479         build_tlb_refill_handler();
 480 }