RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / arch / mips / mm / pg-r4k.c
blob7e056e9488c6814081c9711985b695e9329737d1
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 */
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/mm.h>
12 #include <linux/module.h>
13 #include <linux/proc_fs.h>
15 #include <asm/cacheops.h>
16 #include <asm/inst.h>
17 #include <asm/io.h>
18 #include <asm/page.h>
19 #include <asm/pgtable.h>
20 #include <asm/prefetch.h>
21 #include <asm/system.h>
22 #include <asm/bootinfo.h>
23 #include <asm/mipsregs.h>
24 #include <asm/mmu_context.h>
25 #include <asm/cpu.h>
26 #include <asm/war.h>
28 #define half_scache_line_size() (cpu_scache_line_size() >> 1)
29 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
30 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
34 * Maximum sizes:
36 * R4000 128 bytes S-cache: 0x58 bytes
37 * R4600 v1.7: 0x5c bytes
38 * R4600 v2.0: 0x60 bytes
39 * With prefetching, 16 byte strides 0xa0 bytes
42 static unsigned int clear_page_array[0x130 / 4];
44 void clear_page(void * page) __attribute__((alias("clear_page_array")));
46 EXPORT_SYMBOL(clear_page);
49 * Maximum sizes:
51 * R4000 128 bytes S-cache: 0x11c bytes
52 * R4600 v1.7: 0x080 bytes
53 * R4600 v2.0: 0x07c bytes
54 * With prefetching, 16 byte strides 0x0b8 bytes
56 static unsigned int copy_page_array[0x148 / 4];
58 void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
60 EXPORT_SYMBOL(copy_page);
63 * This is suboptimal for 32-bit kernels; we assume that R10000 is only used
64 * with 64-bit kernels. The prefetch offsets have been experimentally tuned
65 * an Origin 200.
67 static int pref_offset_clear __cpuinitdata = 512;
68 static int pref_offset_copy __cpuinitdata = 256;
70 static unsigned int pref_src_mode __cpuinitdata;
71 static unsigned int pref_dst_mode __cpuinitdata;
73 static int load_offset __cpuinitdata;
74 static int store_offset __cpuinitdata;
76 static unsigned int __cpuinitdata *dest, *epc;
78 static unsigned int instruction_pending;
79 static union mips_instruction delayed_mi;
81 static void __cpuinit emit_instruction(union mips_instruction mi)
83 if (instruction_pending)
84 *epc++ = delayed_mi.word;
86 instruction_pending = 1;
87 delayed_mi = mi;
90 static inline void flush_delay_slot_or_nop(void)
92 if (instruction_pending) {
93 *epc++ = delayed_mi.word;
94 instruction_pending = 0;
95 return;
98 *epc++ = 0;
101 static inline unsigned int *label(void)
103 if (instruction_pending) {
104 *epc++ = delayed_mi.word;
105 instruction_pending = 0;
108 return epc;
111 static inline void build_insn_word(unsigned int word)
113 union mips_instruction mi;
115 mi.word = word;
117 emit_instruction(mi);
120 static inline void build_nop(void)
122 build_insn_word(0); /* nop */
125 static inline void build_src_pref(int advance)
127 if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {
128 union mips_instruction mi;
130 mi.i_format.opcode = pref_op;
131 mi.i_format.rs = 5; /* $a1 */
132 mi.i_format.rt = pref_src_mode;
133 mi.i_format.simmediate = load_offset + advance;
135 emit_instruction(mi);
139 static inline void __build_load_reg(int reg)
141 union mips_instruction mi;
142 unsigned int width;
144 if (cpu_has_64bit_gp_regs) {
145 mi.i_format.opcode = ld_op;
146 width = 8;
147 } else {
148 mi.i_format.opcode = lw_op;
149 width = 4;
151 mi.i_format.rs = 5; /* $a1 */
152 mi.i_format.rt = reg; /* $reg */
153 mi.i_format.simmediate = load_offset;
155 load_offset += width;
156 emit_instruction(mi);
159 static inline void build_load_reg(int reg)
161 if (cpu_has_prefetch)
162 build_src_pref(pref_offset_copy);
164 __build_load_reg(reg);
167 static inline void build_dst_pref(int advance)
169 if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {
170 union mips_instruction mi;
172 mi.i_format.opcode = pref_op;
173 mi.i_format.rs = 4; /* $a0 */
174 mi.i_format.rt = pref_dst_mode;
175 mi.i_format.simmediate = store_offset + advance;
177 emit_instruction(mi);
181 static inline void build_cdex_s(void)
183 union mips_instruction mi;
185 if ((store_offset & (cpu_scache_line_size() - 1)))
186 return;
188 mi.c_format.opcode = cache_op;
189 mi.c_format.rs = 4; /* $a0 */
190 mi.c_format.c_op = 3; /* Create Dirty Exclusive */
191 mi.c_format.cache = 3; /* Secondary Data Cache */
192 mi.c_format.simmediate = store_offset;
194 emit_instruction(mi);
197 static inline void build_cdex_p(void)
199 union mips_instruction mi;
201 if (store_offset & (cpu_dcache_line_size() - 1))
202 return;
204 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
205 build_nop();
206 build_nop();
207 build_nop();
208 build_nop();
211 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
212 build_insn_word(0x8c200000); /* lw $zero, ($at) */
214 mi.c_format.opcode = cache_op;
215 mi.c_format.rs = 4; /* $a0 */
216 mi.c_format.c_op = 3; /* Create Dirty Exclusive */
217 mi.c_format.cache = 1; /* Data Cache */
218 mi.c_format.simmediate = store_offset;
220 emit_instruction(mi);
223 static void __cpuinit __build_store_reg(int reg)
225 union mips_instruction mi;
226 unsigned int width;
228 if (cpu_has_64bit_gp_regs ||
229 (cpu_has_64bit_zero_reg && reg == 0)) {
230 mi.i_format.opcode = sd_op;
231 width = 8;
232 } else {
233 mi.i_format.opcode = sw_op;
234 width = 4;
236 mi.i_format.rs = 4; /* $a0 */
237 mi.i_format.rt = reg; /* $reg */
238 mi.i_format.simmediate = store_offset;
240 store_offset += width;
241 emit_instruction(mi);
244 static inline void build_store_reg(int reg)
246 int pref_off = cpu_has_prefetch ?
247 (reg ? pref_offset_copy : pref_offset_clear) : 0;
248 if (pref_off)
249 build_dst_pref(pref_off);
250 else if (cpu_has_cache_cdex_s)
251 build_cdex_s();
252 else if (cpu_has_cache_cdex_p)
253 build_cdex_p();
255 __build_store_reg(reg);
258 static inline void build_addiu_a2_a0(unsigned long offset)
260 union mips_instruction mi;
262 BUG_ON(offset > 0x7fff);
264 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
265 mi.i_format.rs = 4; /* $a0 */
266 mi.i_format.rt = 6; /* $a2 */
267 mi.i_format.simmediate = offset;
269 emit_instruction(mi);
272 static inline void build_addiu_a2(unsigned long offset)
274 union mips_instruction mi;
276 BUG_ON(offset > 0x7fff);
278 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
279 mi.i_format.rs = 6; /* $a2 */
280 mi.i_format.rt = 6; /* $a2 */
281 mi.i_format.simmediate = offset;
283 emit_instruction(mi);
286 static inline void build_addiu_a1(unsigned long offset)
288 union mips_instruction mi;
290 BUG_ON(offset > 0x7fff);
292 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
293 mi.i_format.rs = 5; /* $a1 */
294 mi.i_format.rt = 5; /* $a1 */
295 mi.i_format.simmediate = offset;
297 load_offset -= offset;
299 emit_instruction(mi);
302 static inline void build_addiu_a0(unsigned long offset)
304 union mips_instruction mi;
306 BUG_ON(offset > 0x7fff);
308 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
309 mi.i_format.rs = 4; /* $a0 */
310 mi.i_format.rt = 4; /* $a0 */
311 mi.i_format.simmediate = offset;
313 store_offset -= offset;
315 emit_instruction(mi);
318 static inline void build_bne(unsigned int *dest)
320 union mips_instruction mi;
322 mi.i_format.opcode = bne_op;
323 mi.i_format.rs = 6; /* $a2 */
324 mi.i_format.rt = 4; /* $a0 */
325 mi.i_format.simmediate = dest - epc - 1;
327 *epc++ = mi.word;
328 flush_delay_slot_or_nop();
331 static inline void build_jr_ra(void)
333 union mips_instruction mi;
335 mi.r_format.opcode = spec_op;
336 mi.r_format.rs = 31;
337 mi.r_format.rt = 0;
338 mi.r_format.rd = 0;
339 mi.r_format.re = 0;
340 mi.r_format.func = jr_op;
342 *epc++ = mi.word;
343 flush_delay_slot_or_nop();
346 void __cpuinit build_clear_page(void)
348 unsigned int loop_start;
349 unsigned long off;
351 epc = (unsigned int *) &clear_page_array;
352 instruction_pending = 0;
353 store_offset = 0;
355 if (cpu_has_prefetch) {
356 switch (current_cpu_data.cputype) {
357 case CPU_TX49XX:
358 /* TX49 supports only Pref_Load */
359 pref_offset_clear = 0;
360 pref_offset_copy = 0;
361 break;
363 case CPU_RM9000:
365 * As a workaround for erratum G105 which make the
366 * PrepareForStore hint unusable we fall back to
367 * StoreRetained on the RM9000. Once it is known which
368 * versions of the RM9000 we'll be able to condition-
369 * alize this.
372 case CPU_R10000:
373 case CPU_R12000:
374 case CPU_R14000:
375 pref_src_mode = Pref_LoadStreamed;
376 pref_dst_mode = Pref_StoreStreamed;
377 break;
379 default:
380 pref_src_mode = Pref_LoadStreamed;
381 pref_dst_mode = Pref_PrepareForStore;
382 break;
386 off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0);
387 if (off > 0x7fff) {
388 build_addiu_a2_a0(off >> 1);
389 build_addiu_a2(off >> 1);
390 } else
391 build_addiu_a2_a0(off);
393 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
394 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
396 dest = label();
397 do {
398 build_store_reg(0);
399 build_store_reg(0);
400 build_store_reg(0);
401 build_store_reg(0);
402 } while (store_offset < half_scache_line_size());
403 build_addiu_a0(2 * store_offset);
404 loop_start = store_offset;
405 do {
406 build_store_reg(0);
407 build_store_reg(0);
408 build_store_reg(0);
409 build_store_reg(0);
410 } while ((store_offset - loop_start) < half_scache_line_size());
411 build_bne(dest);
413 if (cpu_has_prefetch && pref_offset_clear) {
414 build_addiu_a2_a0(pref_offset_clear);
415 dest = label();
416 loop_start = store_offset;
417 do {
418 __build_store_reg(0);
419 __build_store_reg(0);
420 __build_store_reg(0);
421 __build_store_reg(0);
422 } while ((store_offset - loop_start) < half_scache_line_size());
423 build_addiu_a0(2 * store_offset);
424 loop_start = store_offset;
425 do {
426 __build_store_reg(0);
427 __build_store_reg(0);
428 __build_store_reg(0);
429 __build_store_reg(0);
430 } while ((store_offset - loop_start) < half_scache_line_size());
431 build_bne(dest);
434 build_jr_ra();
436 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
439 void __cpuinit build_copy_page(void)
441 unsigned int loop_start;
442 unsigned long off;
444 epc = (unsigned int *) &copy_page_array;
445 store_offset = load_offset = 0;
446 instruction_pending = 0;
448 off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0);
449 if (off > 0x7fff) {
450 build_addiu_a2_a0(off >> 1);
451 build_addiu_a2(off >> 1);
452 } else
453 build_addiu_a2_a0(off);
455 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
456 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
458 dest = label();
459 loop_start = store_offset;
460 do {
461 build_load_reg( 8);
462 build_load_reg( 9);
463 build_load_reg(10);
464 build_load_reg(11);
465 build_store_reg( 8);
466 build_store_reg( 9);
467 build_store_reg(10);
468 build_store_reg(11);
469 } while ((store_offset - loop_start) < half_scache_line_size());
470 build_addiu_a0(2 * store_offset);
471 build_addiu_a1(2 * load_offset);
472 loop_start = store_offset;
473 do {
474 build_load_reg( 8);
475 build_load_reg( 9);
476 build_load_reg(10);
477 build_load_reg(11);
478 build_store_reg( 8);
479 build_store_reg( 9);
480 build_store_reg(10);
481 build_store_reg(11);
482 } while ((store_offset - loop_start) < half_scache_line_size());
483 build_bne(dest);
485 if (cpu_has_prefetch && pref_offset_copy) {
486 build_addiu_a2_a0(pref_offset_copy);
487 dest = label();
488 loop_start = store_offset;
489 do {
490 __build_load_reg( 8);
491 __build_load_reg( 9);
492 __build_load_reg(10);
493 __build_load_reg(11);
494 __build_store_reg( 8);
495 __build_store_reg( 9);
496 __build_store_reg(10);
497 __build_store_reg(11);
498 } while ((store_offset - loop_start) < half_scache_line_size());
499 build_addiu_a0(2 * store_offset);
500 build_addiu_a1(2 * load_offset);
501 loop_start = store_offset;
502 do {
503 __build_load_reg( 8);
504 __build_load_reg( 9);
505 __build_load_reg(10);
506 __build_load_reg(11);
507 __build_store_reg( 8);
508 __build_store_reg( 9);
509 __build_store_reg(10);
510 __build_store_reg(11);
511 } while ((store_offset - loop_start) < half_scache_line_size());
512 build_bne(dest);
515 build_jr_ra();
517 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));