2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/signal.h>
12 #include <asm/branch.h>
14 #include <asm/cpu-features.h>
17 #include <asm/ptrace.h>
18 #include <asm/uaccess.h>
21 * Compute the return address and do emulate branch simulation, if required.
23 int __compute_return_epc(struct pt_regs
*regs
)
25 unsigned int *addr
, bit
, fcr31
, dspcontrol
;
27 union mips_instruction insn
;
34 * Read the instruction
36 addr
= (unsigned int *) epc
;
37 if (__get_user(insn
.word
, addr
)) {
38 force_sig(SIGSEGV
, current
);
42 switch (insn
.i_format
.opcode
) {
44 * jr and jalr are in r_format format.
47 switch (insn
.r_format
.func
) {
49 regs
->regs
[insn
.r_format
.rd
] = epc
+ 8;
52 regs
->cp0_epc
= regs
->regs
[insn
.r_format
.rs
];
58 * This group contains:
59 * bltz_op, bgez_op, bltzl_op, bgezl_op,
60 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
63 switch (insn
.i_format
.rt
) {
66 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
67 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
75 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
76 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
84 regs
->regs
[31] = epc
+ 8;
85 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
86 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
94 regs
->regs
[31] = epc
+ 8;
95 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
96 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
105 dspcontrol
= rddsp(0x01);
107 if (dspcontrol
>= 32) {
108 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
117 * These are unconditional and in j_format.
120 regs
->regs
[31] = regs
->cp0_epc
+ 8;
125 epc
|= (insn
.j_format
.target
<< 2);
130 * These are conditional and in i_format.
134 if (regs
->regs
[insn
.i_format
.rs
] ==
135 regs
->regs
[insn
.i_format
.rt
])
136 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
144 if (regs
->regs
[insn
.i_format
.rs
] !=
145 regs
->regs
[insn
.i_format
.rt
])
146 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
152 case blez_op
: /* not really i_format */
154 /* rt field assumed to be zero */
155 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
156 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
164 /* rt field assumed to be zero */
165 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
166 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
173 * And now the FPA/cp1 branch instructions.
178 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
180 fcr31
= current
->thread
.fpu
.fcr31
;
183 bit
= (insn
.i_format
.rt
>> 2);
186 switch (insn
.i_format
.rt
& 3) {
189 if (~fcr31
& (1 << bit
))
190 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
198 if (fcr31
& (1 << bit
))
199 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
211 printk("%s: unaligned epc - sending SIGBUS.\n", current
->comm
);
212 force_sig(SIGBUS
, current
);
216 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current
->comm
);
217 force_sig(SIGBUS
, current
);