release/src-rt-6.x/linux/linux-2.6/arch/cris/arch-v10/kernel/time.c

   1 /* $Id: time.c,v 1.5 2004/09/29 06:12:46 starvik Exp $
   2  *
   3  *  linux/arch/cris/arch-v10/kernel/time.c
   4  *
   5  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   6  *  Copyright (C) 1999-2002 Axis Communications AB
   7  *
   8  */
   9
  10 #include <linux/timex.h>
  11 #include <linux/time.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/swap.h>
  15 #include <linux/sched.h>
  16 #include <linux/init.h>
  17 #include <asm/arch/svinto.h>
  18 #include <asm/types.h>
  19 #include <asm/signal.h>
  20 #include <asm/io.h>
  21 #include <asm/delay.h>
  22 #include <asm/rtc.h>
  23
  24 /* define this if you need to use print_timestamp */
  25 /* it will make jiffies at 96 hz instead of 100 hz though */
  26 #undef USE_CASCADE_TIMERS
  27
  28 extern void update_xtime_from_cmos(void);
  29 extern int set_rtc_mmss(unsigned long nowtime);
  30 extern int setup_irq(int, struct irqaction *);
  31 extern int have_rtc;
  32
  33 unsigned long get_ns_in_jiffie(void)
  34 {
  35         unsigned char timer_count, t1;
  36         unsigned short presc_count;
  37         unsigned long ns;
  38         unsigned long flags;
  39
  40         local_irq_save(flags);
  41         timer_count = *R_TIMER0_DATA;
  42         presc_count = *R_TIM_PRESC_STATUS;
  43         /* presc_count might be wrapped */
  44         t1 = *R_TIMER0_DATA;
  45
  46         if (timer_count != t1){
  47                 /* it wrapped, read prescaler again...  */
  48                 presc_count = *R_TIM_PRESC_STATUS;
  49                 timer_count = t1;
  50         }
  51         local_irq_restore(flags);
  52         if (presc_count >= PRESCALE_VALUE/2 ){
  53                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
  54         } else {
  55                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
  56         }
  57
  58         ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
  59              ( (presc_count) * (1000000000/PRESCALE_FREQ));
  60         return ns;
  61 }
  62
  63 unsigned long do_slow_gettimeoffset(void)
  64 {
  65         unsigned long count, t1;
  66         unsigned long usec_count = 0;
  67         unsigned short presc_count;
  68
  69         static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
  70         static unsigned long jiffies_p = 0;
  71
  72         /*
  73          * cache volatile jiffies temporarily; we have IRQs turned off.
  74          */
  75         unsigned long jiffies_t;
  76
  77         /* The timer interrupt comes from Etrax timer 0. In order to get
  78          * better precision, we check the current value. It might have
  79          * underflowed already though.
  80          */
  81
  82 #ifndef CONFIG_SVINTO_SIM
  83         /* Not available in the xsim simulator. */
  84         count = *R_TIMER0_DATA;
  85         presc_count = *R_TIM_PRESC_STATUS;
  86         /* presc_count might be wrapped */
  87         t1 = *R_TIMER0_DATA;
  88         if (count != t1){
  89                 /* it wrapped, read prescaler again...  */
  90                 presc_count = *R_TIM_PRESC_STATUS;
  91                 count = t1;
  92         }
  93 #else
  94         count = 0;
  95         presc_count = 0;
  96 #endif
  97
  98         jiffies_t = jiffies;
  99
 100         /*
 101          * avoiding timer inconsistencies (they are rare, but they happen)...
 102          * there are one problem that must be avoided here:
 103          *  1. the timer counter underflows
 104          */
 105         if( jiffies_t == jiffies_p ) {
 106                 if( count > count_p ) {
 107                         /* Timer wrapped, use new count and prescale
 108                          * increase the time corresponding to one jiffie
 109                          */
 110                         usec_count = 1000000/HZ;
 111                 }
 112         } else
 113                 jiffies_p = jiffies_t;
 114         count_p = count;
 115         if (presc_count >= PRESCALE_VALUE/2 ){
 116                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
 117         } else {
 118                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
 119         }
 120         /* Convert timer value to usec */
 121         usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
 122                       (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
 123
 124         return usec_count;
 125 }
 126
 127 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 128  *
 129  * 3.10.4 Watchdog timer
 130
 131  * When the watchdog timer is started, it generates an NMI if the watchdog
 132  * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 133  * stopped after an additional 3.3 ms, the watchdog resets the chip.
 134  * The watchdog timer is stopped after reset. The watchdog timer is controlled
 135  * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 136  * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 137  * described in the table below:
 138  *
 139  *   Watchdog    Value written:
 140  *   state:      To enable:  To key:      Operation:
 141  *   --------    ----------  -------      ----------
 142  *   stopped         0         X          No effect.
 143  *   stopped         1       key_val      Start watchdog with key = key_val.
 144  *   started         0       ~key         Stop watchdog
 145  *   started         1       ~key         Restart watchdog with key = ~key.
 146  *   started         X       new_key_val  Change key to new_key_val.
 147  *
 148  * Note: '~' is the bitwise NOT operator.
 149  *
 150  */
 151
 152 /* right now, starting the watchdog is the same as resetting it */
 153 #define start_watchdog reset_watchdog
 154
 155 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 156 static int watchdog_key = 0;  /* arbitrary number */
 157 #endif
 158
 159 /* number of pages to consider "out of memory". it is normal that the memory
 160  * is used though, so put this really low.
 161  */
 162
 163 #define WATCHDOG_MIN_FREE_PAGES 8
 164
 165 void
 166 reset_watchdog(void)
 167 {
 168 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 169         /* only keep watchdog happy as long as we have memory left! */
 170         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 171                 /* reset the watchdog with the inverse of the old key */
 172                 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 173                 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 174                         IO_STATE(R_WATCHDOG, enable, start);
 175         }
 176 #endif
 177 }
 178
 179 /* stop the watchdog - we still need the correct key */
 180
 181 void
 182 stop_watchdog(void)
 183 {
 184 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 185         watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 186         *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 187                 IO_STATE(R_WATCHDOG, enable, stop);
 188 #endif
 189 }
 190
 191 /* last time the cmos clock got updated */
 192 static long last_rtc_update = 0;
 193
 194 /*
 195  * timer_interrupt() needs to keep up the real-time clock,
 196  * as well as call the "do_timer()" routine every clocktick
 197  */
 198
 199 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
 200
 201 extern void cris_do_profile(struct pt_regs *regs);
 202
 203 static inline irqreturn_t
 204 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 205 {
 206         /* acknowledge the timer irq */
 207
 208 #ifdef USE_CASCADE_TIMERS
 209         *R_TIMER_CTRL =
 210                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 211                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 212                 IO_STATE( R_TIMER_CTRL, i1, clr) |
 213                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 214                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 215                 IO_STATE( R_TIMER_CTRL, i0, clr) |
 216                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 217                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 218 #else
 219         *R_TIMER_CTRL = r_timer_ctrl_shadow |
 220                 IO_STATE(R_TIMER_CTRL, i0, clr);
 221 #endif
 222
 223         /* reset watchdog otherwise it resets us! */
 224
 225         reset_watchdog();
 226
 227         /* call the real timer interrupt handler */
 228
 229         do_timer(1);
 230
 231         cris_do_profile(regs); /* Save profiling information */
 232
 233         /*
 234          * If we have an externally synchronized Linux clock, then update
 235          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 236          * called as close as possible to 500 ms before the new second starts.
 237          *
 238          * The division here is not time critical since it will run once in
 239          * 11 minutes
 240          */
 241         if (ntp_synced() &&
 242             xtime.tv_sec > last_rtc_update + 660 &&
 243             (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 244             (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 245                 if (set_rtc_mmss(xtime.tv_sec) == 0)
 246                         last_rtc_update = xtime.tv_sec;
 247                 else
 248                         last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
 249         }
 250         return IRQ_HANDLED;
 251 }
 252
 253 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 254  * it needs to be IRQF_DISABLED to make the jiffies update work properly
 255  */
 256
 257 static struct irqaction irq2  = { timer_interrupt, IRQF_SHARED | IRQF_DISABLED,
 258                                   CPU_MASK_NONE, "timer", NULL, NULL};
 259
 260 void __init
 261 time_init(void)
 262 {
 263         /* probe for the RTC and read it if it exists
 264          * Before the RTC can be probed the loops_per_usec variable needs
 265          * to be initialized to make usleep work. A better value for
 266          * loops_per_usec is calculated by the kernel later once the
 267          * clock has started.
 268          */
 269         loops_per_usec = 50;
 270
 271         if(RTC_INIT() < 0) {
 272                 /* no RTC, start at 1980 */
 273                 xtime.tv_sec = 0;
 274                 xtime.tv_nsec = 0;
 275                 have_rtc = 0;
 276         } else {
 277                 /* get the current time */
 278                 have_rtc = 1;
 279                 update_xtime_from_cmos();
 280         }
 281
 282         /*
 283          * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
 284          * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
 285          */
 286         set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 287
 288         /* Setup the etrax timers
 289          * Base frequency is 25000 hz, divider 250 -> 100 HZ
 290          * In normal mode, we use timer0, so timer1 is free. In cascade
 291          * mode (which we sometimes use for debugging) both timers are used.
 292          * Remember that linux/timex.h contains #defines that rely on the
 293          * timer settings below (hz and divide factor) !!!
 294          */
 295
 296 #ifdef USE_CASCADE_TIMERS
 297         *R_TIMER_CTRL =
 298                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 299                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 300                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 301                 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
 302                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 303                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 304                 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
 305                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 306
 307         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 308                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 309                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 310                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 311                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 312                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 313                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 314                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 315                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 316 #else
 317         *R_TIMER_CTRL =
 318                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 319                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 320                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 321                 IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 322                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 323                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 324                 IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
 325                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 326
 327         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 328                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 329                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 330                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 331                 IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 332                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 333                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 334                 IO_STATE(R_TIMER_CTRL, tm0,       run)      |
 335                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 336
 337         *R_TIMER_PRESCALE = PRESCALE_VALUE;
 338 #endif
 339
 340         *R_IRQ_MASK0_SET =
 341                 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
 342
 343         /* now actually register the timer irq handler that calls timer_interrupt() */
 344
 345         setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 346
 347         /* enable watchdog if we should use one */
 348
 349 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 350         printk("Enabling watchdog...\n");
 351         start_watchdog();
 352
 353         /* If we use the hardware watchdog, we want to trap it as an NMI
 354            and dump registers before it resets us.  For this to happen, we
 355            must set the "m" NMI enable flag (which once set, is unset only
 356            when an NMI is taken).
 357
 358            The same goes for the external NMI, but that doesn't have any
 359            driver or infrastructure support yet.  */
 360         asm ("setf m");
 361
 362         *R_IRQ_MASK0_SET =
 363                 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
 364         *R_VECT_MASK_SET =
 365                 IO_STATE(R_VECT_MASK_SET, nmi, set);
 366 #endif
 367 }