release/src-rt-6.x/linux/linux-2.6/arch/arm/mach-s3c2412/s3c2412.c

   1 /* linux/arch/arm/mach-s3c2412/s3c2412.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://armlinux.simtec.co.uk/.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/irq.h>
  27
  28 #include <asm/hardware.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 #include <asm/arch/reset.h>
  34 #include <asm/arch/idle.h>
  35
  36 #include <asm/arch/regs-clock.h>
  37 #include <asm/arch/regs-serial.h>
  38 #include <asm/arch/regs-power.h>
  39 #include <asm/arch/regs-gpio.h>
  40 #include <asm/arch/regs-gpioj.h>
  41 #include <asm/arch/regs-dsc.h>
  42 #include <asm/arch/regs-spi.h>
  43 #include <asm/arch/regs-s3c2412.h>
  44
  45 #include <asm/plat-s3c24xx/s3c2412.h>
  46 #include <asm/plat-s3c24xx/cpu.h>
  47 #include <asm/plat-s3c24xx/devs.h>
  48 #include <asm/plat-s3c24xx/clock.h>
  49 #include <asm/plat-s3c24xx/pm.h>
  50
  51 #ifndef CONFIG_CPU_S3C2412_ONLY
  52 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
  53
  54 static inline void s3c2412_init_gpio2(void)
  55 {
  56         s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
  57 }
  58 #else
  59 #define s3c2412_init_gpio2() do { } while(0)
  60 #endif
  61
  62 /* Initial IO mappings */
  63
  64 static struct map_desc s3c2412_iodesc[] __initdata = {
  65         IODESC_ENT(CLKPWR),
  66         IODESC_ENT(LCD),
  67         IODESC_ENT(TIMER),
  68         IODESC_ENT(WATCHDOG),
  69 };
  70
  71 /* uart registration process */
  72
  73 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  74 {
  75         s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
  76
  77         /* rename devices that are s3c2412/s3c2413 specific */
  78         s3c_device_sdi.name  = "s3c2412-sdi";
  79         s3c_device_lcd.name  = "s3c2412-lcd";
  80         s3c_device_nand.name = "s3c2412-nand";
  81
  82         /* spi channel related changes, s3c2412/13 specific */
  83         s3c_device_spi0.name = "s3c2412-spi";
  84         s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
  85         s3c_device_spi1.name = "s3c2412-spi";
  86         s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
  87         s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
  88
  89 }
  90
  91 /* s3c2412_idle
  92  *
  93  * use the standard idle call by ensuring the idle mode
  94  * in power config, then issuing the idle co-processor
  95  * instruction
  96 */
  97
  98 static void s3c2412_idle(void)
  99 {
 100         unsigned long tmp;
 101
 102         /* ensure our idle mode is to go to idle */
 103
 104         tmp = __raw_readl(S3C2412_PWRCFG);
 105         tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
 106         tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
 107         __raw_writel(tmp, S3C2412_PWRCFG);
 108
 109         cpu_do_idle();
 110 }
 111
 112 static void s3c2412_hard_reset(void)
 113 {
 114         /* errata "Watch-dog/Software Reset Problem" specifies that
 115          * this reset must be done with the SYSCLK sourced from
 116          * EXTCLK instead of FOUT to avoid a glitch in the reset
 117          * mechanism.
 118          *
 119          * See the watchdog section of the S3C2412 manual for more
 120          * information on this fix.
 121          */
 122
 123         __raw_writel(0x00, S3C2412_CLKSRC);
 124         __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
 125
 126         mdelay(1);
 127 }
 128
 129 /* s3c2412_map_io
 130  *
 131  * register the standard cpu IO areas, and any passed in from the
 132  * machine specific initialisation.
 133 */
 134
 135 void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
 136 {
 137         /* move base of IO */
 138
 139         s3c2412_init_gpio2();
 140
 141         /* set our idle function */
 142
 143         s3c24xx_idle = s3c2412_idle;
 144
 145         /* set custom reset hook */
 146
 147         s3c24xx_reset_hook = s3c2412_hard_reset;
 148
 149         /* register our io-tables */
 150
 151         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
 152         iotable_init(mach_desc, mach_size);
 153 }
 154
 155 void __init s3c2412_init_clocks(int xtal)
 156 {
 157         unsigned long tmp;
 158         unsigned long fclk;
 159         unsigned long hclk;
 160         unsigned long pclk;
 161
 162         /* now we've got our machine bits initialised, work out what
 163          * clocks we've got */
 164
 165         fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
 166
 167         tmp = __raw_readl(S3C2410_CLKDIVN);
 168
 169         /* work out clock scalings */
 170
 171         hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
 172         hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
 173         pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
 174
 175         /* print brieft summary of clocks, etc */
 176
 177         printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
 178                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
 179
 180         /* initialise the clocks here, to allow other things like the
 181          * console to use them
 182          */
 183
 184         s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
 185         s3c2412_baseclk_add();
 186 }
 187
 188 /* need to register class before we actually register the device, and
 189  * we also need to ensure that it has been initialised before any of the
 190  * drivers even try to use it (even if not on an s3c2412 based system)
 191  * as a driver which may support both 2410 and 2440 may try and use it.
 192 */
 193
 194 struct sysdev_class s3c2412_sysclass = {
 195         set_kset_name("s3c2412-core"),
 196 };
 197
 198 static int __init s3c2412_core_init(void)
 199 {
 200         return sysdev_class_register(&s3c2412_sysclass);
 201 }
 202
 203 core_initcall(s3c2412_core_init);
 204
 205 static struct sys_device s3c2412_sysdev = {
 206         .cls            = &s3c2412_sysclass,
 207 };
 208
 209 int __init s3c2412_init(void)
 210 {
 211         printk("S3C2412: Initialising architecture\n");
 212
 213         return sysdev_register(&s3c2412_sysdev);
 214 }