release/src-rt-6.x/linux/linux-2.6/arch/arm/mach-iop13xx/iq81340mc.c

   1 /*
   2  * iq81340mc board support
   3  * Copyright (c) 2005-2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  */
  19 #include <linux/pci.h>
  20
  21 #include <asm/hardware.h>
  22 #include <asm/irq.h>
  23 #include <asm/mach/pci.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/arch/pci.h>
  27 #include <asm/mach/time.h>
  28 #include <asm/arch/time.h>
  29
  30 extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
  31
  32 static int __init
  33 iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
  34 {
  35         switch (idsel) {
  36         case 1:
  37                 switch (pin) {
  38                 case 1: return ATUX_INTB;
  39                 case 2: return ATUX_INTC;
  40                 case 3: return ATUX_INTD;
  41                 case 4: return ATUX_INTA;
  42                 default: return -1;
  43                 }
  44         case 2:
  45                 switch (pin) {
  46                 case 1: return ATUX_INTC;
  47                 case 2: return ATUX_INTD;
  48                 case 3: return ATUX_INTC;
  49                 case 4: return ATUX_INTD;
  50                 default: return -1;
  51                 }
  52         default: return -1;
  53         }
  54 }
  55
  56 static struct hw_pci iq81340mc_pci __initdata = {
  57         .swizzle        = pci_std_swizzle,
  58         .nr_controllers = 0,
  59         .setup          = iop13xx_pci_setup,
  60         .map_irq        = iq81340mc_pcix_map_irq,
  61         .scan           = iop13xx_scan_bus,
  62         .preinit        = iop13xx_pci_init,
  63 };
  64
  65 static int __init iq81340mc_pci_init(void)
  66 {
  67         iop13xx_atu_select(&iq81340mc_pci);
  68         pci_common_init(&iq81340mc_pci);
  69         iop13xx_map_pci_memory();
  70
  71         return 0;
  72 }
  73
  74 static void __init iq81340mc_init(void)
  75 {
  76         iop13xx_platform_init();
  77         iq81340mc_pci_init();
  78         iop13xx_add_tpmi_devices();
  79 }
  80
  81 static void __init iq81340mc_timer_init(void)
  82 {
  83         unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
  84         printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
  85         iop_init_time(bus_freq);
  86 }
  87
  88 static struct sys_timer iq81340mc_timer = {
  89        .init       = iq81340mc_timer_init,
  90        .offset     = iop_gettimeoffset,
  91 };
  92
  93 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
  94         /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
  95         .phys_io        = IOP13XX_PMMR_PHYS_MEM_BASE,
  96         .io_pg_offst    = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc,
  97         .boot_params    = 0x00000100,
  98         .map_io         = iop13xx_map_io,
  99         .init_irq       = iop13xx_init_irq,
 100         .timer          = &iq81340mc_timer,
 101         .init_machine   = iq81340mc_init,
 102 MACHINE_END