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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / include / sbchipc.h
blobd70cf52f9abd9faf3b0781009c32101820bacd08
1 /*
2 * SiliconBackplane Chipcommon core hardware definitions.
3 *
4 * The chipcommon core provides chip identification, SB control,
5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
6 * GPIO interface, extbus, and support for serial and parallel flashes.
7 *
8 * $Id: sbchipc.h 354512 2012-08-31 10:28:54Z $
9 *
10 * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
11 *
12 * Permission to use, copy, modify, and/or distribute this software for any
13 * purpose with or without fee is hereby granted, provided that the above
14 * copyright notice and this permission notice appear in all copies.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 */
24
25 #ifndef _SBCHIPC_H
26 #define _SBCHIPC_H
27
28 #ifndef _LANGUAGE_ASSEMBLY
29
30 /* cpp contortions to concatenate w/arg prescan */
31 #ifndef PAD
32 #define _PADLINE(line) pad ## line
33 #define _XSTR(line) _PADLINE(line)
34 #define PAD _XSTR(__LINE__)
35 #endif /* PAD */
36
37 typedef struct eci_prerev35 {
38 uint32 eci_output;
39 uint32 eci_control;
40 uint32 eci_inputlo;
41 uint32 eci_inputmi;
42 uint32 eci_inputhi;
43 uint32 eci_inputintpolaritylo;
44 uint32 eci_inputintpolaritymi;
45 uint32 eci_inputintpolarityhi;
46 uint32 eci_intmasklo;
47 uint32 eci_intmaskmi;
48 uint32 eci_intmaskhi;
49 uint32 eci_eventlo;
50 uint32 eci_eventmi;
51 uint32 eci_eventhi;
52 uint32 eci_eventmasklo;
53 uint32 eci_eventmaskmi;
54 uint32 eci_eventmaskhi;
55 uint32 PAD[3];
56 } eci_prerev35_t;
57
58 typedef struct eci_rev35 {
59 uint32 eci_outputlo;
60 uint32 eci_outputhi;
61 uint32 eci_controllo;
62 uint32 eci_controlhi;
63 uint32 eci_inputlo;
64 uint32 eci_inputhi;
65 uint32 eci_inputintpolaritylo;
66 uint32 eci_inputintpolarityhi;
67 uint32 eci_intmasklo;
68 uint32 eci_intmaskhi;
69 uint32 eci_eventlo;
70 uint32 eci_eventhi;
71 uint32 eci_eventmasklo;
72 uint32 eci_eventmaskhi;
73 uint32 eci_auxtx;
74 uint32 eci_auxrx;
75 uint32 eci_datatag;
76 uint32 eci_uartescvalue;
77 uint32 eci_autobaudctr;
78 uint32 eci_uartfifolevel;
79 } eci_rev35_t;
80
81 typedef struct flash_config {
82 uint32 PAD[19];
83 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */
84 uint32 flashstrconfig;
85 } flash_config_t;
86
87 typedef volatile struct {
88 uint32 chipid; /* 0x0 */
89 uint32 capabilities;
90 uint32 corecontrol; /* corerev >= 1 */
91 uint32 bist;
92
93 /* OTP */
94 uint32 otpstatus; /* 0x10, corerev >= 10 */
95 uint32 otpcontrol;
96 uint32 otpprog;
97 uint32 otplayout; /* corerev >= 23 */
98
99 /* Interrupt control */
100 uint32 intstatus; /* 0x20 */
101 uint32 intmask;
102
103 /* Chip specific regs */
104 uint32 chipcontrol; /* 0x28, rev >= 11 */
105 uint32 chipstatus; /* 0x2c, rev >= 11 */
106
107 /* Jtag Master */
108 uint32 jtagcmd; /* 0x30, rev >= 10 */
109 uint32 jtagir;
110 uint32 jtagdr;
111 uint32 jtagctrl;
112
113 /* serial flash interface registers */
114 uint32 flashcontrol; /* 0x40 */
115 uint32 flashaddress;
116 uint32 flashdata;
117 uint32 otplayoutextension; /* rev >= 35 */
118
119 /* Silicon backplane configuration broadcast control */
120 uint32 broadcastaddress; /* 0x50 */
121 uint32 broadcastdata;
122
123 /* gpio - cleared only by power-on-reset */
124 uint32 gpiopullup; /* 0x58, corerev >= 20 */
125 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
126 uint32 gpioin; /* 0x60 */
127 uint32 gpioout; /* 0x64 */
128 uint32 gpioouten; /* 0x68 */
129 uint32 gpiocontrol; /* 0x6C */
130 uint32 gpiointpolarity; /* 0x70 */
131 uint32 gpiointmask; /* 0x74 */
132
133 /* GPIO events corerev >= 11 */
134 uint32 gpioevent;
135 uint32 gpioeventintmask;
136
137 /* Watchdog timer */
138 uint32 watchdog; /* 0x80 */
139
140 /* GPIO events corerev >= 11 */
141 uint32 gpioeventintpolarity;
142
143 /* GPIO based LED powersave registers corerev >= 16 */
144 uint32 gpiotimerval; /* 0x88 */
145 uint32 gpiotimeroutmask;
146
147 /* clock control */
148 uint32 clockcontrol_n; /* 0x90 */
149 uint32 clockcontrol_sb; /* aka m0 */
150 uint32 clockcontrol_pci; /* aka m1 */
151 uint32 clockcontrol_m2; /* mii/uart/mipsref */
152 uint32 clockcontrol_m3; /* cpu */
153 uint32 clkdiv; /* corerev >= 3 */
154 uint32 gpiodebugsel; /* corerev >= 28 */
155 uint32 capabilities_ext; /* 0xac */
156
157 /* pll delay registers (corerev >= 4) */
158 uint32 pll_on_delay; /* 0xb0 */
159 uint32 fref_sel_delay;
160 uint32 slow_clk_ctl; /* 5 < corerev < 10 */
161 uint32 PAD;
162
163 /* Instaclock registers (corerev >= 10) */
164 uint32 system_clk_ctl; /* 0xc0 */
165 uint32 clkstatestretch;
166 uint32 PAD[2];
167
168 /* Indirect backplane access (corerev >= 22) */
169 uint32 bp_addrlow; /* 0xd0 */
170 uint32 bp_addrhigh;
171 uint32 bp_data;
172 uint32 PAD;
173 uint32 bp_indaccess;
174 /* SPI registers, corerev >= 37 */
175 uint32 gsioctrl;
176 uint32 gsioaddress;
177 uint32 gsiodata;
178
179 /* More clock dividers (corerev >= 32) */
180 uint32 clkdiv2;
181 /* FAB ID (corerev >= 40) */
182 uint32 otpcontrol1;
183 uint32 fabid; /* 0xf8 */
184
185 /* In AI chips, pointer to erom */
186 uint32 eromptr; /* 0xfc */
187
188 /* ExtBus control registers (corerev >= 3) */
189 uint32 pcmcia_config; /* 0x100 */
190 uint32 pcmcia_memwait;
191 uint32 pcmcia_attrwait;
192 uint32 pcmcia_iowait;
193 uint32 ide_config;
194 uint32 ide_memwait;
195 uint32 ide_attrwait;
196 uint32 ide_iowait;
197 uint32 prog_config;
198 uint32 prog_waitcount;
199 uint32 flash_config;
200 uint32 flash_waitcount;
201 uint32 SECI_config; /* 0x130 SECI configuration */
202 uint32 SECI_status;
203 uint32 SECI_statusmask;
204 uint32 SECI_rxnibchanged;
205
206 union { /* 0x140 */
207 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
208 struct eci_prerev35 lt35;
209 struct eci_rev35 ge35;
210 /* Other interfaces */
211 struct flash_config flashconf;
212 uint32 PAD[20];
213 } eci;
214
215 /* SROM interface (corerev >= 32) */
216 uint32 sromcontrol; /* 0x190 */
217 uint32 sromaddress;
218 uint32 sromdata;
219 uint32 PAD[1]; /* 0x19C */
220 /* NAND flash registers for BCM4706 (corerev = 31) */
221 uint32 nflashctrl; /* 0x1a0 */
222 uint32 nflashconf;
223 uint32 nflashcoladdr;
224 uint32 nflashrowaddr;
225 uint32 nflashdata;
226 uint32 nflashwaitcnt0; /* 0x1b4 */
227 uint32 PAD[2];
228
229 uint32 seci_uart_data; /* 0x1C0 */
230 uint32 seci_uart_bauddiv;
231 uint32 seci_uart_fcr;
232 uint32 seci_uart_lcr;
233 uint32 seci_uart_mcr;
234 uint32 seci_uart_lsr;
235 uint32 seci_uart_msr;
236 uint32 seci_uart_baudadj;
237 /* Clock control and hardware workarounds (corerev >= 20) */
238 uint32 clk_ctl_st; /* 0x1e0 */
239 uint32 hw_war;
240 uint32 PAD[70];
241
242 /* UARTs */
243 uint8 uart0data; /* 0x300 */
244 uint8 uart0imr;
245 uint8 uart0fcr;
246 uint8 uart0lcr;
247 uint8 uart0mcr;
248 uint8 uart0lsr;
249 uint8 uart0msr;
250 uint8 uart0scratch;
251 uint8 PAD[248]; /* corerev >= 1 */
252
253 uint8 uart1data; /* 0x400 */
254 uint8 uart1imr;
255 uint8 uart1fcr;
256 uint8 uart1lcr;
257 uint8 uart1mcr;
258 uint8 uart1lsr;
259 uint8 uart1msr;
260 uint8 uart1scratch;
261 uint32 PAD[126];
262
263 /* PMU registers (corerev >= 20) */
264 /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP.
265 * The CPU must read them twice, compare, and retry if different.
266 */
267 uint32 pmucontrol; /* 0x600 */
268 uint32 pmucapabilities;
269 uint32 pmustatus;
270 uint32 res_state;
271 uint32 res_pending;
272 uint32 pmutimer;
273 uint32 min_res_mask;
274 uint32 max_res_mask;
275 uint32 res_table_sel;
276 uint32 res_dep_mask;
277 uint32 res_updn_timer;
278 uint32 res_timer;
279 uint32 clkstretch;
280 uint32 pmuwatchdog;
281 uint32 gpiosel; /* 0x638, rev >= 1 */
282 uint32 gpioenable; /* 0x63c, rev >= 1 */
283 uint32 res_req_timer_sel;
284 uint32 res_req_timer;
285 uint32 res_req_mask;
286 uint32 PAD;
287 uint32 chipcontrol_addr; /* 0x650 */
288 uint32 chipcontrol_data; /* 0x654 */
289 uint32 regcontrol_addr;
290 uint32 regcontrol_data;
291 uint32 pllcontrol_addr;
292 uint32 pllcontrol_data;
293 uint32 pmustrapopt; /* 0x668, corerev >= 28 */
294 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
295 uint32 PAD[100];
296 uint16 sromotp[512]; /* 0x800 */
297 #ifdef NFLASH_SUPPORT
298 /* Nand flash MLC controller registers (corerev >= 38) */
299 uint32 nand_revision; /* 0xC00 */
300 uint32 nand_cmd_start;
301 uint32 nand_cmd_addr_x;
302 uint32 nand_cmd_addr;
303 uint32 nand_cmd_end_addr;
304 uint32 nand_cs_nand_select;
305 uint32 nand_cs_nand_xor;
306 uint32 PAD;
307 uint32 nand_spare_rd0;
308 uint32 nand_spare_rd4;
309 uint32 nand_spare_rd8;
310 uint32 nand_spare_rd12;
311 uint32 nand_spare_wr0;
312 uint32 nand_spare_wr4;
313 uint32 nand_spare_wr8;
314 uint32 nand_spare_wr12;
315 uint32 nand_acc_control;
316 uint32 PAD;
317 uint32 nand_config;
318 uint32 PAD;
319 uint32 nand_timing_1;
320 uint32 nand_timing_2;
321 uint32 nand_semaphore;
322 uint32 PAD;
323 uint32 nand_devid;
324 uint32 nand_devid_x;
325 uint32 nand_block_lock_status;
326 uint32 nand_intfc_status;
327 uint32 nand_ecc_corr_addr_x;
328 uint32 nand_ecc_corr_addr;
329 uint32 nand_ecc_unc_addr_x;
330 uint32 nand_ecc_unc_addr;
331 uint32 nand_read_error_count;
332 uint32 nand_corr_stat_threshold;
333 uint32 PAD[2];
334 uint32 nand_read_addr_x;
335 uint32 nand_read_addr;
336 uint32 nand_page_program_addr_x;
337 uint32 nand_page_program_addr;
338 uint32 nand_copy_back_addr_x;
339 uint32 nand_copy_back_addr;
340 uint32 nand_block_erase_addr_x;
341 uint32 nand_block_erase_addr;
342 uint32 nand_inv_read_addr_x;
343 uint32 nand_inv_read_addr;
344 uint32 PAD[2];
345 uint32 nand_blk_wr_protect;
346 uint32 PAD[3];
347 uint32 nand_acc_control_cs1;
348 uint32 nand_config_cs1;
349 uint32 nand_timing_1_cs1;
350 uint32 nand_timing_2_cs1;
351 uint32 PAD[20];
352 uint32 nand_spare_rd16;
353 uint32 nand_spare_rd20;
354 uint32 nand_spare_rd24;
355 uint32 nand_spare_rd28;
356 uint32 nand_cache_addr;
357 uint32 nand_cache_data;
358 uint32 nand_ctrl_config;
359 uint32 nand_ctrl_status;
360 #endif /* NFLASH_SUPPORT */
361 uint32 gci_corecaps0; /* GCI starting at 0xC00 */
362 uint32 gci_corecaps1;
363 uint32 gci_corecaps2;
364 uint32 gci_corectrl;
365 uint32 gci_corestat; /* 0xC10 */
366 uint32 PAD[11];
367 uint32 gci_indirect_addr; /* 0xC40 */
368 uint32 PAD[111];
369 uint32 gci_chipctrl; /* 0xE00 */
370 } chipcregs_t;
371
372 #endif /* _LANGUAGE_ASSEMBLY */
373
374 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
375 /* Selective swapped defines for those registers we need in
376 * big-endian code.
377 */
378 #define CC_CHIPID 4
379 #define CC_CAPABILITIES 0
380 #define CC_CHIPST 0x28
381 #define CC_EROMPTR 0xf8
382
383 #else /* !IL_BIGENDIAN || !BCMHND74K */
384
385 #define CC_CHIPID 0
386 #define CC_CAPABILITIES 4
387 #define CC_CHIPST 0x2c
388 #define CC_EROMPTR 0xfc
389
390 #endif /* IL_BIGENDIAN && BCMHND74K */
391
392 #define CC_OTPST 0x10
393 #define CC_JTAGCMD 0x30
394 #define CC_JTAGIR 0x34
395 #define CC_JTAGDR 0x38
396 #define CC_JTAGCTRL 0x3c
397 #define CC_GPIOPU 0x58
398 #define CC_GPIOPD 0x5c
399 #define CC_GPIOIN 0x60
400 #define CC_GPIOOUT 0x64
401 #define CC_GPIOOUTEN 0x68
402 #define CC_GPIOCTRL 0x6c
403 #define CC_GPIOPOL 0x70
404 #define CC_GPIOINTM 0x74
405 #define CC_WATCHDOG 0x80
406 #define CC_CLKC_N 0x90
407 #define CC_CLKC_M0 0x94
408 #define CC_CLKC_M1 0x98
409 #define CC_CLKC_M2 0x9c
410 #define CC_CLKC_M3 0xa0
411 #define CC_CLKDIV 0xa4
412 #define CC_SYS_CLK_CTL 0xc0
413 #define CC_CLK_CTL_ST SI_CLK_CTL_ST
414 #define PMU_CTL 0x600
415 #define PMU_CAP 0x604
416 #define PMU_ST 0x608
417 #define PMU_RES_STATE 0x60c
418 #define PMU_TIMER 0x614
419 #define PMU_MIN_RES_MASK 0x618
420 #define PMU_MAX_RES_MASK 0x61c
421 #define CC_CHIPCTL_ADDR 0x650
422 #define CC_CHIPCTL_DATA 0x654
423 #define PMU_REG_CONTROL_ADDR 0x658
424 #define PMU_REG_CONTROL_DATA 0x65C
425 #define PMU_PLL_CONTROL_ADDR 0x660
426 #define PMU_PLL_CONTROL_DATA 0x664
427 #define CC_SROM_CTRL 0x190
428 #define CC_SROM_OTP 0x800 /* SROM/OTP address space */
429 #define CC_GCI_INDIRECT_ADDR_REG 0xC40
430 #define CC_GCI_CHIP_CTRL_REG 0xE00
431 #define CC_GCI_CC_OFFSET_2 2
432 #define CC_GCI_CC_OFFSET_5 5
433
434 #ifdef NFLASH_SUPPORT
435 /* NAND flash support */
436 #define CC_NAND_REVISION 0xC00
437 #define CC_NAND_CMD_START 0xC04
438 #define CC_NAND_CMD_ADDR 0xC0C
439 #define CC_NAND_SPARE_RD_0 0xC20
440 #define CC_NAND_SPARE_RD_4 0xC24
441 #define CC_NAND_SPARE_RD_8 0xC28
442 #define CC_NAND_SPARE_RD_C 0xC2C
443 #define CC_NAND_CONFIG 0xC48
444 #define CC_NAND_DEVID 0xC60
445 #define CC_NAND_DEVID_EXT 0xC64
446 #define CC_NAND_INTFC_STATUS 0xC6C
447 #endif /* NFLASH_SUPPORT */
448
449 /* chipid */
450 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */
451 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
452 #define CID_REV_SHIFT 16 /* Chip Revision shift */
453 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */
454 #define CID_PKG_SHIFT 20 /* Package Option shift */
455 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
456 #define CID_CC_SHIFT 24
457 #define CID_TYPE_MASK 0xf0000000 /* Chip Type */
458 #define CID_TYPE_SHIFT 28
459
460 /* capabilities */
461 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
462 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
463 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
464 #define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
465 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
466 #define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
467 #define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
468 #define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
469 #define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
470 #define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
471 #define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
472 #define CC_CAP_PWR_CTL 0x00040000 /* Power control */
473 #define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
474 #define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
475 #define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
476 #define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
477 #define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
478 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
479 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
480 #define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
481 #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
482 #define CC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */
483
484 #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
485 #define CC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */
486
487 /* capabilities extension */
488 #define CC_CAP_EXT_SECI_PRESENT 0x00000001 /* SECI present */
489
490 /* PLL type */
491 #define PLL_NONE 0x00000000
492 #define PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */
493 #define PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */
494 #define PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */
495 #define PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */
496 #define PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */
497 #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
498 #define PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */
499
500 /* ILP clock */
501 #define ILP_CLOCK 32000
502
503 /* ALP clock on pre-PMU chips */
504 #define ALP_CLOCK 20000000
505
506 #ifdef CFG_SIM
507 #define NS_ALP_CLOCK 84922
508 #define NS_SLOW_ALP_CLOCK 84922
509 #define NS_CPU_CLOCK 534500
510 #define NS_SLOW_CPU_CLOCK 534500
511 #define NS_SI_CLOCK 271750
512 #define NS_SLOW_SI_CLOCK 271750
513 #define NS_FAST_MEM_CLOCK 271750
514 #define NS_MEM_CLOCK 271750
515 #define NS_SLOW_MEM_CLOCK 271750
516 #else
517 #define NS_ALP_CLOCK 125000000
518 #define NS_SLOW_ALP_CLOCK 100000000
519 #define NS_CPU_CLOCK 1000000000
520 #define NS_SLOW_CPU_CLOCK 800000000
521 #define NS_SI_CLOCK 250000000
522 #define NS_SLOW_SI_CLOCK 200000000
523 #define NS_FAST_MEM_CLOCK 800000000
524 #define NS_MEM_CLOCK 533000000
525 #define NS_SLOW_MEM_CLOCK 400000000
526 #endif /* CFG_SIM */
527
528 /* HT clock */
529 #define HT_CLOCK 80000000
530
531 /* corecontrol */
532 #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
533 #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
534 #define CC_ASYNCGPIO 0x00000004 /* 1=generate GPIO interrupt without backplane clock */
535 #define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
536
537 /* 4321 chipcontrol */
538 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
539 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
540 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */
541
542 /* Fields in the otpstatus register in rev >= 21 */
543 #define OTPS_OL_MASK 0x000000ff
544 #define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
545 #define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
546 #define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
547 #define OTPS_OL_GU 0x00000008 /* general use region is locked */
548 #define OTPS_GUP_MASK 0x00000f00
549 #define OTPS_GUP_SHIFT 8
550 #define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
551 #define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
552 #define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
553 #define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
554 #define OTPS_READY 0x00001000
555 #define OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */
556 #define OTPS_RV_MASK 0x0fff0000
557 #define OTPS_PROGOK 0x40000000
558
559 /* Fields in the otpcontrol register in rev >= 21 */
560 #define OTPC_PROGSEL 0x00000001
561 #define OTPC_PCOUNT_MASK 0x0000000e
562 #define OTPC_PCOUNT_SHIFT 1
563 #define OTPC_VSEL_MASK 0x000000f0
564 #define OTPC_VSEL_SHIFT 4
565 #define OTPC_TMM_MASK 0x00000700
566 #define OTPC_TMM_SHIFT 8
567 #define OTPC_ODM 0x00000800
568 #define OTPC_PROGEN 0x80000000
569
570 /* Fields in the 40nm otpcontrol register in rev >= 40 */
571 #define OTPC_40NM_PROGSEL_SHIFT 0
572 #define OTPC_40NM_PCOUNT_SHIFT 1
573 #define OTPC_40NM_PCOUNT_WR 0xA
574 #define OTPC_40NM_PCOUNT_V1X 0xB
575 #define OTPC_40NM_REGCSEL_SHIFT 5
576 #define OTPC_40NM_REGCSEL_DEF 0x4
577 #define OTPC_40NM_PROGIN_SHIFT 8
578 #define OTPC_40NM_R2X_SHIFT 10
579 #define OTPC_40NM_ODM_SHIFT 11
580 #define OTPC_40NM_DF_SHIFT 15
581 #define OTPC_40NM_VSEL_SHIFT 16
582 #define OTPC_40NM_VSEL_WR 0xA
583 #define OTPC_40NM_VSEL_V1X 0xA
584 #define OTPC_40NM_VSEL_R1X 0x5
585 #define OTPC_40NM_COFAIL_SHIFT 30
586
587 #define OTPC1_CPCSEL_SHIFT 0
588 #define OTPC1_CPCSEL_DEF 6
589 #define OTPC1_TM_SHIFT 8
590 #define OTPC1_TM_WR 0x84
591 #define OTPC1_TM_V1X 0x84
592 #define OTPC1_TM_R1X 0x4
593
594 /* Fields in otpprog in rev >= 21 and HND OTP */
595 #define OTPP_COL_MASK 0x000000ff
596 #define OTPP_COL_SHIFT 0
597 #define OTPP_ROW_MASK 0x0000ff00
598 #define OTPP_ROW_SHIFT 8
599 #define OTPP_OC_MASK 0x0f000000
600 #define OTPP_OC_SHIFT 24
601 #define OTPP_READERR 0x10000000
602 #define OTPP_VALUE_MASK 0x20000000
603 #define OTPP_VALUE_SHIFT 29
604 #define OTPP_START_BUSY 0x80000000
605 #define OTPP_READ 0x40000000 /* HND OTP */
606
607 /* Fields in otplayout register */
608 #define OTPL_HWRGN_OFF_MASK 0x00000FFF
609 #define OTPL_HWRGN_OFF_SHIFT 0
610 #define OTPL_WRAP_REVID_MASK 0x00F80000
611 #define OTPL_WRAP_REVID_SHIFT 19
612 #define OTPL_WRAP_TYPE_MASK 0x00070000
613 #define OTPL_WRAP_TYPE_SHIFT 16
614 #define OTPL_WRAP_TYPE_65NM 0
615 #define OTPL_WRAP_TYPE_40NM 1
616
617 /* otplayout reg corerev >= 36 */
618 #define OTP_CISFORMAT_NEW 0x80000000
619
620 /* Opcodes for OTPP_OC field */
621 #define OTPPOC_READ 0
622 #define OTPPOC_BIT_PROG 1
623 #define OTPPOC_VERIFY 3
624 #define OTPPOC_INIT 4
625 #define OTPPOC_SET 5
626 #define OTPPOC_RESET 6
627 #define OTPPOC_OCST 7
628 #define OTPPOC_ROW_LOCK 8
629 #define OTPPOC_PRESCN_TEST 9
630
631 /* Opcodes for OTPP_OC field (40NM) */
632 #define OTPPOC_READ_40NM 0
633 #define OTPPOC_PROG_ENABLE_40NM 1
634 #define OTPPOC_PROG_DISABLE_40NM 2
635 #define OTPPOC_VERIFY_40NM 3
636 #define OTPPOC_WORD_VERIFY_1_40NM 4
637 #define OTPPOC_ROW_LOCK_40NM 5
638 #define OTPPOC_STBY_40NM 6
639 #define OTPPOC_WAKEUP_40NM 7
640 #define OTPPOC_WORD_VERIFY_0_40NM 8
641 #define OTPPOC_PRESCN_TEST_40NM 9
642 #define OTPPOC_BIT_PROG_40NM 10
643 #define OTPPOC_WORDPROG_40NM 11
644 #define OTPPOC_BURNIN_40NM 12
645 #define OTPPOC_AUTORELOAD_40NM 13
646 #define OTPPOC_OVST_READ_40NM 14
647 #define OTPPOC_OVST_PROG_40NM 15
648
649 /* Fields in otplayoutextension */
650 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF
651
652
653 /* Jtagm characteristics that appeared at a given corerev */
654 #define JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */
655 #define JTAGM_CREV_IRP 22 /* Able to do pause-ir */
656 #define JTAGM_CREV_RTI 28 /* Able to do return-to-idle */
657
658 /* jtagcmd */
659 #define JCMD_START 0x80000000
660 #define JCMD_BUSY 0x80000000
661 #define JCMD_STATE_MASK 0x60000000
662 #define JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */
663 #define JCMD_STATE_PIR 0x20000000 /* Pause IR */
664 #define JCMD_STATE_PDR 0x40000000 /* Pause DR */
665 #define JCMD_STATE_RTI 0x60000000 /* Run-test-idle */
666 #define JCMD0_ACC_MASK 0x0000f000
667 #define JCMD0_ACC_IRDR 0x00000000
668 #define JCMD0_ACC_DR 0x00001000
669 #define JCMD0_ACC_IR 0x00002000
670 #define JCMD0_ACC_RESET 0x00003000
671 #define JCMD0_ACC_IRPDR 0x00004000
672 #define JCMD0_ACC_PDR 0x00005000
673 #define JCMD0_IRW_MASK 0x00000f00
674 #define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
675 #define JCMD_ACC_IRDR 0x00000000
676 #define JCMD_ACC_DR 0x00010000
677 #define JCMD_ACC_IR 0x00020000
678 #define JCMD_ACC_RESET 0x00030000
679 #define JCMD_ACC_IRPDR 0x00040000
680 #define JCMD_ACC_PDR 0x00050000
681 #define JCMD_ACC_PIR 0x00060000
682 #define JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */
683 #define JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */
684 #define JCMD_IRW_MASK 0x00001f00
685 #define JCMD_IRW_SHIFT 8
686 #define JCMD_DRW_MASK 0x0000003f
687
688 /* jtagctrl */
689 #define JCTRL_FORCE_CLK 4 /* Force clock */
690 #define JCTRL_EXT_EN 2 /* Enable external targets */
691 #define JCTRL_EN 1 /* Enable Jtag master */
692
693 /* Fields in clkdiv */
694 #define CLKD_SFLASH 0x0f000000
695 #define CLKD_SFLASH_SHIFT 24
696 #define CLKD_OTP 0x000f0000
697 #define CLKD_OTP_SHIFT 16
698 #define CLKD_JTAG 0x00000f00
699 #define CLKD_JTAG_SHIFT 8
700 #define CLKD_UART 0x000000ff
701
702 #define CLKD2_SROM 0x00000003
703
704 /* intstatus/intmask */
705 #define CI_GPIO 0x00000001 /* gpio intr */
706 #define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
707 #define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
708 #define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
709 #define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
710 #define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
711 #define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
712 #define CI_WDRESET 0x80000000 /* watchdog reset occurred */
713
714 /* slow_clk_ctl */
715 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
716 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
717 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
718 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
719 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
720 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
721 * 0: LPO is enabled
722 */
723 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
724 * 0: power logic control
725 */
726 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
727 * PLL clock disable requests from core
728 */
729 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
730 * disable crystal when appropriate
731 */
732 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
733 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
734 #define SCC_CD_SHIFT 16
735
736 /* system_clk_ctl */
737 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
738 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
739 #define SYCC_FP 0x00000004 /* ForcePLLOn */
740 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
741 #define SYCC_HR 0x00000010 /* Force HT */
742 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
743 #define SYCC_CD_SHIFT 16
744
745 /* Indirect backplane access */
746 #define BPIA_BYTEEN 0x0000000f
747 #define BPIA_SZ1 0x00000001
748 #define BPIA_SZ2 0x00000003
749 #define BPIA_SZ4 0x00000007
750 #define BPIA_SZ8 0x0000000f
751 #define BPIA_WRITE 0x00000100
752 #define BPIA_START 0x00000200
753 #define BPIA_BUSY 0x00000200
754 #define BPIA_ERROR 0x00000400
755
756 /* pcmcia/prog/flash_config */
757 #define CF_EN 0x00000001 /* enable */
758 #define CF_EM_MASK 0x0000000e /* mode */
759 #define CF_EM_SHIFT 1
760 #define CF_EM_FLASH 0 /* flash/asynchronous mode */
761 #define CF_EM_SYNC 2 /* synchronous mode */
762 #define CF_EM_PCMCIA 4 /* pcmcia mode */
763 #define CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */
764 #define CF_BS 0x00000020 /* byteswap */
765 #define CF_CD_MASK 0x000000c0 /* clock divider */
766 #define CF_CD_SHIFT 6
767 #define CF_CD_DIV2 0x00000000 /* backplane/2 */
768 #define CF_CD_DIV3 0x00000040 /* backplane/3 */
769 #define CF_CD_DIV4 0x00000080 /* backplane/4 */
770 #define CF_CE 0x00000100 /* clock enable */
771 #define CF_SB 0x00000200 /* size/bytestrobe (synch only) */
772
773 /* pcmcia_memwait */
774 #define PM_W0_MASK 0x0000003f /* waitcount0 */
775 #define PM_W1_MASK 0x00001f00 /* waitcount1 */
776 #define PM_W1_SHIFT 8
777 #define PM_W2_MASK 0x001f0000 /* waitcount2 */
778 #define PM_W2_SHIFT 16
779 #define PM_W3_MASK 0x1f000000 /* waitcount3 */
780 #define PM_W3_SHIFT 24
781
782 /* pcmcia_attrwait */
783 #define PA_W0_MASK 0x0000003f /* waitcount0 */
784 #define PA_W1_MASK 0x00001f00 /* waitcount1 */
785 #define PA_W1_SHIFT 8
786 #define PA_W2_MASK 0x001f0000 /* waitcount2 */
787 #define PA_W2_SHIFT 16
788 #define PA_W3_MASK 0x1f000000 /* waitcount3 */
789 #define PA_W3_SHIFT 24
790
791 /* pcmcia_iowait */
792 #define PI_W0_MASK 0x0000003f /* waitcount0 */
793 #define PI_W1_MASK 0x00001f00 /* waitcount1 */
794 #define PI_W1_SHIFT 8
795 #define PI_W2_MASK 0x001f0000 /* waitcount2 */
796 #define PI_W2_SHIFT 16
797 #define PI_W3_MASK 0x1f000000 /* waitcount3 */
798 #define PI_W3_SHIFT 24
799
800 /* prog_waitcount */
801 #define PW_W0_MASK 0x0000001f /* waitcount0 */
802 #define PW_W1_MASK 0x00001f00 /* waitcount1 */
803 #define PW_W1_SHIFT 8
804 #define PW_W2_MASK 0x001f0000 /* waitcount2 */
805 #define PW_W2_SHIFT 16
806 #define PW_W3_MASK 0x1f000000 /* waitcount3 */
807 #define PW_W3_SHIFT 24
808
809 #define PW_W0 0x0000000c
810 #define PW_W1 0x00000a00
811 #define PW_W2 0x00020000
812 #define PW_W3 0x01000000
813
814 /* flash_waitcount */
815 #define FW_W0_MASK 0x0000003f /* waitcount0 */
816 #define FW_W1_MASK 0x00001f00 /* waitcount1 */
817 #define FW_W1_SHIFT 8
818 #define FW_W2_MASK 0x001f0000 /* waitcount2 */
819 #define FW_W2_SHIFT 16
820 #define FW_W3_MASK 0x1f000000 /* waitcount3 */
821 #define FW_W3_SHIFT 24
822
823 /* watchdog */
824 #define WATCHDOG_CLOCK 48000000 /* Hz */
825 #define WATCHDOG_CLOCK_5354 32000 /* Hz */
826
827 /* When Srom support present, fields in sromcontrol */
828 #define SRC_START 0x80000000
829 #define SRC_BUSY 0x80000000
830 #define SRC_OPCODE 0x60000000
831 #define SRC_OP_READ 0x00000000
832 #define SRC_OP_WRITE 0x20000000
833 #define SRC_OP_WRDIS 0x40000000
834 #define SRC_OP_WREN 0x60000000
835 #define SRC_OTPSEL 0x00000010
836 #define SRC_LOCK 0x00000008
837 #define SRC_SIZE_MASK 0x00000006
838 #define SRC_SIZE_1K 0x00000000
839 #define SRC_SIZE_4K 0x00000002
840 #define SRC_SIZE_16K 0x00000004
841 #define SRC_SIZE_SHIFT 1
842 #define SRC_PRESENT 0x00000001
843
844 /* Fields in pmucontrol */
845 #define PCTL_ILP_DIV_MASK 0xffff0000
846 #define PCTL_ILP_DIV_SHIFT 16
847 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
848 #define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
849 #define PCTL_HT_REQ_EN 0x00000100
850 #define PCTL_ALP_REQ_EN 0x00000080
851 #define PCTL_XTALFREQ_MASK 0x0000007c
852 #define PCTL_XTALFREQ_SHIFT 2
853 #define PCTL_ILP_DIV_EN 0x00000002
854 #define PCTL_LPO_SEL 0x00000001
855
856 /* Fields in clkstretch */
857 #define CSTRETCH_HT 0xffff0000
858 #define CSTRETCH_ALP 0x0000ffff
859
860 /* gpiotimerval */
861 #define GPIO_ONTIME_SHIFT 16
862
863 /* clockcontrol_n */
864 #define CN_N1_MASK 0x3f /* n1 control */
865 #define CN_N2_MASK 0x3f00 /* n2 control */
866 #define CN_N2_SHIFT 8
867 #define CN_PLLC_MASK 0xf0000 /* pll control */
868 #define CN_PLLC_SHIFT 16
869
870 /* clockcontrol_sb/pci/uart */
871 #define CC_M1_MASK 0x3f /* m1 control */
872 #define CC_M2_MASK 0x3f00 /* m2 control */
873 #define CC_M2_SHIFT 8
874 #define CC_M3_MASK 0x3f0000 /* m3 control */
875 #define CC_M3_SHIFT 16
876 #define CC_MC_MASK 0x1f000000 /* mux control */
877 #define CC_MC_SHIFT 24
878
879 /* N3M Clock control magic field values */
880 #define CC_F6_2 0x02 /* A factor of 2 in */
881 #define CC_F6_3 0x03 /* 6-bit fields like */
882 #define CC_F6_4 0x05 /* N1, M1 or M3 */
883 #define CC_F6_5 0x09
884 #define CC_F6_6 0x11
885 #define CC_F6_7 0x21
886
887 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
888
889 #define CC_MC_BYPASS 0x08
890 #define CC_MC_M1 0x04
891 #define CC_MC_M1M2 0x02
892 #define CC_MC_M1M2M3 0x01
893 #define CC_MC_M1M3 0x11
894
895 /* Type 2 Clock control magic field values */
896 #define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
897 #define CC_T2M2_BIAS 3 /* m2 bias */
898
899 #define CC_T2MC_M1BYP 1
900 #define CC_T2MC_M2BYP 2
901 #define CC_T2MC_M3BYP 4
902
903 /* Type 6 Clock control magic field values */
904 #define CC_T6_MMASK 1 /* bits of interest in m */
905 #define CC_T6_M0 120000000 /* sb clock for m = 0 */
906 #define CC_T6_M1 100000000 /* sb clock for m = 1 */
907 #define SB2MIPS_T6(sb) (2 * (sb))
908
909 /* Common clock base */
910 #define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
911 #define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */
912
913 /* Clock control values for 200MHz in 5350 */
914 #define CLKC_5350_N 0x0311
915 #define CLKC_5350_M 0x04020009
916
917 /* Flash types in the chipcommon capabilities register */
918 #define FLASH_NONE 0x000 /* No flash */
919 #define SFLASH_ST 0x100 /* ST serial flash */
920 #define SFLASH_AT 0x200 /* Atmel serial flash */
921 #define NFLASH 0x300
922 #define PFLASH 0x700 /* Parallel flash */
923 #define QSPIFLASH_ST 0x800
924 #define QSPIFLASH_AT 0x900
925
926 /* Bits in the ExtBus config registers */
927 #define CC_CFG_EN 0x0001 /* Enable */
928 #define CC_CFG_EM_MASK 0x000e /* Extif Mode */
929 #define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
930 #define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
931 #define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
932 #define CC_CFG_EM_IDE 0x0006 /* IDE */
933 #define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
934 #define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
935 #define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
936 #define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
937 #define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
938
939 /* ExtBus address space */
940 #define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
941 #define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
942 #define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
943 #define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
944 #define CC_EB_IDE 0x1a800000 /* IDE memory base */
945 #define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
946 #define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
947 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
948 #define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
949
950
951 /* Start/busy bit in flashcontrol */
952 #define SFLASH_OPCODE 0x000000ff
953 #define SFLASH_ACTION 0x00000700
954 #define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
955 #define SFLASH_START 0x80000000
956 #define SFLASH_BUSY SFLASH_START
957
958 /* flashcontrol action codes */
959 #define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
960 #define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
961 #define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */
962 #define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */
963 #define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */
964 #define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */
965 #define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */
966
967 /* flashcontrol action+opcodes for ST flashes */
968 #define SFLASH_ST_WREN 0x0006 /* Write Enable */
969 #define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
970 #define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
971 #define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
972 #define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
973 #define SFLASH_ST_PP 0x0302 /* Page Program */
974 #define SFLASH_ST_SE 0x02d8 /* Sector Erase */
975 #define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
976 #define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
977 #define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
978 #define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
979 #define SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */
980
981 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */
982 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */
983
984 /* Status register bits for ST flashes */
985 #define SFLASH_ST_WIP 0x01 /* Write In Progress */
986 #define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
987 #define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
988 #define SFLASH_ST_BP_SHIFT 2
989 #define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
990
991 /* flashcontrol action+opcodes for Atmel flashes */
992 #define SFLASH_AT_READ 0x07e8
993 #define SFLASH_AT_PAGE_READ 0x07d2
994 #define SFLASH_AT_BUF1_READ
995 #define SFLASH_AT_BUF2_READ
996 #define SFLASH_AT_STATUS 0x01d7
997 #define SFLASH_AT_BUF1_WRITE 0x0384
998 #define SFLASH_AT_BUF2_WRITE 0x0387
999 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
1000 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
1001 #define SFLASH_AT_BUF1_PROGRAM 0x0288
1002 #define SFLASH_AT_BUF2_PROGRAM 0x0289
1003 #define SFLASH_AT_PAGE_ERASE 0x0281
1004 #define SFLASH_AT_BLOCK_ERASE 0x0250
1005 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
1006 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
1007 #define SFLASH_AT_BUF1_LOAD 0x0253
1008 #define SFLASH_AT_BUF2_LOAD 0x0255
1009 #define SFLASH_AT_BUF1_COMPARE 0x0260
1010 #define SFLASH_AT_BUF2_COMPARE 0x0261
1011 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
1012 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
1013
1014 /* Status register bits for Atmel flashes */
1015 #define SFLASH_AT_READY 0x80
1016 #define SFLASH_AT_MISMATCH 0x40
1017 #define SFLASH_AT_ID_MASK 0x38
1018 #define SFLASH_AT_ID_SHIFT 3
1019
1020 /* SPI register bits, corerev >= 37 */
1021 #define GSIO_START 0x80000000
1022 #define GSIO_BUSY GSIO_START
1023
1024 /*
1025 * These are the UART port assignments, expressed as offsets from the base
1026 * register. These assignments should hold for any serial port based on
1027 * a 8250, 16450, or 16550(A).
1028 */
1029
1030 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1031 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
1032 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
1033 #define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
1034 #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
1035 #define UART_IIR 2 /* In: Interrupt Identity Register */
1036 #define UART_FCR 2 /* Out: FIFO Control Register */
1037 #define UART_LCR 3 /* Out: Line Control Register */
1038 #define UART_MCR 4 /* Out: Modem Control Register */
1039 #define UART_LSR 5 /* In: Line Status Register */
1040 #define UART_MSR 6 /* In: Modem Status Register */
1041 #define UART_SCR 7 /* I/O: Scratch Register */
1042 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1043 #define UART_LCR_WLEN8 0x03 /* Word length: 8 bits */
1044 #define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
1045 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1046 #define UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */
1047 #define UART_LSR_TDHR 0x40 /* Data-hold-register empty */
1048 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1049 #define UART_LSR_BREAK 0x10 /* Break interrupt */
1050 #define UART_LSR_FRAMING 0x08 /* Framing error */
1051 #define UART_LSR_PARITY 0x04 /* Parity error */
1052 #define UART_LSR_OVERRUN 0x02 /* Overrun error */
1053 #define UART_LSR_RXRDY 0x01 /* Receiver ready */
1054 #define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
1055
1056 /* Interrupt Identity Register (IIR) bits */
1057 #define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
1058 #define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
1059 #define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
1060 #define UART_IIR_NOINT 0x1 /* No interrupt pending */
1061 #define UART_IIR_THRE 0x2 /* THR empty */
1062 #define UART_IIR_RCVD_DATA 0x4 /* Received data available */
1063 #define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
1064 #define UART_IIR_CHAR_TIME 0xc /* Character time */
1065
1066 /* Interrupt Enable Register (IER) bits */
1067 #define UART_IER_EDSSI 8 /* enable modem status interrupt */
1068 #define UART_IER_ELSI 4 /* enable receiver line status interrupt */
1069 #define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
1070 #define UART_IER_ERBFI 1 /* enable data available interrupt */
1071
1072 /* pmustatus */
1073 #define PST_EXTLPOAVAIL 0x0100
1074 #define PST_WDRESET 0x0080
1075 #define PST_INTPEND 0x0040
1076 #define PST_SBCLKST 0x0030
1077 #define PST_SBCLKST_ILP 0x0010
1078 #define PST_SBCLKST_ALP 0x0020
1079 #define PST_SBCLKST_HT 0x0030
1080 #define PST_ALPAVAIL 0x0008
1081 #define PST_HTAVAIL 0x0004
1082 #define PST_RESINIT 0x0003
1083
1084 /* pmucapabilities */
1085 #define PCAP_REV_MASK 0x000000ff
1086 #define PCAP_RC_MASK 0x00001f00
1087 #define PCAP_RC_SHIFT 8
1088 #define PCAP_TC_MASK 0x0001e000
1089 #define PCAP_TC_SHIFT 13
1090 #define PCAP_PC_MASK 0x001e0000
1091 #define PCAP_PC_SHIFT 17
1092 #define PCAP_VC_MASK 0x01e00000
1093 #define PCAP_VC_SHIFT 21
1094 #define PCAP_CC_MASK 0x1e000000
1095 #define PCAP_CC_SHIFT 25
1096 #define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
1097 #define PCAP5_PC_SHIFT 17
1098 #define PCAP5_VC_MASK 0x07c00000
1099 #define PCAP5_VC_SHIFT 22
1100 #define PCAP5_CC_MASK 0xf8000000
1101 #define PCAP5_CC_SHIFT 27
1102
1103 /* PMU Resource Request Timer registers */
1104 /* This is based on PmuRev0 */
1105 #define PRRT_TIME_MASK 0x03ff
1106 #define PRRT_INTEN 0x0400
1107 #define PRRT_REQ_ACTIVE 0x0800
1108 #define PRRT_ALP_REQ 0x1000
1109 #define PRRT_HT_REQ 0x2000
1110 #define PRRT_HQ_REQ 0x4000
1111
1112 /* PMU resource bit position */
1113 #define PMURES_BIT(bit) (1 << (bit))
1114
1115 /* PMU resource number limit */
1116 #define PMURES_MAX_RESNUM 30
1117
1118 /* PMU chip control0 register */
1119 #define PMU_CHIPCTL0 0
1120
1121 /* clock req types */
1122 #define PMU_CC1_CLKREQ_TYPE_SHIFT 19
1123 #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT)
1124
1125 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0
1126 #define CLKREQ_TYPE_CONFIG_PUSHPULL 1
1127
1128 /* PMU chip control1 register */
1129 #define PMU_CHIPCTL1 1
1130 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000
1131
1132 #define PMU_CC1_IF_TYPE_MASK 0x00000030
1133 #define PMU_CC1_IF_TYPE_RMII 0x00000000
1134 #define PMU_CC1_IF_TYPE_MII 0x00000010
1135 #define PMU_CC1_IF_TYPE_RGMII 0x00000020
1136
1137 #define PMU_CC1_SW_TYPE_MASK 0x000000c0
1138 #define PMU_CC1_SW_TYPE_EPHY 0x00000000
1139 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
1140 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
1141 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0
1142
1143 /* PMU chip control2 register */
1144 #define PMU_CHIPCTL2 2
1145
1146 /* PMU chip control3 register */
1147 #define PMU_CHIPCTL3 3
1148
1149 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19
1150 #define PMU_CC3_ENABLE_RF_SHIFT 22
1151 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23
1152
1153
1154 /* PMU corerev and chip specific PLL controls.
1155 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
1156 * to differentiate different PLLs controlled by the same PMU rev.
1157 */
1158 /* pllcontrol registers */
1159 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
1160 #define PMU0_PLL0_PLLCTL0 0
1161 #define PMU0_PLL0_PC0_PDIV_MASK 1
1162 #define PMU0_PLL0_PC0_PDIV_FREQ 25000
1163 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
1164 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
1165 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8
1166
1167 /* PC0_DIV_ARM for PLLOUT_ARM */
1168 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
1169 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
1170 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
1171 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
1172 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
1173 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
1174 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
1175 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
1176
1177 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
1178 #define PMU0_PLL0_PLLCTL1 1
1179 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
1180 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
1181 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
1182 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
1183 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040
1184
1185 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
1186 #define PMU0_PLL0_PLLCTL2 2
1187 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
1188 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
1189
1190 /* pllcontrol registers */
1191 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
1192 #define PMU1_PLL0_PLLCTL0 0
1193 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
1194 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20
1195 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
1196 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24
1197
1198 /* m<x>div */
1199 #define PMU1_PLL0_PLLCTL1 1
1200 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
1201 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0
1202 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
1203 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8
1204 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
1205 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16
1206 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
1207 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24
1208 #define PMU1_PLL0_PC1_M4DIV_BY_9 9
1209 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12
1210 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24
1211
1212 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
1213 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1214 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1215
1216 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
1217 #define PMU1_PLL0_PLLCTL2 2
1218 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
1219 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0
1220 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc
1221 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12
1222 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24
1223 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
1224 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8
1225 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12
1226 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24
1227 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
1228 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
1229 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1
1230 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */
1231 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
1232 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
1233
1234 /* ndiv_frac */
1235 #define PMU1_PLL0_PLLCTL3 3
1236 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
1237 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
1238
1239 /* pll_ctrl */
1240 #define PMU1_PLL0_PLLCTL4 4
1241
1242 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
1243 #define PMU1_PLL0_PLLCTL5 5
1244 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
1245 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
1246
1247 /* PMU rev 2 control words */
1248 #define PMU2_PHY_PLL_PLLCTL 4
1249 #define PMU2_SI_PLL_PLLCTL 10
1250
1251 /* PMU rev 2 */
1252 /* pllcontrol registers */
1253 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
1254 #define PMU2_PLL_PLLCTL0 0
1255 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
1256 #define PMU2_PLL_PC0_P1DIV_SHIFT 20
1257 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
1258 #define PMU2_PLL_PC0_P2DIV_SHIFT 24
1259
1260 /* m<x>div */
1261 #define PMU2_PLL_PLLCTL1 1
1262 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
1263 #define PMU2_PLL_PC1_M1DIV_SHIFT 0
1264 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
1265 #define PMU2_PLL_PC1_M2DIV_SHIFT 8
1266 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
1267 #define PMU2_PLL_PC1_M3DIV_SHIFT 16
1268 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
1269 #define PMU2_PLL_PC1_M4DIV_SHIFT 24
1270
1271 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
1272 #define PMU2_PLL_PLLCTL2 2
1273 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
1274 #define PMU2_PLL_PC2_M5DIV_SHIFT 0
1275 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
1276 #define PMU2_PLL_PC2_M6DIV_SHIFT 8
1277 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
1278 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17
1279 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
1280 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20
1281
1282 /* ndiv_frac */
1283 #define PMU2_PLL_PLLCTL3 3
1284 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
1285 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
1286
1287 /* pll_ctrl */
1288 #define PMU2_PLL_PLLCTL4 4
1289
1290 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
1291 #define PMU2_PLL_PLLCTL5 5
1292 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
1293 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
1294 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
1295 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
1296 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
1297 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
1298 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
1299 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
1300 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
1301 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
1302 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
1303 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
1304
1305 /* PMU rev 5 (& 6) */
1306 #define PMU5_PLL_P1P2_OFF 0
1307 #define PMU5_PLL_P1_MASK 0x0f000000
1308 #define PMU5_PLL_P1_SHIFT 24
1309 #define PMU5_PLL_P2_MASK 0x00f00000
1310 #define PMU5_PLL_P2_SHIFT 20
1311 #define PMU5_PLL_M14_OFF 1
1312 #define PMU5_PLL_MDIV_MASK 0x000000ff
1313 #define PMU5_PLL_MDIV_WIDTH 8
1314 #define PMU5_PLL_NM5_OFF 2
1315 #define PMU5_PLL_NDIV_MASK 0xfff00000
1316 #define PMU5_PLL_NDIV_SHIFT 20
1317 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
1318 #define PMU5_PLL_NDIV_MODE_SHIFT 17
1319 #define PMU5_PLL_FMAB_OFF 3
1320 #define PMU5_PLL_MRAT_MASK 0xf0000000
1321 #define PMU5_PLL_MRAT_SHIFT 28
1322 #define PMU5_PLL_ABRAT_MASK 0x08000000
1323 #define PMU5_PLL_ABRAT_SHIFT 27
1324 #define PMU5_PLL_FDIV_MASK 0x07ffffff
1325 #define PMU5_PLL_PLLCTL_OFF 4
1326 #define PMU5_PLL_PCHI_OFF 5
1327 #define PMU5_PLL_PCHI_MASK 0x0000003f
1328
1329 /* pmu XtalFreqRatio */
1330 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
1331 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
1332 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
1333
1334 /* Divider allocation in 4716/47162/5356/5357 */
1335 #define PMU5_MAINPLL_CPU 1
1336 #define PMU5_MAINPLL_MEM 2
1337 #define PMU5_MAINPLL_SI 3
1338
1339 /* 4706 PMU */
1340 #define PMU4706_MAINPLL_PLL0 0
1341 #define PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
1342 #define PMU6_4706_PROC_P2DIV_MASK 0x000f0000
1343 #define PMU6_4706_PROC_P2DIV_SHIFT 16
1344 #define PMU6_4706_PROC_P1DIV_MASK 0x0000f000
1345 #define PMU6_4706_PROC_P1DIV_SHIFT 12
1346 #define PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
1347 #define PMU6_4706_PROC_NDIV_INT_SHIFT 3
1348 #define PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1349 #define PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1350
1351 #define PMU7_PLL_PLLCTL7 7
1352 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000
1353 #define PMU7_PLL_CTL7_M4DIV_SHIFT 24
1354 #define PMU7_PLL_CTL7_M4DIV_BY_6 6
1355 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc
1356 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18
1357 #define PMU7_PLL_PLLCTL8 8
1358 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff
1359 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0
1360 #define PMU7_PLL_CTL8_M5DIV_BY_8 8
1361 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc
1362 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18
1363 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00
1364 #define PMU7_PLL_CTL8_M6DIV_SHIFT 8
1365 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc
1366 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18
1367 #define PMU7_PLL_PLLCTL11 11
1368 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00
1369 #define PMU7_PLL_PLLCTL11_VAL 0x22222200
1370
1371 /* PMU rev 15 */
1372 #define PMU15_PLL_PLLCTL0 0
1373 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1374 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0
1375 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1376 #define PMU15_PLL_PC0_FREQTGT_SHIFT 2
1377 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1378 #define PMU15_PLL_PC0_PRESCALE_SHIFT 22
1379 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1380 #define PMU15_PLL_PC0_KPCTRL_SHIFT 24
1381 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1382 #define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1383 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1384 #define PMU15_PLL_PC0_FDCMODE_SHIFT 30
1385 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1386 #define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1387
1388 #define PMU15_PLL_PLLCTL1 1
1389 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060
1390 #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5
1391 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040
1392 #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6
1393 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80
1394 #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7
1395 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000
1396 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17
1397 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000
1398 #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26
1399 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000
1400 #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28
1401 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000
1402 #define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30
1403
1404 #define PMU15_PLL_PLLCTL2 2
1405 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001
1406 #define PMU15_PLL_PC2_CTEN_SHIFT 0
1407
1408 #define PMU15_PLL_PLLCTL3 3
1409 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001
1410 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0
1411 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000
1412 #define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25
1413 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01
1414 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0
1415 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02
1416 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1
1417 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04
1418 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2
1419 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18
1420 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3
1421 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60
1422 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5
1423 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0
1424 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1
1425 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2
1426 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3
1427
1428 #define PMU15_PLL_PLLCTL4 4
1429 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007
1430 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0
1431 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038
1432 #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3
1433 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0
1434 #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6
1435 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00
1436 #define PMU15_PLL_PC4_DBGMODE_SHIFT 9
1437 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000
1438 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12
1439 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000
1440 #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13
1441 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000
1442 #define PMU15_PLL_PC4_DINPOL_SHIFT 20
1443 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000
1444 #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21
1445 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000
1446 #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22
1447 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000
1448 #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23
1449 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000
1450 #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24
1451 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000
1452 #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25
1453 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000
1454 #define PMU15_PLL_PC4_TEST_EN_SHIFT 26
1455
1456 #define PMU15_PLL_PLLCTL5 5
1457 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF
1458 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0
1459 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000
1460 #define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20
1461 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000
1462 #define PMU15_PLL_PC5_PRESCALE_SHIFT 27
1463
1464 #define PMU15_PLL_PLLCTL6 6
1465 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF
1466 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0
1467 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000
1468 #define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20
1469 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000
1470 #define PMU15_PLL_PC6_PRESCALE_SHIFT 27
1471
1472 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1
1473 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5
1474 #define PMU15_ARM_96MHZ 96000000 /* 96 Mhz */
1475 #define PMU15_ARM_98MHZ 98400000 /* 98.4 Mhz */
1476 #define PMU15_ARM_97MHZ 97000000 /* 97 Mhz */
1477
1478
1479 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070
1480 #define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4
1481
1482 #define PMU17_PLLCTL2_NDIV_MODE_INT 0
1483 #define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1
1484 #define PMU17_PLLCTL2_NDIV_MODE_MASH111 2
1485 #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3
1486
1487 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0
1488 #define PMU17_PLLCTL0_BBPLL_DRST 3
1489 #define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8
1490
1491 /* PLL usage in 4716/47162 */
1492 #define PMU4716_MAINPLL_PLL0 12
1493
1494 /* PLL usage in 5356/5357 */
1495 #define PMU5356_MAINPLL_PLL0 0
1496 #define PMU5357_MAINPLL_PLL0 0
1497
1498 /* 4716/47162 resources */
1499 #define RES4716_PROC_PLL_ON 0x00000040
1500 #define RES4716_PROC_HT_AVAIL 0x00000080
1501
1502 /* 4716/4717/4718 Chip specific ChipControl register bits */
1503 #define CCTRL_471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared w/ pflash */
1504
1505 /* 5357 Chip specific ChipControl register bits */
1506 /* 2nd - 32-bit reg */
1507 #define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 /* I2S pins enable */
1508 #define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 /* I2C/SPI pins enable */
1509
1510 /* 5354 resources */
1511 #define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
1512 #define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
1513 #define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
1514 #define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
1515 #define RES5354_ILP_REQUEST 4 /* 0x00010 */
1516 #define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
1517 #define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
1518 #define RES5354_ROM_SWITCH 7 /* 0x00080 */
1519 #define RES5354_PA_REF_LDO 8 /* 0x00100 */
1520 #define RES5354_RADIO_LDO 9 /* 0x00200 */
1521 #define RES5354_AFE_LDO 10 /* 0x00400 */
1522 #define RES5354_PLL_LDO 11 /* 0x00800 */
1523 #define RES5354_BG_FILTBYP 12 /* 0x01000 */
1524 #define RES5354_TX_FILTBYP 13 /* 0x02000 */
1525 #define RES5354_RX_FILTBYP 14 /* 0x04000 */
1526 #define RES5354_XTAL_PU 15 /* 0x08000 */
1527 #define RES5354_XTAL_EN 16 /* 0x10000 */
1528 #define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
1529 #define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
1530 #define RES5354_BB_PLL_PU 19 /* 0x80000 */
1531
1532 /* 5357 Chip specific ChipControl register bits */
1533 #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
1534 #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
1535 #define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */
1536
1537 /* 43217 Chip specific ChipControl register bits */
1538 #define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */
1539 #define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */
1540
1541 /* 4328 resources */
1542 #define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
1543 #define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
1544 #define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
1545 #define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
1546 #define RES4328_ILP_REQUEST 4 /* 0x00010 */
1547 #define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
1548 #define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
1549 #define RES4328_ROM_SWITCH 7 /* 0x00080 */
1550 #define RES4328_PA_REF_LDO 8 /* 0x00100 */
1551 #define RES4328_RADIO_LDO 9 /* 0x00200 */
1552 #define RES4328_AFE_LDO 10 /* 0x00400 */
1553 #define RES4328_PLL_LDO 11 /* 0x00800 */
1554 #define RES4328_BG_FILTBYP 12 /* 0x01000 */
1555 #define RES4328_TX_FILTBYP 13 /* 0x02000 */
1556 #define RES4328_RX_FILTBYP 14 /* 0x04000 */
1557 #define RES4328_XTAL_PU 15 /* 0x08000 */
1558 #define RES4328_XTAL_EN 16 /* 0x10000 */
1559 #define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
1560 #define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
1561 #define RES4328_BB_PLL_PU 19 /* 0x80000 */
1562
1563 /* 4325 A0/A1 resources */
1564 #define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
1565 #define RES4325_CBUCK_BURST 1 /* 0x00000002 */
1566 #define RES4325_CBUCK_PWM 2 /* 0x00000004 */
1567 #define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
1568 #define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
1569 #define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
1570 #define RES4325_ILP_REQUEST 6 /* 0x00000040 */
1571 #define RES4325_ABUCK_BURST 7 /* 0x00000080 */
1572 #define RES4325_ABUCK_PWM 8 /* 0x00000100 */
1573 #define RES4325_LNLDO1_PU 9 /* 0x00000200 */
1574 #define RES4325_OTP_PU 10 /* 0x00000400 */
1575 #define RES4325_LNLDO3_PU 11 /* 0x00000800 */
1576 #define RES4325_LNLDO4_PU 12 /* 0x00001000 */
1577 #define RES4325_XTAL_PU 13 /* 0x00002000 */
1578 #define RES4325_ALP_AVAIL 14 /* 0x00004000 */
1579 #define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
1580 #define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
1581 #define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1582 #define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1583 #define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
1584 #define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1585 #define RES4325_HT_AVAIL 21 /* 0x00200000 */
1586
1587 /* 4325 B0/C0 resources */
1588 #define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */
1589 #define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */
1590 #define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */
1591 #define RES4325B0_CLDO_PU 4 /* 0x00000010 */
1592
1593 /* 4325 C1 resources */
1594 #define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */
1595
1596 /* 4325 chip-specific ChipStatus register bits */
1597 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003
1598 #define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1599 #define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1600 #define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
1601 #define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
1602 #define CST4325_SDIO_USB_MODE_MASK 0x00000004
1603 #define CST4325_SDIO_USB_MODE_SHIFT 2
1604 #define CST4325_RCAL_VALID_MASK 0x00000008
1605 #define CST4325_RCAL_VALID_SHIFT 3
1606 #define CST4325_RCAL_VALUE_MASK 0x000001f0
1607 #define CST4325_RCAL_VALUE_SHIFT 4
1608 #define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
1609 #define CST4325_PMUTOP_2B_SHIFT 9
1610
1611 #define RES4329_RESERVED0 0 /* 0x00000001 */
1612 #define RES4329_CBUCK_LPOM 1 /* 0x00000002 */
1613 #define RES4329_CBUCK_BURST 2 /* 0x00000004 */
1614 #define RES4329_CBUCK_PWM 3 /* 0x00000008 */
1615 #define RES4329_CLDO_PU 4 /* 0x00000010 */
1616 #define RES4329_PALDO_PU 5 /* 0x00000020 */
1617 #define RES4329_ILP_REQUEST 6 /* 0x00000040 */
1618 #define RES4329_RESERVED7 7 /* 0x00000080 */
1619 #define RES4329_RESERVED8 8 /* 0x00000100 */
1620 #define RES4329_LNLDO1_PU 9 /* 0x00000200 */
1621 #define RES4329_OTP_PU 10 /* 0x00000400 */
1622 #define RES4329_RESERVED11 11 /* 0x00000800 */
1623 #define RES4329_LNLDO2_PU 12 /* 0x00001000 */
1624 #define RES4329_XTAL_PU 13 /* 0x00002000 */
1625 #define RES4329_ALP_AVAIL 14 /* 0x00004000 */
1626 #define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */
1627 #define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */
1628 #define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1629 #define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1630 #define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */
1631 #define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1632 #define RES4329_HT_AVAIL 21 /* 0x00200000 */
1633
1634 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
1635 #define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1636 #define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1637 #define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */
1638 #define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
1639 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
1640 #define CST4329_SPI_SDIO_MODE_SHIFT 2
1641
1642 /* 4312 chip-specific ChipStatus register bits */
1643 #define CST4312_SPROM_OTP_SEL_MASK 0x00000003
1644 #define CST4312_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1645 #define CST4312_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1646 #define CST4312_OTP_SEL 2 /* OTP is powered up, no SPROM */
1647 #define CST4312_OTP_BAD 3 /* OTP is broken, SPROM is present */
1648
1649 /* 4312 resources (all PMU chips with little memory constraint) */
1650 #define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
1651 #define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
1652 #define RES4312_PA_REF_LDO 2 /* 0x00000004 */
1653 #define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
1654 #define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
1655 #define RES4312_RADIO_LDO 5 /* 0x00000020 */
1656 #define RES4312_ILP_REQUEST 6 /* 0x00000040 */
1657 #define RES4312_BG_FILTBYP 7 /* 0x00000080 */
1658 #define RES4312_TX_FILTBYP 8 /* 0x00000100 */
1659 #define RES4312_RX_FILTBYP 9 /* 0x00000200 */
1660 #define RES4312_XTAL_PU 10 /* 0x00000400 */
1661 #define RES4312_ALP_AVAIL 11 /* 0x00000800 */
1662 #define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
1663 #define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
1664 #define RES4312_HT_AVAIL 14 /* 0x00004000 */
1665
1666 /* 4322 resources */
1667 #define RES4322_RF_LDO 0
1668 #define RES4322_ILP_REQUEST 1
1669 #define RES4322_XTAL_PU 2
1670 #define RES4322_ALP_AVAIL 3
1671 #define RES4322_SI_PLL_ON 4
1672 #define RES4322_HT_SI_AVAIL 5
1673 #define RES4322_PHY_PLL_ON 6
1674 #define RES4322_HT_PHY_AVAIL 7
1675 #define RES4322_OTP_PU 8
1676
1677 /* 4322 chip-specific ChipStatus register bits */
1678 #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020
1679 #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0
1680 #define CST4322_SPROM_OTP_SEL_SHIFT 6
1681 #define CST4322_NO_SPROM_OTP 0 /* no OTP, no SPROM */
1682 #define CST4322_SPROM_PRESENT 1 /* SPROM is present */
1683 #define CST4322_OTP_PRESENT 2 /* OTP is present */
1684 #define CST4322_PCI_OR_USB 0x00000100
1685 #define CST4322_BOOT_MASK 0x00000600
1686 #define CST4322_BOOT_SHIFT 9
1687 #define CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
1688 #define CST4322_BOOT_FROM_ROM 1 /* boot from ROM */
1689 #define CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */
1690 #define CST4322_BOOT_FROM_INVALID 3
1691 #define CST4322_ILP_DIV_EN 0x00000800
1692 #define CST4322_FLASH_TYPE_MASK 0x00001000
1693 #define CST4322_FLASH_TYPE_SHIFT 12
1694 #define CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */
1695 #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */
1696 #define CST4322_ARM_TAP_SEL 0x00002000
1697 #define CST4322_RES_INIT_MODE_MASK 0x0000c000
1698 #define CST4322_RES_INIT_MODE_SHIFT 14
1699 #define CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */
1700 #define CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */
1701 #define CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */
1702 #define CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */
1703 #define CST4322_PCIPLLCLK_GATING 0x00010000
1704 #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000
1705 #define CST4322_PCI_CARDBUS_MODE 0x00040000
1706
1707 /* 43224 chip-specific ChipControl register bits */
1708 #define CCTRL43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
1709 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
1710 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
1711
1712 /* 43236 resources */
1713 #define RES43236_REGULATOR 0
1714 #define RES43236_ILP_REQUEST 1
1715 #define RES43236_XTAL_PU 2
1716 #define RES43236_ALP_AVAIL 3
1717 #define RES43236_SI_PLL_ON 4
1718 #define RES43236_HT_SI_AVAIL 5
1719
1720 /* 43236 chip-specific ChipControl register bits */
1721 #define CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */
1722 #define CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
1723 #define CCTRL43236_EXT_LNA (1<<2) /* 0 disable */
1724 #define CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */
1725 #define CCTRL43236_GSIO (1<<4) /* 0 disable */
1726
1727 /* 43236 Chip specific ChipStatus register bits */
1728 #define CST43236_SFLASH_MASK 0x00000040
1729 #define CST43236_OTP_SEL_MASK 0x00000080
1730 #define CST43236_OTP_SEL_SHIFT 7
1731 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
1732 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
1733 #define CST43236_BOOT_MASK 0x00001800
1734 #define CST43236_BOOT_SHIFT 11
1735 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
1736 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
1737 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
1738 #define CST43236_BOOT_FROM_INVALID 3
1739
1740 /* 43237 resources */
1741 #define RES43237_REGULATOR 0
1742 #define RES43237_ILP_REQUEST 1
1743 #define RES43237_XTAL_PU 2
1744 #define RES43237_ALP_AVAIL 3
1745 #define RES43237_SI_PLL_ON 4
1746 #define RES43237_HT_SI_AVAIL 5
1747
1748 /* 43237 chip-specific ChipControl register bits */
1749 #define CCTRL43237_BT_COEXIST (1<<0) /* 0 disable */
1750 #define CCTRL43237_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
1751 #define CCTRL43237_EXT_LNA (1<<2) /* 0 disable */
1752 #define CCTRL43237_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */
1753 #define CCTRL43237_GSIO (1<<4) /* 0 disable */
1754
1755 /* 43237 Chip specific ChipStatus register bits */
1756 #define CST43237_SFLASH_MASK 0x00000040
1757 #define CST43237_OTP_SEL_MASK 0x00000080
1758 #define CST43237_OTP_SEL_SHIFT 7
1759 #define CST43237_HSIC_MASK 0x00000100 /* USB/HSIC */
1760 #define CST43237_BP_CLK 0x00000200 /* 120/96Mbps */
1761 #define CST43237_BOOT_MASK 0x00001800
1762 #define CST43237_BOOT_SHIFT 11
1763 #define CST43237_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
1764 #define CST43237_BOOT_FROM_ROM 1 /* boot from ROM */
1765 #define CST43237_BOOT_FROM_FLASH 2 /* boot from FLASH */
1766 #define CST43237_BOOT_FROM_INVALID 3
1767
1768 /* 43239 resources */
1769 #define RES43239_OTP_PU 9
1770 #define RES43239_MACPHY_CLKAVAIL 23
1771 #define RES43239_HT_AVAIL 24
1772
1773 /* 43239 Chip specific ChipStatus register bits */
1774 #define CST43239_SPROM_MASK 0x00000002
1775 #define CST43239_SFLASH_MASK 0x00000004
1776 #define CST43239_RES_INIT_MODE_SHIFT 7
1777 #define CST43239_RES_INIT_MODE_MASK 0x000001f0
1778 #define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15)) /* SDIO || gSPI */
1779 #define CST43239_CHIPMODE_USB20D(cs) (~(cs) & (1 << 15)) /* USB || USBDA */
1780 #define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0) /* SDIO */
1781 #define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) /* gSPI */
1782
1783 /* 4324 resources */
1784 /* 43242 use same PMU as 4324 */
1785 #define RES4324_LPLDO_PU 0
1786 #define RES4324_RESET_PULLDN_DIS 1
1787 #define RES4324_PMU_BG_PU 2
1788 #define RES4324_HSIC_LDO_PU 3
1789 #define RES4324_CBUCK_LPOM_PU 4
1790 #define RES4324_CBUCK_PFM_PU 5
1791 #define RES4324_CLDO_PU 6
1792 #define RES4324_LPLDO2_LVM 7
1793 #define RES4324_LNLDO1_PU 8
1794 #define RES4324_LNLDO2_PU 9
1795 #define RES4324_LDO3P3_PU 10
1796 #define RES4324_OTP_PU 11
1797 #define RES4324_XTAL_PU 12
1798 #define RES4324_BBPLL_PU 13
1799 #define RES4324_LQ_AVAIL 14
1800 #define RES4324_WL_CORE_READY 17
1801 #define RES4324_ILP_REQ 18
1802 #define RES4324_ALP_AVAIL 19
1803 #define RES4324_PALDO_PU 20
1804 #define RES4324_RADIO_PU 21
1805 #define RES4324_SR_CLK_STABLE 22
1806 #define RES4324_SR_SAVE_RESTORE 23
1807 #define RES4324_SR_PHY_PWRSW 24
1808 #define RES4324_SR_PHY_PIC 25
1809 #define RES4324_SR_SUBCORE_PWRSW 26
1810 #define RES4324_SR_SUBCORE_PIC 27
1811 #define RES4324_SR_MEM_PM0 28
1812 #define RES4324_HT_AVAIL 29
1813 #define RES4324_MACPHY_CLKAVAIL 30
1814
1815 /* 4324 Chip specific ChipStatus register bits */
1816 #define CST4324_SPROM_MASK 0x00000080
1817 #define CST4324_SFLASH_MASK 0x00400000
1818 #define CST4324_RES_INIT_MODE_SHIFT 10
1819 #define CST4324_RES_INIT_MODE_MASK 0x00000c00
1820 #define CST4324_CHIPMODE_MASK 0x7
1821 #define CST4324_CHIPMODE_SDIOD(cs) ((~(cs)) & (1 << 2)) /* SDIO || gSPI */
1822 #define CST4324_CHIPMODE_USB20D(cs) (((cs) & CST4324_CHIPMODE_MASK) == 0x6) /* USB || USBDA */
1823
1824 /* 43242 Chip specific ChipStatus register bits */
1825 #define CST43242_SFLASH_MASK 0x00000008
1826
1827 /* 4331 resources */
1828 #define RES4331_REGULATOR 0
1829 #define RES4331_ILP_REQUEST 1
1830 #define RES4331_XTAL_PU 2
1831 #define RES4331_ALP_AVAIL 3
1832 #define RES4331_SI_PLL_ON 4
1833 #define RES4331_HT_SI_AVAIL 5
1834
1835 /* 4331 chip-specific ChipControl register bits */
1836 #define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */
1837 #define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
1838 #define CCTRL4331_EXT_LNA_G (1<<2) /* 0 disable */
1839 #define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */
1840 #define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */
1841 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */
1842 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */
1843 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */
1844 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */
1845 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */
1846 #define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */
1847 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */
1848 #define CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa disable, 1 ext pa enabled */
1849 #define CCTRL4331_EXT_LNA_A (1<<13) /* 0 disable */
1850 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */
1851 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */
1852 #define CCTRL4331_EXTPA_ANA_EN (1<<24) /* 0 ext pa disable, 1 ext pa enabled */
1853
1854 /* 4331 Chip specific ChipStatus register bits */
1855 #define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */
1856 #define CST4331_SPROM_OTP_SEL_MASK 0x00000006
1857 #define CST4331_SPROM_OTP_SEL_SHIFT 1
1858 #define CST4331_SPROM_PRESENT 0x00000002
1859 #define CST4331_OTP_PRESENT 0x00000004
1860 #define CST4331_LDO_RF 0x00000008
1861 #define CST4331_LDO_PAR 0x00000010
1862
1863 /* 4315 resource */
1864 #define RES4315_CBUCK_LPOM 1 /* 0x00000002 */
1865 #define RES4315_CBUCK_BURST 2 /* 0x00000004 */
1866 #define RES4315_CBUCK_PWM 3 /* 0x00000008 */
1867 #define RES4315_CLDO_PU 4 /* 0x00000010 */
1868 #define RES4315_PALDO_PU 5 /* 0x00000020 */
1869 #define RES4315_ILP_REQUEST 6 /* 0x00000040 */
1870 #define RES4315_LNLDO1_PU 9 /* 0x00000200 */
1871 #define RES4315_OTP_PU 10 /* 0x00000400 */
1872 #define RES4315_LNLDO2_PU 12 /* 0x00001000 */
1873 #define RES4315_XTAL_PU 13 /* 0x00002000 */
1874 #define RES4315_ALP_AVAIL 14 /* 0x00004000 */
1875 #define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */
1876 #define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */
1877 #define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1878 #define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1879 #define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */
1880 #define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1881 #define RES4315_HT_AVAIL 21 /* 0x00200000 */
1882
1883 /* 4315 chip-specific ChipStatus register bits */
1884 #define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /* gpio [7:6], SDIO CIS selection */
1885 #define CST4315_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
1886 #define CST4315_SPROM_SEL 0x00000001 /* use SPROM, OTP is powered up */
1887 #define CST4315_OTP_SEL 0x00000002 /* use OTP, OTP is powered up */
1888 #define CST4315_OTP_PWRDN 0x00000003 /* use SPROM, OTP is powered down */
1889 #define CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */
1890 #define CST4315_RCAL_VALID 0x00000008
1891 #define CST4315_RCAL_VALUE_MASK 0x000001f0
1892 #define CST4315_RCAL_VALUE_SHIFT 4
1893 #define CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */
1894 #define CST4315_CBUCK_MODE_MASK 0x00000c00
1895 #define CST4315_CBUCK_MODE_BURST 0x00000400
1896 #define CST4315_CBUCK_MODE_LPBURST 0x00000c00
1897
1898 /* 4319 resources */
1899 #define RES4319_CBUCK_LPOM 1 /* 0x00000002 */
1900 #define RES4319_CBUCK_BURST 2 /* 0x00000004 */
1901 #define RES4319_CBUCK_PWM 3 /* 0x00000008 */
1902 #define RES4319_CLDO_PU 4 /* 0x00000010 */
1903 #define RES4319_PALDO_PU 5 /* 0x00000020 */
1904 #define RES4319_ILP_REQUEST 6 /* 0x00000040 */
1905 #define RES4319_LNLDO1_PU 9 /* 0x00000200 */
1906 #define RES4319_OTP_PU 10 /* 0x00000400 */
1907 #define RES4319_LNLDO2_PU 12 /* 0x00001000 */
1908 #define RES4319_XTAL_PU 13 /* 0x00002000 */
1909 #define RES4319_ALP_AVAIL 14 /* 0x00004000 */
1910 #define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */
1911 #define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */
1912 #define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1913 #define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1914 #define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */
1915 #define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1916 #define RES4319_HT_AVAIL 21 /* 0x00200000 */
1917
1918 /* 4319 chip-specific ChipStatus register bits */
1919 #define CST4319_SPI_CPULESSUSB 0x00000001
1920 #define CST4319_SPI_CLK_POL 0x00000002
1921 #define CST4319_SPI_CLK_PH 0x00000008
1922 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */
1923 #define CST4319_SPROM_OTP_SEL_SHIFT 6
1924 #define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
1925 #define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */
1926 #define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */
1927 #define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */
1928 #define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */
1929 #define CST4319_REMAP_SEL_MASK 0x00000600
1930 #define CST4319_ILPDIV_EN 0x00000800
1931 #define CST4319_XTAL_PD_POL 0x00001000
1932 #define CST4319_LPO_SEL 0x00002000
1933 #define CST4319_RES_INIT_MODE 0x0000c000
1934 #define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */
1935 #define CST4319_CBUCK_MODE_MASK 0x00060000
1936 #define CST4319_CBUCK_MODE_BURST 0x00020000
1937 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
1938 #define CST4319_RCAL_VALID 0x01000000
1939 #define CST4319_RCAL_VALUE_MASK 0x3e000000
1940 #define CST4319_RCAL_VALUE_SHIFT 25
1941
1942 #define PMU1_PLL0_CHIPCTL0 0
1943 #define PMU1_PLL0_CHIPCTL1 1
1944 #define PMU1_PLL0_CHIPCTL2 2
1945 #define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
1946 #define CCTL_4319USB_XTAL_SEL_SHIFT 19
1947 #define CCTL_4319USB_48MHZ_PLL_SEL 1
1948 #define CCTL_4319USB_24MHZ_PLL_SEL 2
1949
1950 /* PMU resources for 4336 */
1951 #define RES4336_CBUCK_LPOM 0
1952 #define RES4336_CBUCK_BURST 1
1953 #define RES4336_CBUCK_LP_PWM 2
1954 #define RES4336_CBUCK_PWM 3
1955 #define RES4336_CLDO_PU 4
1956 #define RES4336_DIS_INT_RESET_PD 5
1957 #define RES4336_ILP_REQUEST 6
1958 #define RES4336_LNLDO_PU 7
1959 #define RES4336_LDO3P3_PU 8
1960 #define RES4336_OTP_PU 9
1961 #define RES4336_XTAL_PU 10
1962 #define RES4336_ALP_AVAIL 11
1963 #define RES4336_RADIO_PU 12
1964 #define RES4336_BG_PU 13
1965 #define RES4336_VREG1p4_PU_PU 14
1966 #define RES4336_AFE_PWRSW_PU 15
1967 #define RES4336_RX_PWRSW_PU 16
1968 #define RES4336_TX_PWRSW_PU 17
1969 #define RES4336_BB_PWRSW_PU 18
1970 #define RES4336_SYNTH_PWRSW_PU 19
1971 #define RES4336_MISC_PWRSW_PU 20
1972 #define RES4336_LOGEN_PWRSW_PU 21
1973 #define RES4336_BBPLL_PWRSW_PU 22
1974 #define RES4336_MACPHY_CLKAVAIL 23
1975 #define RES4336_HT_AVAIL 24
1976 #define RES4336_RSVD 25
1977
1978 /* 4336 chip-specific ChipStatus register bits */
1979 #define CST4336_SPI_MODE_MASK 0x00000001
1980 #define CST4336_SPROM_PRESENT 0x00000002
1981 #define CST4336_OTP_PRESENT 0x00000004
1982 #define CST4336_ARMREMAP_0 0x00000008
1983 #define CST4336_ILPDIV_EN_MASK 0x00000010
1984 #define CST4336_ILPDIV_EN_SHIFT 4
1985 #define CST4336_XTAL_PD_POL_MASK 0x00000020
1986 #define CST4336_XTAL_PD_POL_SHIFT 5
1987 #define CST4336_LPO_SEL_MASK 0x00000040
1988 #define CST4336_LPO_SEL_SHIFT 6
1989 #define CST4336_RES_INIT_MODE_MASK 0x00000180
1990 #define CST4336_RES_INIT_MODE_SHIFT 7
1991 #define CST4336_CBUCK_MODE_MASK 0x00000600
1992 #define CST4336_CBUCK_MODE_SHIFT 9
1993
1994 /* 4336 Chip specific PMU ChipControl register bits */
1995 #define PCTL_4336_SERIAL_ENAB (1 << 24)
1996
1997 /* 4330 resources */
1998 #define RES4330_CBUCK_LPOM 0
1999 #define RES4330_CBUCK_BURST 1
2000 #define RES4330_CBUCK_LP_PWM 2
2001 #define RES4330_CBUCK_PWM 3
2002 #define RES4330_CLDO_PU 4
2003 #define RES4330_DIS_INT_RESET_PD 5
2004 #define RES4330_ILP_REQUEST 6
2005 #define RES4330_LNLDO_PU 7
2006 #define RES4330_LDO3P3_PU 8
2007 #define RES4330_OTP_PU 9
2008 #define RES4330_XTAL_PU 10
2009 #define RES4330_ALP_AVAIL 11
2010 #define RES4330_RADIO_PU 12
2011 #define RES4330_BG_PU 13
2012 #define RES4330_VREG1p4_PU_PU 14
2013 #define RES4330_AFE_PWRSW_PU 15
2014 #define RES4330_RX_PWRSW_PU 16
2015 #define RES4330_TX_PWRSW_PU 17
2016 #define RES4330_BB_PWRSW_PU 18
2017 #define RES4330_SYNTH_PWRSW_PU 19
2018 #define RES4330_MISC_PWRSW_PU 20
2019 #define RES4330_LOGEN_PWRSW_PU 21
2020 #define RES4330_BBPLL_PWRSW_PU 22
2021 #define RES4330_MACPHY_CLKAVAIL 23
2022 #define RES4330_HT_AVAIL 24
2023 #define RES4330_5gRX_PWRSW_PU 25
2024 #define RES4330_5gTX_PWRSW_PU 26
2025 #define RES4330_5g_LOGEN_PWRSW_PU 27
2026
2027 /* 4330 chip-specific ChipStatus register bits */
2028 #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */
2029 #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */
2030 #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */
2031 #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */
2032 #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */
2033 #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */
2034 #define CST4330_OTP_PRESENT 0x00000010
2035 #define CST4330_LPO_AUTODET_EN 0x00000020
2036 #define CST4330_ARMREMAP_0 0x00000040
2037 #define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */
2038 #define CST4330_ILPDIV_EN 0x00000100
2039 #define CST4330_LPO_SEL 0x00000200
2040 #define CST4330_RES_INIT_MODE_SHIFT 10
2041 #define CST4330_RES_INIT_MODE_MASK 0x00000c00
2042 #define CST4330_CBUCK_MODE_SHIFT 12
2043 #define CST4330_CBUCK_MODE_MASK 0x00003000
2044 #define CST4330_CBUCK_POWER_OK 0x00004000
2045 #define CST4330_BB_PLL_LOCKED 0x00008000
2046 #define SOCDEVRAM_BP_ADDR 0x1E000000
2047 #define SOCDEVRAM_ARM_ADDR 0x00800000
2048
2049 /* 4330 Chip specific PMU ChipControl register bits */
2050 #define PCTL_4330_SERIAL_ENAB (1 << 24)
2051
2052 /* 4330 Chip specific ChipControl register bits */
2053 #define CCTRL_4330_GPIO_SEL 0x00000001 /* 1=select GPIOs to be muxed out */
2054 #define CCTRL_4330_ERCX_SEL 0x00000002 /* 1=select ERCX BT coex to be muxed out */
2055 #define CCTRL_4330_SDIO_HOST_WAKE 0x00000004 /* SDIO: 1=configure GPIO0 for host wake */
2056 #define CCTRL_4330_JTAG_DISABLE 0x00000008 /* 1=disable JTAG interface on mux'd pins */
2057
2058 /* 4334 resources */
2059 #define RES4334_LPLDO_PU 0
2060 #define RES4334_RESET_PULLDN_DIS 1
2061 #define RES4334_PMU_BG_PU 2
2062 #define RES4334_HSIC_LDO_PU 3
2063 #define RES4334_CBUCK_LPOM_PU 4
2064 #define RES4334_CBUCK_PFM_PU 5
2065 #define RES4334_CLDO_PU 6
2066 #define RES4334_LPLDO2_LVM 7
2067 #define RES4334_LNLDO_PU 8
2068 #define RES4334_LDO3P3_PU 9
2069 #define RES4334_OTP_PU 10
2070 #define RES4334_XTAL_PU 11
2071 #define RES4334_WL_PWRSW_PU 12
2072 #define RES4334_LQ_AVAIL 13
2073 #define RES4334_LOGIC_RET 14
2074 #define RES4334_MEM_SLEEP 15
2075 #define RES4334_MACPHY_RET 16
2076 #define RES4334_WL_CORE_READY 17
2077 #define RES4334_ILP_REQ 18
2078 #define RES4334_ALP_AVAIL 19
2079 #define RES4334_MISC_PWRSW_PU 20
2080 #define RES4334_SYNTH_PWRSW_PU 21
2081 #define RES4334_RX_PWRSW_PU 22
2082 #define RES4334_RADIO_PU 23
2083 #define RES4334_WL_PMU_PU 24
2084 #define RES4334_VCO_LDO_PU 25
2085 #define RES4334_AFE_LDO_PU 26
2086 #define RES4334_RX_LDO_PU 27
2087 #define RES4334_TX_LDO_PU 28
2088 #define RES4334_HT_AVAIL 29
2089 #define RES4334_MACPHY_CLK_AVAIL 30
2090
2091 /* 4334 chip-specific ChipStatus register bits */
2092 #define CST4334_CHIPMODE_MASK 7
2093 #define CST4334_SDIO_MODE 0x00000000
2094 #define CST4334_SPI_MODE 0x00000004
2095 #define CST4334_HSIC_MODE 0x00000006
2096 #define CST4334_BLUSB_MODE 0x00000007
2097 #define CST4334_CHIPMODE_HSIC(cs) (((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE)
2098 #define CST4334_OTP_PRESENT 0x00000010
2099 #define CST4334_LPO_AUTODET_EN 0x00000020
2100 #define CST4334_ARMREMAP_0 0x00000040
2101 #define CST4334_SPROM_PRESENT 0x00000080
2102 #define CST4334_ILPDIV_EN_MASK 0x00000100
2103 #define CST4334_ILPDIV_EN_SHIFT 8
2104 #define CST4334_LPO_SEL_MASK 0x00000200
2105 #define CST4334_LPO_SEL_SHIFT 9
2106 #define CST4334_RES_INIT_MODE_MASK 0x00000C00
2107 #define CST4334_RES_INIT_MODE_SHIFT 10
2108
2109 /* 4334 Chip specific PMU ChipControl register bits */
2110 #define PCTL_4334_GPIO3_ENAB (1 << 3)
2111
2112 /* 4334 Chip control */
2113 #define CCTRL4334_HSIC_LDO_PU (1 << 23)
2114
2115 /* 4324 Chip specific ChipControl1 register bits */
2116 #define CCTRL1_4324_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2117 #define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2118
2119 /* 43143 chip-specific ChipStatus register bits based on Confluence documentation */
2120 /* register contains strap values sampled during POR */
2121 #define CST43143_REMAP_TO_ROM (3 << 0) /* 00=Boot SRAM, 01=Boot ROM, 10=Boot SFLASH */
2122 #define CST43143_SDIO_EN (1 << 2) /* 0 = USB Enab, SDIO pins are GPIO or I2S */
2123 #define CST43143_SDIO_ISO (1 << 3) /* 1 = SDIO isolated */
2124 #define CST43143_USB_CPU_LESS (1 << 4) /* 1 = CPULess mode Enabled */
2125 #define CST43143_CBUCK_MODE (3 << 6) /* Indicates what controller mode CBUCK is in */
2126 #define CST43143_POK_CBUCK (1 << 8) /* 1 = 1.2V CBUCK voltage ready */
2127 #define CST43143_PMU_OVRSPIKE (1 << 9)
2128 #define CST43143_PMU_OVRTEMP (0xF << 10)
2129 #define CST43143_SR_FLL_CAL_DONE (1 << 14)
2130 #define CST43143_USB_PLL_LOCKDET (1 << 15)
2131 #define CST43143_PMU_PLL_LOCKDET (1 << 16)
2132 #define CST43143_CHIPMODE_SDIOD(cs) (((cs) & CST43143_SDIO_EN) != 0) /* SDIO */
2133
2134 /* 43143 Chip specific ChipControl register bits */
2135 /* 00: SECI is disabled (JATG functional), 01: 2 wire, 10: 4 wire */
2136 #define CCTRL_43143_SECI (1<<0)
2137 #define CCTRL_43143_BT_LEGACY (1<<1)
2138 #define CCTRL_43143_I2S_MODE (1<<2) /* 0: SDIO enabled */
2139 #define CCTRL_43143_I2S_MASTER (1<<3) /* 0: I2S MCLK input disabled */
2140 #define CCTRL_43143_I2S_FULL (1<<4) /* 0: I2S SDIN and SPDIF_TX inputs disabled */
2141 #define CCTRL_43143_GSIO (1<<5) /* 0: sFlash enabled */
2142 #define CCTRL_43143_RF_SWCTRL_MASK (7<<6) /* 0: disabled */
2143 #define CCTRL_43143_RF_SWCTRL_0 (1<<6)
2144 #define CCTRL_43143_RF_SWCTRL_1 (2<<6)
2145 #define CCTRL_43143_RF_SWCTRL_2 (4<<6)
2146 #define CCTRL_43143_RF_XSWCTRL (1<<9) /* 0: UART enabled */
2147 #define CCTRL_43143_HOST_WAKE0 (1<<11) /* 1: SDIO separate interrupt output from GPIO4 */
2148 #define CCTRL_43143_HOST_WAKE1 (1<<12) /* 1: SDIO separate interrupt output from GPIO16 */
2149
2150 /* 43143 resources, based on pmu_params.xls V1.19 */
2151 #define RES43143_EXT_SWITCHER_PWM 0 /* 0x00001 */
2152 #define RES43143_XTAL_PU 1 /* 0x00002 */
2153 #define RES43143_ILP_REQUEST 2 /* 0x00004 */
2154 #define RES43143_ALP_AVAIL 3 /* 0x00008 */
2155 #define RES43143_WL_CORE_READY 4 /* 0x00010 */
2156 #define RES43143_BBPLL_PWRSW_PU 5 /* 0x00020 */
2157 #define RES43143_HT_AVAIL 6 /* 0x00040 */
2158 #define RES43143_RADIO_PU 7 /* 0x00080 */
2159 #define RES43143_MACPHY_CLK_AVAIL 8 /* 0x00100 */
2160 #define RES43143_OTP_PU 9 /* 0x00200 */
2161 #define RES43143_LQ_AVAIL 10 /* 0x00400 */
2162
2163 /* 4313 resources */
2164 #define RES4313_BB_PU_RSRC 0
2165 #define RES4313_ILP_REQ_RSRC 1
2166 #define RES4313_XTAL_PU_RSRC 2
2167 #define RES4313_ALP_AVAIL_RSRC 3
2168 #define RES4313_RADIO_PU_RSRC 4
2169 #define RES4313_BG_PU_RSRC 5
2170 #define RES4313_VREG1P4_PU_RSRC 6
2171 #define RES4313_AFE_PWRSW_RSRC 7
2172 #define RES4313_RX_PWRSW_RSRC 8
2173 #define RES4313_TX_PWRSW_RSRC 9
2174 #define RES4313_BB_PWRSW_RSRC 10
2175 #define RES4313_SYNTH_PWRSW_RSRC 11
2176 #define RES4313_MISC_PWRSW_RSRC 12
2177 #define RES4313_BB_PLL_PWRSW_RSRC 13
2178 #define RES4313_HT_AVAIL_RSRC 14
2179 #define RES4313_MACPHY_CLK_AVAIL_RSRC 15
2180
2181 /* 4313 chip-specific ChipStatus register bits */
2182 #define CST4313_SPROM_PRESENT 1
2183 #define CST4313_OTP_PRESENT 2
2184 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
2185 #define CST4313_SPROM_OTP_SEL_SHIFT 0
2186
2187 /* 4313 Chip specific ChipControl register bits */
2188 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2189
2190 /* PMU respources for 4314 */
2191 #define RES4314_LPLDO_PU 0
2192 #define RES4314_PMU_SLEEP_DIS 1
2193 #define RES4314_PMU_BG_PU 2
2194 #define RES4314_CBUCK_LPOM_PU 3
2195 #define RES4314_CBUCK_PFM_PU 4
2196 #define RES4314_CLDO_PU 5
2197 #define RES4314_LPLDO2_LVM 6
2198 #define RES4314_WL_PMU_PU 7
2199 #define RES4314_LNLDO_PU 8
2200 #define RES4314_LDO3P3_PU 9
2201 #define RES4314_OTP_PU 10
2202 #define RES4314_XTAL_PU 11
2203 #define RES4314_WL_PWRSW_PU 12
2204 #define RES4314_LQ_AVAIL 13
2205 #define RES4314_LOGIC_RET 14
2206 #define RES4314_MEM_SLEEP 15
2207 #define RES4314_MACPHY_RET 16
2208 #define RES4314_WL_CORE_READY 17
2209 #define RES4314_ILP_REQ 18
2210 #define RES4314_ALP_AVAIL 19
2211 #define RES4314_MISC_PWRSW_PU 20
2212 #define RES4314_SYNTH_PWRSW_PU 21
2213 #define RES4314_RX_PWRSW_PU 22
2214 #define RES4314_RADIO_PU 23
2215 #define RES4314_VCO_LDO_PU 24
2216 #define RES4314_AFE_LDO_PU 25
2217 #define RES4314_RX_LDO_PU 26
2218 #define RES4314_TX_LDO_PU 27
2219 #define RES4314_HT_AVAIL 28
2220 #define RES4314_MACPHY_CLK_AVAIL 29
2221
2222 /* 4314 chip-specific ChipStatus register bits */
2223 #define CST4314_OTP_ENABLED 0x00200000
2224
2225 /* 43228 resources */
2226 #define RES43228_NOT_USED 0
2227 #define RES43228_ILP_REQUEST 1
2228 #define RES43228_XTAL_PU 2
2229 #define RES43228_ALP_AVAIL 3
2230 #define RES43228_PLL_EN 4
2231 #define RES43228_HT_PHY_AVAIL 5
2232
2233 /* 43228 chipstatus reg bits */
2234 #define CST43228_ILP_DIV_EN 0x1
2235 #define CST43228_OTP_PRESENT 0x2
2236 #define CST43228_SERDES_REFCLK_PADSEL 0x4
2237 #define CST43228_SDIO_MODE 0x8
2238 #define CST43228_SDIO_OTP_PRESENT 0x10
2239 #define CST43228_SDIO_RESET 0x20
2240
2241 /* 4706 chipstatus reg bits */
2242 #define CST4706_PKG_OPTION (1<<0) /* 0: full-featured package 1: low-cost package */
2243 #define CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */
2244 #define CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2245 #define CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */
2246 #define CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */
2247
2248 /* 4706 flashstrconfig reg bits */
2249 #define FLSTRCF4706_MASK 0x000000ff
2250 #define FLSTRCF4706_SF1 0x00000001 /* 2nd serial flash present */
2251 #define FLSTRCF4706_PF1 0x00000002 /* 2nd parallel flash present */
2252 #define FLSTRCF4706_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
2253 #define FLSTRCF4706_NF1 0x00000008 /* 2nd NAND flash present */
2254 #define FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /* Valid value mask */
2255 #define FLSTRCF4706_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
2256 #define FLSTRCF4706_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
2257 #define FLSTRCF4706_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
2258 #define FLSTRCF4706_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
2259 #define FLSTRCF4706_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
2260 #define FLSTRCF4706_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
2261 #define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
2262
2263 /* 4360 Chip specific ChipControl register bits */
2264 #define CCTRL4360_I2C_MODE (1 << 0)
2265 #define CCTRL4360_UART_MODE (1 << 1)
2266 #define CCTRL4360_SECI_MODE (1 << 2)
2267 #define CCTRL4360_BTSWCTRL_MODE (1 << 3)
2268 #define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4)
2269 #define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5)
2270 #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6)
2271 #define CCTRL4360_EXTRA_GPIO_MODE (1 << 7)
2272 #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8)
2273 #define CCTRL4360_BT_LGCY_MODE (1 << 9)
2274 #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21)
2275 #define CCTRL4360_SECI_ON_GPIO01 (1 << 24)
2276
2277
2278 /* 4360 PMU resources and chip status bits */
2279 #define RES4360_REGULATOR 0
2280 #define RES4360_ILP_AVAIL 1
2281 #define RES4360_ILP_REQ 2
2282 #define RES4360_XTAL_LDO_PU 3
2283 #define RES4360_XTAL_PU 4
2284 #define RES4360_ALP_AVAIL 5
2285 #define RES4360_BBPLLPWRSW_PU 6
2286 #define RES4360_HT_AVAIL 7
2287 #define RES4360_OTP_PU 8
2288
2289 #define CST4360_XTAL_40MZ 0x00000001
2290 #define CST4360_SFLASH 0x00000002
2291 #define CST4360_SPROM_PRESENT 0x00000004
2292 #define CST4360_SFLASH_TYPE 0x00000004
2293 #define CST4360_OTP_ENABLED 0x00000008
2294 #define CST4360_REMAP_ROM 0x00000010
2295 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060
2296 #define CST4360_RSRC_INIT_MODE_SHIFT 5
2297 #define CST4360_ILP_DIVEN 0x00000080
2298 #define CST4360_MODE_USB 0x00000100
2299 #define CST4360_SPROM_SIZE_MASK 0x00000600
2300 #define CST4360_SPROM_SIZE_SHIFT 9
2301 #define CST4360_BBPLL_LOCK 0x00000800
2302 #define CST4360_AVBBPLL_LOCK 0x00001000
2303 #define CST4360_USBBBPLL_LOCK 0x00002000
2304
2305 #define CCTL_4360_UART_SEL 2
2306
2307 /* 4335 resources */
2308 #define RES4335_LPLDO_PO 0
2309 #define RES4335_PMU_BG_PU 1
2310 #define RES4335_PMU_SLEEP 2
2311 #define RES4335_RSVD_3 3
2312 #define RES4335_CBUCK_LPOM_PU 4
2313 #define RES4335_CBUCK_PFM_PU 5
2314 #define RES4335_RSVD_6 6
2315 #define RES4335_RSVD_7 7
2316 #define RES4335_LNLDO_PU 8
2317 #define RES4335_XTALLDO_PU 9
2318 #define RES4335_LDO3P3_PU 10
2319 #define RES4335_OTP_PU 11
2320 #define RES4335_XTAL_PU 12
2321 #define RES4335_SR_CLK_START 13
2322 #define RES4335_LQ_AVAIL 14
2323 #define RES4335_LQ_START 15
2324 #define RES4335_RSVD_16 16
2325 #define RES4335_WL_CORE_RDY 17
2326 #define RES4335_ILP_REQ 18
2327 #define RES4335_ALP_AVAIL 19
2328 #define RES4335_MINI_PMU 20
2329 #define RES4335_RADIO_PU 21
2330 #define RES4335_SR_CLK_STABLE 22
2331 #define RES4335_SR_SAVE_RESTORE 23
2332 #define RES4335_SR_PHY_PWRSW 24
2333 #define RES4335_SR_VDDM_PWRSW 25
2334 #define RES4335_SR_SUBCORE_PWRSW 26
2335 #define RES4335_SR_SLEEP 27
2336 #define RES4335_HT_START 28
2337 #define RES4335_HT_AVAIL 29
2338 #define RES4335_MACPHY_CLKAVAIL 30
2339
2340 /* 4335 Chip specific ChipStatus register bits */
2341 #define CST4335_SPROM_MASK 0x00000020
2342 #define CST4335_SFLASH_MASK 0x00000040
2343 #define CST4335_RES_INIT_MODE_SHIFT 7
2344 #define CST4335_RES_INIT_MODE_MASK 0x00000180
2345 #define CST4335_CHIPMODE_MASK 0xF
2346 #define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */
2347 #define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */
2348 #define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) /* USB || USBDA */
2349 #define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */
2350
2351 /* 4335 Chip specific ChipControl1 register bits */
2352 #define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2353 #define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2354
2355
2356 #define CR4_RAM_BASE (0x180000)
2357 #define PATCHTBL_SIZE (0x800)
2358 /* 4335 resources--END */
2359
2360 /* 4350 PMU resources and chip status bits */
2361 #define CST4350_SDIO_MODE 0x00000001
2362 #define CST4350_HSIC20D_MODE 0x00000002
2363 #define CST4350_HSIC30D_MODE 0x00000004
2364 #define CST4350_PCIE_MODE 0x00000008
2365 #define CST4350_USB20D_MODE 0x00000010
2366 #define CST4350_USB30D_MODE 0x00000020
2367 #define CST4350_SPROM_PRESENT 0x00000040
2368 #define CST4350_SFLASH_PRESENT 0x00040000
2369
2370 #define RES4350_LPLDO_PU 0
2371 #define RES4350_PMU_BG_PU 1
2372 #define RES4350_PMU_SLEEP 2
2373 #define RES4350_RSVD_3 3
2374 #define RES4350_CBUCK_LPOM_PU 4
2375 #define RES4350_CBUCK_PFM_PU 5
2376 #define RES4350_COLD_START_WAIT 6
2377 #define RES4350_RSVD_7 7
2378 #define RES4350_LNLDO_PU 8
2379 #define RES4350_XTALLDO_PU 9
2380 #define RES4350_LDO3P3_PU 10
2381 #define RES4350_OTP_PU 11
2382 #define RES4350_XTAL_PU 12
2383 #define RES4350_SR_CLK_START 13
2384 #define RES4350_LQ_AVAIL 14
2385 #define RES4350_LQ_START 15
2386 #define RES4350_RSVD_16 16
2387 #define RES4350_WL_CORE_RDY 17
2388 #define RES4350_ILP_REQ 18
2389 #define RES4350_ALP_AVAIL 19
2390 #define RES4350_MINI_PMU 20
2391 #define RES4350_RADIO_PU 21
2392 #define RES4350_SR_CLK_STABLE 22
2393 #define RES4350_SR_SAVE_RESTORE 23
2394 #define RES4350_SR_PHY_PWRSW 24
2395 #define RES4350_SR_VDDM_PWRSW 25
2396 #define RES4350_SR_SUBCORE_PWRSW 26
2397 #define RES4350_SR_SLEEP 27
2398 #define RES4350_HT_START 28
2399 #define RES4350_HT_AVAIL 29
2400 #define RES4350_MACPHY_CLKAVAIL 30
2401
2402 #define CST4350_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0)
2403
2404 /* GCI chipcontrol register indices */
2405 #define CC_GCI_CHIPCTRL_00 (0)
2406 #define CC_GCI_CHIPCTRL_01 (1)
2407 #define CC_GCI_CHIPCTRL_02 (2)
2408 #define CC_GCI_CHIPCTRL_03 (3)
2409 #define CC_GCI_CHIPCTRL_04 (4)
2410 #define CC_GCI_CHIPCTRL_05 (5)
2411 #define CC_GCI_CHIPCTRL_06 (6)
2412 #define CC_GCI_CHIPCTRL_07 (7)
2413 #define CC_GCI_CHIPCTRL_08 (8)
2414
2415 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8)
2416
2417 /* 4335 pins
2418 * note: only the values set as default/used are added here.
2419 */
2420 #define CC4335_PIN_GPIO_00 (0)
2421 #define CC4335_PIN_GPIO_01 (1)
2422 #define CC4335_PIN_GPIO_02 (2)
2423 #define CC4335_PIN_GPIO_03 (3)
2424 #define CC4335_PIN_GPIO_04 (4)
2425 #define CC4335_PIN_GPIO_05 (5)
2426 #define CC4335_PIN_GPIO_06 (6)
2427 #define CC4335_PIN_GPIO_07 (7)
2428 #define CC4335_PIN_GPIO_08 (8)
2429 #define CC4335_PIN_GPIO_09 (9)
2430 #define CC4335_PIN_GPIO_10 (10)
2431 #define CC4335_PIN_GPIO_11 (11)
2432 #define CC4335_PIN_GPIO_12 (12)
2433 #define CC4335_PIN_GPIO_13 (13)
2434 #define CC4335_PIN_GPIO_14 (14)
2435 #define CC4335_PIN_GPIO_15 (15)
2436 #define CC4335_PIN_SDIO_CLK (16)
2437 #define CC4335_PIN_SDIO_CMD (17)
2438 #define CC4335_PIN_SDIO_DATA0 (18)
2439 #define CC4335_PIN_SDIO_DATA1 (19)
2440 #define CC4335_PIN_SDIO_DATA2 (20)
2441 #define CC4335_PIN_SDIO_DATA3 (21)
2442 #define CC4335_PIN_RF_SW_CTRL_6 (22)
2443 #define CC4335_PIN_RF_SW_CTRL_7 (23)
2444 #define CC4335_PIN_RF_SW_CTRL_8 (24)
2445 #define CC4335_PIN_RF_SW_CTRL_9 (25)
2446
2447 /* 4335 GCI function sel values
2448 */
2449 #define CC4335_FNSEL_HWDEF (0)
2450 #define CC4335_FNSEL_SAMEASPIN (1)
2451 #define CC4335_FNSEL_GPIO0 (2)
2452 #define CC4335_FNSEL_GPIO1 (3)
2453 #define CC4335_FNSEL_GCI0 (4)
2454 #define CC4335_FNSEL_GCI1 (5)
2455 #define CC4335_FNSEL_UART (6)
2456 #define CC4335_FNSEL_SFLASH (7)
2457 #define CC4335_FNSEL_SPROM (8)
2458 #define CC4335_FNSEL_MISC0 (9)
2459 #define CC4335_FNSEL_MISC1 (10)
2460 #define CC4335_FNSEL_MISC2 (11)
2461 #define CC4335_FNSEL_IND (12)
2462 #define CC4335_FNSEL_PDN (13)
2463 #define CC4335_FNSEL_PUP (14)
2464 #define CC4335_FNSEL_TRI (15)
2465
2466 /* find the 4 bit mask given the bit position */
2467 #define GCIMASK(pos) (((uint32)0xF) << pos)
2468
2469 /* get the value which can be used to directly OR with chipcontrol reg */
2470 #define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos))
2471
2472 /* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic
2473 * for now only UART for bootloader.
2474 */
2475 #define MUXENAB4335_UART_MASK (0x0000000f)
2476
2477
2478 /* defines to detect active host interface in use */
2479 #define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) & CST4360_MODE_USB)
2480
2481 /*
2482 * Maximum delay for the PMU state transition in us.
2483 * This is an upper bound intended for spinwaits etc.
2484 */
2485 #define PMU_MAX_TRANSITION_DLY 20000
2486
2487 /* PMU resource up transition time in ILP cycles */
2488 #define PMURES_UP_TRANSITION 2
2489
2490 /*
2491 * Information from BT to WLAN over eci_inputlo, eci_inputmi &
2492 * eci_inputhi register. Rev >=21
2493 */
2494 /* Fields in eci_inputlo register - [0:31] */
2495 #define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */
2496 #define ECI_INLO_TASKTYPE_SHIFT 0
2497 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
2498 #define ECI_INLO_PKTDUR_SHIFT 4
2499 #define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */
2500 #define ECI_INLO_ROLE_SHIFT 8
2501 #define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */
2502 #define ECI_INLO_MLP_SHIFT 9
2503 #define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */
2504 #define ECI_INLO_TXPWR_SHIFT 12
2505 #define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */
2506 #define ECI_INLO_RSSI_SHIFT 20
2507 #define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */
2508 #define ECI_INLO_VAD_SHIFT 28
2509
2510 /*
2511 * Register eci_inputlo bitfield values.
2512 * - BT packet type information bits [7:0]
2513 */
2514 /* [3:0] - Task (link) type */
2515 #define BT_ACL 0x00
2516 #define BT_SCO 0x01
2517 #define BT_eSCO 0x02
2518 #define BT_A2DP 0x03
2519 #define BT_SNIFF 0x04
2520 #define BT_PAGE_SCAN 0x05
2521 #define BT_INQUIRY_SCAN 0x06
2522 #define BT_PAGE 0x07
2523 #define BT_INQUIRY 0x08
2524 #define BT_MSS 0x09
2525 #define BT_PARK 0x0a
2526 #define BT_RSSISCAN 0x0b
2527 #define BT_MD_ACL 0x0c
2528 #define BT_MD_eSCO 0x0d
2529 #define BT_SCAN_WITH_SCO_LINK 0x0e
2530 #define BT_SCAN_WITHOUT_SCO_LINK 0x0f
2531 /* [7:4] = packet duration code */
2532 /* [8] - Master / Slave */
2533 #define BT_MASTER 0
2534 #define BT_SLAVE 1
2535 /* [11:9] - multi-level priority */
2536 #define BT_LOWEST_PRIO 0x0
2537 #define BT_HIGHEST_PRIO 0x3
2538 /* [19:12] - BT transmit power */
2539 /* [27:20] - BT RSSI */
2540 /* [28] - VAD silence */
2541 /* [31:29] - Undefined */
2542 /* Register eci_inputmi values - [32:63] - none defined */
2543 /* [63:32] - Undefined */
2544
2545 /* Information from WLAN to BT over eci_output register. */
2546 /* Fields in eci_output register - [0:31] */
2547 #define ECI48_OUT_MASKMAGIC_HIWORD 0x55550000
2548 #define ECI_OUT_CHANNEL_MASK(ccrev) ((ccrev) < 35 ? 0xf : (ECI48_OUT_MASKMAGIC_HIWORD | 0xf000))
2549 #define ECI_OUT_CHANNEL_SHIFT(ccrev) ((ccrev) < 35 ? 0 : 12)
2550 #define ECI_OUT_BW_MASK(ccrev) ((ccrev) < 35 ? 0x70 : (ECI48_OUT_MASKMAGIC_HIWORD | 0xe00))
2551 #define ECI_OUT_BW_SHIFT(ccrev) ((ccrev) < 35 ? 4 : 9)
2552 #define ECI_OUT_ANTENNA_MASK(ccrev) ((ccrev) < 35 ? 0x80 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x100))
2553 #define ECI_OUT_ANTENNA_SHIFT(ccrev) ((ccrev) < 35 ? 7 : 8)
2554 #define ECI_OUT_SIMUL_TXRX_MASK(ccrev) \
2555 ((ccrev) < 35 ? 0x10000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x80))
2556 #define ECI_OUT_SIMUL_TXRX_SHIFT(ccrev) ((ccrev) < 35 ? 16 : 7)
2557 #define ECI_OUT_FM_DISABLE_MASK(ccrev) \
2558 ((ccrev) < 35 ? 0x40000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x40))
2559 #define ECI_OUT_FM_DISABLE_SHIFT(ccrev) ((ccrev) < 35 ? 18 : 6)
2560
2561 /* Indicate control of ECI bits between s/w and dot11mac.
2562 * 0 => FW control, 1=> MAC/ucode control
2563
2564 * Current assignment (ccrev >= 35):
2565 * 0 - TxConf (ucode)
2566 * 38 - FM disable (wl)
2567 * 39 - Allow sim rx (ucode)
2568 * 40 - Num antennas (wl)
2569 * 43:41 - WLAN channel exclusion BW (wl)
2570 * 47:44 - WLAN channel (wl)
2571 *
2572 * (ccrev < 35)
2573 * 15:0 - wl
2574 * 16 -
2575 * 18 - FM disable
2576 * 30 - wl interrupt
2577 * 31 - ucode interrupt
2578 * others - unassigned (presumed to be with dot11mac/ucode)
2579 */
2580 #define ECI_MACCTRL_BITS 0xbffb0000
2581 #define ECI_MACCTRLLO_BITS 0x1
2582 #define ECI_MACCTRLHI_BITS 0xFF
2583
2584 /* SECI configuration */
2585 #define SECI_MODE_UART 0x0
2586 #define SECI_MODE_SECI 0x1
2587 #define SECI_MODE_LEGACY_3WIRE_BT 0x2
2588 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3
2589 #define SECI_MODE_HALF_SECI 0x4
2590
2591 #define SECI_RESET (1 << 0)
2592 #define SECI_RESET_BAR_UART (1 << 1)
2593 #define SECI_ENAB_SECI_ECI (1 << 2)
2594 #define SECI_ENAB_SECIOUT_DIS (1 << 3)
2595 #define SECI_MODE_MASK 0x7
2596 #define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */
2597 #define SECI_UPD_SECI (1 << 7)
2598
2599 #define SECI_SIGNOFF_0 0xDB
2600 #define SECI_SIGNOFF_1 0
2601
2602 /* seci clk_ctl_st bits */
2603 #define CLKCTL_STS_SECI_CLK_REQ (1 << 8)
2604 #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24)
2605
2606 #define SECI_UART_MSR_CTS_STATE (1 << 0)
2607 #define SECI_UART_MSR_RTS_STATE (1 << 1)
2608 #define SECI_UART_SECI_IN_STATE (1 << 2)
2609 #define SECI_UART_SECI_IN2_STATE (1 << 3)
2610
2611 /* SECI UART LCR/MCR register bits */
2612 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */
2613 #define SECI_UART_LCR_PARITY_EN (1 << 1)
2614 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */
2615 #define SECI_UART_LCR_RX_EN (1 << 3)
2616 #define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */
2617 #define SECI_UART_LCR_TXO_EN (1 << 5)
2618 #define SECI_UART_LCR_RTSO_EN (1 << 6)
2619 #define SECI_UART_LCR_SLIPMODE_EN (1 << 7)
2620 #define SECI_UART_LCR_RXCRC_CHK (1 << 8)
2621 #define SECI_UART_LCR_TXCRC_INV (1 << 9)
2622 #define SECI_UART_LCR_TXCRC_LSBF (1 << 10)
2623 #define SECI_UART_LCR_TXCRC_EN (1 << 11)
2624
2625 #define SECI_UART_MCR_TX_EN (1 << 0)
2626 #define SECI_UART_MCR_PRTS (1 << 1)
2627 #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2)
2628 #define SECI_UART_MCR_HIGHRATE_EN (1 << 3)
2629 #define SECI_UART_MCR_LOOPBK_EN (1 << 4)
2630 #define SECI_UART_MCR_AUTO_RTS (1 << 5)
2631 #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6)
2632 #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7)
2633 #define SECI_UART_MCR_XONOFF_RPT (1 << 9)
2634
2635 /* WLAN channel numbers - used from wifi.h */
2636
2637 /* WLAN BW */
2638 #define ECI_BW_20 0x0
2639 #define ECI_BW_25 0x1
2640 #define ECI_BW_30 0x2
2641 #define ECI_BW_35 0x3
2642 #define ECI_BW_40 0x4
2643 #define ECI_BW_45 0x5
2644 #define ECI_BW_50 0x6
2645 #define ECI_BW_ALL 0x7
2646
2647 /* WLAN - number of antenna */
2648 #define WLAN_NUM_ANT1 TXANT_0
2649 #define WLAN_NUM_ANT2 TXANT_1
2650
2651 #endif /* _SBCHIPC_H */
Tomato firmware and modifications.