release/src-rt-6.x/cfe/cfe/usb/ohci.h

   1 /*  *********************************************************************
   2     *  Broadcom Common Firmware Environment (CFE)
   3     *
   4     *  OHCI defs                                File: ohci.h
   5     *
   6     *  Open Host controller interface definitions
   7     *
   8     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
   9     *
  10     *********************************************************************
  11     *
  12     *  Copyright 2000,2001,2002,2003
  13     *  Broadcom Corporation. All rights reserved.
  14     *
  15     *  This software is furnished under license and may be used and
  16     *  copied only in accordance with the following terms and
  17     *  conditions.  Subject to these conditions, you may download,
  18     *  copy, install, use, modify and distribute modified or unmodified
  19     *  copies of this software in source and/or binary form.  No title
  20     *  or ownership is transferred hereby.
  21     *
  22     *  1) Any source code used, modified or distributed must reproduce
  23     *     and retain this copyright notice and list of conditions
  24     *     as they appear in the source file.
  25     *
  26     *  2) No right is granted to use any trade name, trademark, or
  27     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  28     *     name may not be used to endorse or promote products derived
  29     *     from this software without the prior written permission of
  30     *     Broadcom Corporation.
  31     *
  32     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  33     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  34     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  35     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  36     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  37     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  38     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  39     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  40     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  41     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  42     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  43     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  44     *     THE POSSIBILITY OF SUCH DAMAGE.
  45     ********************************************************************* */
  46
  47
  48 /*  *********************************************************************
  49     *  Macros to muck with bitfields
  50     ********************************************************************* */
  51
  52 #define _OHCI_MAKE32(x) ((uint32_t)(x))
  53
  54 /*
  55  * Make a mask for 1 bit at position 'n'
  56  */
  57
  58 #define _OHCI_MAKEMASK1(n) (_OHCI_MAKE32(1) << _OHCI_MAKE32(n))
  59
  60 /*
  61  * Make a mask for 'v' bits at position 'n'
  62  */
  63
  64 #define _OHCI_MAKEMASK(v,n) (_OHCI_MAKE32((_OHCI_MAKE32(1)<<(v))-1) << _OHCI_MAKE32(n))
  65
  66 /*
  67  * Make a value at 'v' at bit position 'n'
  68  */
  69
  70 #define _OHCI_MAKEVALUE(v,n) (_OHCI_MAKE32(v) << _OHCI_MAKE32(n))
  71 #define _OHCI_GETVALUE(v,n,m) ((_OHCI_MAKE32(v) & _OHCI_MAKE32(m)) >> _OHCI_MAKE32(n))
  72
  73
  74
  75 /*  *********************************************************************
  76     *  Endpoint Descriptor (interrupt, bulk)
  77     ********************************************************************* */
  78
  79 #define OHCI_ED_ALIGN   32
  80
  81 typedef struct ohci_ed_s {
  82     uint32_t ed_control;
  83     uint32_t ed_tailp;
  84     uint32_t ed_headp;
  85     uint32_t ed_next_ed;
  86 } ohci_ed_t;
  87
  88 #define S_OHCI_ED_FA            0
  89 #define M_OHCI_ED_FA            _OHCI_MAKEMASK(7,S_OHCI_ED_FA)
  90 #define V_OHCI_ED_FA(x)         _OHCI_MAKEVALUE(x,S_OHCI_ED_FA)
  91 #define G_OHCI_ED_FA(x)         _OHCI_GETVALUE(x,S_OHCI_ED_FA,M_OHCI_ED_FA)
  92
  93 #define S_OHCI_ED_EN            7
  94 #define M_OHCI_ED_EN            _OHCI_MAKEMASK(4,S_OHCI_ED_EN)
  95 #define V_OHCI_ED_EN(x)         _OHCI_MAKEVALUE(x,S_OHCI_ED_EN)
  96 #define G_OHCI_ED_EN(x)         _OHCI_GETVALUE(x,S_OHCI_ED_EN,M_OHCI_ED_EN)
  97
  98 #define S_OHCI_ED_DIR           11
  99 #define M_OHCI_ED_DIR           _OHCI_MAKEMASK(2,S_OHCI_ED_DIR)
 100 #define V_OHCI_ED_DIR(x)        _OHCI_MAKEVALUE(x,S_OHCI_ED_DIR)
 101 #define G_OHCI_ED_DIR(x)        _OHCI_GETVALUE(x,S_OHCI_ED_DIR,M_OHCI_ED_DIR)
 102
 103 #define K_OHCI_ED_DIR_FROMTD    0
 104 #define K_OHCI_ED_DIR_OUT       1
 105 #define K_OHCI_ED_DIR_IN        2
 106
 107 #define M_OHCI_ED_LOWSPEED      _OHCI_MAKEMASK1(13)
 108 #define M_OHCI_ED_SKIP          _OHCI_MAKEMASK1(14)
 109 #define M_OHCI_ED_ISOCFMT       _OHCI_MAKEMASK1(15)
 110
 111 #define S_OHCI_ED_MPS           16
 112 #define M_OHCI_ED_MPS           _OHCI_MAKEMASK(11,S_OHCI_ED_MPS)
 113 #define V_OHCI_ED_MPS(x)        _OHCI_MAKEVALUE(x,S_OHCI_ED_MPS)
 114 #define G_OHCI_ED_MPS(x)        _OHCI_GETVALUE(x,S_OHCI_ED_MPS,M_OHCI_ED_MPS)
 115
 116 #define M_OHCI_ED_PTRMASK       0xFFFFFFF0
 117 #define M_OHCI_ED_HALT          _OHCI_MAKEMASK1(0)
 118 #define M_OHCI_ED_TOGGLECARRY   _OHCI_MAKEMASK1(1)
 119
 120 /*  *********************************************************************
 121     *  Transfer Descriptor
 122     ********************************************************************* */
 123
 124 #define OHCI_TD_ALIGN   32
 125
 126 typedef struct ohci_td_s {
 127     uint32_t td_control;
 128     uint32_t td_cbp;
 129     uint32_t td_next_td;
 130     uint32_t td_be;
 131 } ohci_td_t;
 132
 133 #define M_OHCI_TD_SHORTOK       _OHCI_MAKEMASK1(18)
 134
 135 #define S_OHCI_TD_PID           19
 136 #define M_OHCI_TD_PID           _OHCI_MAKEMASK(2,S_OHCI_TD_PID)
 137 #define V_OHCI_TD_PID(x)        _OHCI_MAKEVALUE(x,S_OHCI_TD_PID)
 138 #define G_OHCI_TD_PID(x)        _OHCI_GETVALUE(x,S_OHCI_TD_PID,M_OHCI_TD_PID)
 139
 140 #define K_OHCI_TD_SETUP         0
 141 #define K_OHCI_TD_OUT           1
 142 #define K_OHCI_TD_IN            2
 143 #define K_OHCI_TD_RESERVED      3
 144
 145 #define V_OHCI_TD_SETUP         V_OHCI_TD_PID(K_OHCI_TD_SETUP)
 146 #define V_OHCI_TD_OUT           V_OHCI_TD_PID(K_OHCI_TD_OUT)
 147 #define V_OHCI_TD_IN            V_OHCI_TD_PID(K_OHCI_TD_IN)
 148 #define V_OHCI_TD_RESERVED      V_OHCI_TD_PID(K_OHCI_TD_RESERVED)
 149
 150 #define S_OHCI_TD_DI            21
 151 #define M_OHCI_TD_DI            _OHCI_MAKEMASK(3,S_OHCI_TD_DI)
 152 #define V_OHCI_TD_DI(x)         _OHCI_MAKEVALUE(x,S_OHCI_TD_DI)
 153 #define G_OHCI_TD_DI(x)         _OHCI_GETVALUE(x,S_OHCI_TD_DI,M_OHCI_TD_DI)
 154
 155 #define K_OHCI_TD_NOINTR        7
 156 #define V_OHCI_TD_NOINTR        V_OHCI_TD_DI(K_OHCI_TD_NOINTR)
 157
 158 #define S_OHCI_TD_DT            24
 159 #define M_OHCI_TD_DT            _OHCI_MAKEMASK(2,S_OHCI_TD_DT)
 160 #define V_OHCI_TD_DT(x)         _OHCI_MAKEVALUE(x,S_OHCI_TD_DT)
 161 #define G_OHCI_TD_DT(x)         _OHCI_GETVALUE(x,S_OHCI_TD_DT,M_OHCI_TD_DT)
 162
 163 #define K_OHCI_TD_DT_DATA0      2
 164 #define K_OHCI_TD_DT_DATA1      3
 165 #define K_OHCI_TD_DT_TCARRY     0
 166
 167 #define S_OHCI_TD_EC            26
 168 #define M_OHCI_TD_EC            _OHCI_MAKEMASK(2,S_OHCI_TD_EC)
 169 #define V_OHCI_TD_EC(x)         _OHCI_MAKEVALUE(x,S_OHCI_TD_EC)
 170 #define G_OHCI_TD_EC(x)         _OHCI_GETVALUE(x,S_OHCI_TD_EC,M_OHCI_TD_EC)
 171
 172 #define S_OHCI_TD_CC            28
 173 #define M_OHCI_TD_CC            _OHCI_MAKEMASK(4,S_OHCI_TD_CC)
 174 #define V_OHCI_TD_CC(x)         _OHCI_MAKEVALUE(x,S_OHCI_TD_CC)
 175 #define G_OHCI_TD_CC(x)         _OHCI_GETVALUE(x,S_OHCI_TD_CC,M_OHCI_TD_CC)
 176
 177 #define K_OHCI_CC_NOERROR               0
 178 #define K_OHCI_CC_CRC                   1
 179 #define K_OHCI_CC_BITSTUFFING           2
 180 #define K_OHCI_CC_DATATOGGLEMISMATCH    3
 181 #define K_OHCI_CC_STALL                 4
 182 #define K_OHCI_CC_DEVICENOTRESPONDING   5
 183 #define K_OHCI_CC_PIDCHECKFAILURE       6
 184 #define K_OHCI_CC_UNEXPECTEDPID         7
 185 #define K_OHCI_CC_DATAOVERRUN           8
 186 #define K_OHCI_CC_DATAUNDERRUN          9
 187 #define K_OHCI_CC_BUFFEROVERRUN         12
 188 #define K_OHCI_CC_BUFFERUNDERRUN        13
 189 #define K_OHCI_CC_NOTACCESSED           15
 190
 191 #define K_OHCI_CC_CANCELLED             0xFF
 192
 193 #define OHCI_TD_MAX_DATA                8192
 194
 195
 196 /*  *********************************************************************
 197     *  Endpoint descriptor (isochronous)
 198     ********************************************************************* */
 199
 200 /*
 201  * TBA
 202  */
 203
 204 /*  *********************************************************************
 205     *  Host Controller Communications Area (HCCA)
 206     ********************************************************************* */
 207
 208 #define OHCI_INTTABLE_SIZE      32
 209
 210 #define OHCI_HCCA_ALIGN         256     /* Align on 256-byte boundary */
 211
 212 typedef struct ohci_hcca_s {
 213     uint32_t hcca_inttable[OHCI_INTTABLE_SIZE];
 214     uint32_t hcca_framenum;             /* note: actually two 16-bit fields */
 215     uint32_t hcca_donehead;
 216     uint32_t hcca_reserved[29];         /* round to 256 bytes */
 217     uint32_t hcca_pad;
 218 } ohci_hcca_t;
 219
 220 /*  *********************************************************************
 221     *  Registers
 222     ********************************************************************* */
 223
 224 #define _OHCI_REGIDX(x) ((x)*4)
 225
 226 #define R_OHCI_REVISION         _OHCI_REGIDX(0)
 227 #define R_OHCI_CONTROL          _OHCI_REGIDX(1)
 228 #define R_OHCI_CMDSTATUS        _OHCI_REGIDX(2)
 229 #define R_OHCI_INTSTATUS        _OHCI_REGIDX(3)
 230 #define R_OHCI_INTENABLE        _OHCI_REGIDX(4)
 231 #define R_OHCI_INTDISABLE       _OHCI_REGIDX(5)
 232 #define R_OHCI_HCCA             _OHCI_REGIDX(6)
 233 #define R_OHCI_PERIODCURRENTED  _OHCI_REGIDX(7)
 234 #define R_OHCI_CONTROLHEADED    _OHCI_REGIDX(8)
 235 #define R_OHCI_CONTROLCURRENTED _OHCI_REGIDX(9)
 236 #define R_OHCI_BULKHEADED       _OHCI_REGIDX(10)
 237 #define R_OHCI_BULKCURRENTED    _OHCI_REGIDX(11)
 238 #define R_OHCI_DONEHEAD         _OHCI_REGIDX(12)
 239 #define R_OHCI_FMINTERVAL       _OHCI_REGIDX(13)
 240 #define R_OHCI_FMREMAINING      _OHCI_REGIDX(14)
 241 #define R_OHCI_FMNUMBER         _OHCI_REGIDX(15)
 242 #define R_OHCI_PERIODICSTART    _OHCI_REGIDX(16)
 243 #define R_OHCI_LSTHRESHOLD      _OHCI_REGIDX(17)
 244 #define R_OHCI_RHDSCRA          _OHCI_REGIDX(18)
 245 #define R_OHCI_RHDSCRB          _OHCI_REGIDX(19)
 246 #define R_OHCI_RHSTATUS         _OHCI_REGIDX(20)
 247 #define R_OHCI_RHPORTSTATUS(x)  _OHCI_REGIDX(20+(x))    /* note: 1-based! */
 248
 249
 250 /*
 251  * R_OHCI_REVISION
 252  */
 253
 254 #define S_OHCI_REV_REV          0
 255 #define M_OHCI_REV_REV          _OHCI_MAKEMASK(8,S_OHCI_REV_REV)
 256 #define V_OHCI_REV_REV(x)       _OHCI_MAKEVALUE(x,S_OHCI_REV_REV)
 257 #define G_OHCI_REV_REV(x)       _OHCI_GETVALUE(x,S_OHCI_REV_REV,M_OHCI_REV_REV)
 258 #define K_OHCI_REV_11           0x10
 259
 260 /*
 261  * R_OHCI_CONTROL
 262  */
 263
 264 #define S_OHCI_CONTROL_CBSR     0
 265 #define M_OHCI_CONTROL_CBSR     _OHCI_MAKEMASK(2,S_OHCI_CONTROL_CBSR)
 266 #define V_OHCI_CONTROL_CBSR(x)  _OHCI_MAKEVALUE(x,S_OHCI_CONTROL_CBSR)
 267 #define G_OHCI_CONTROL_CBSR(x)  _OHCI_GETVALUE(x,S_OHCI_CONTROL_CBSR,M_OHCI_CONTROL_CBSR)
 268
 269 #define K_OHCI_CBSR_11          0
 270 #define K_OHCI_CBSR_21          1
 271 #define K_OHCI_CBSR_31          2
 272 #define K_OHCI_CBSR_41          3
 273
 274 #define M_OHCI_CONTROL_PLE      _OHCI_MAKEMASK1(2)
 275 #define M_OHCI_CONTROL_IE       _OHCI_MAKEMASK1(3)
 276 #define M_OHCI_CONTROL_CLE      _OHCI_MAKEMASK1(4)
 277 #define M_OHCI_CONTROL_BLE      _OHCI_MAKEMASK1(5)
 278
 279 #define S_OHCI_CONTROL_HCFS     6
 280 #define M_OHCI_CONTROL_HCFS     _OHCI_MAKEMASK(2,S_OHCI_CONTROL_HCFS)
 281 #define V_OHCI_CONTROL_HCFS(x)  _OHCI_MAKEVALUE(x,S_OHCI_CONTROL_HCFS)
 282 #define G_OHCI_CONTROL_HCFS(x)  _OHCI_GETVALUE(x,S_OHCI_CONTROL_HCFS,M_OHCI_CONTROL_HCFS)
 283
 284 #define K_OHCI_HCFS_RESET       0
 285 #define K_OHCI_HCFS_RESUME      1
 286 #define K_OHCI_HCFS_OPERATIONAL 2
 287 #define K_OHCI_HCFS_SUSPEND     3
 288
 289 #define M_OHCI_CONTROL_IR       _OHCI_MAKEMASK1(8)
 290 #define M_OHCI_CONTROL_RWC      _OHCI_MAKEMASK1(9)
 291 #define M_OHCI_CONTROL_RWE      _OHCI_MAKEMASK1(10)
 292
 293 /*
 294  * R_OHCI_CMDSTATUS
 295  */
 296
 297 #define M_OHCI_CMDSTATUS_HCR    _OHCI_MAKEMASK1(0)
 298 #define M_OHCI_CMDSTATUS_CLF    _OHCI_MAKEMASK1(1)
 299 #define M_OHCI_CMDSTATUS_BLF    _OHCI_MAKEMASK1(2)
 300 #define M_OHCI_CMDSTATUS_OCR    _OHCI_MAKEMASK1(3)
 301
 302 #define S_OHCI_CMDSTATUS_SOC    16
 303 #define M_OHCI_CMDSTATUS_SOC    _OHCI_MAKEMASK(2,S_OHCI_CMDSTATUS_SOC)
 304 #define V_OHCI_CMDSTATUS_SOC(x) _OHCI_MAKEVALUE(x,S_OHCI_CMDSTATUS_SOC)
 305 #define G_OHCI_CMDSTATUS_SOC(x) _OHCI_GETVALUE(x,S_OHCI_CMDSTATUS_SOC,M_OHCI_CMDSTATUS_SOC)
 306
 307 /*
 308  * R_OHCI_INTSTATUS, R_OHCI_INTENABLE, R_OHCI_INTDISABLE
 309  */
 310
 311
 312 #define M_OHCI_INT_SO           _OHCI_MAKEMASK1(0)
 313 #define M_OHCI_INT_WDH          _OHCI_MAKEMASK1(1)
 314 #define M_OHCI_INT_SF           _OHCI_MAKEMASK1(2)
 315 #define M_OHCI_INT_RD           _OHCI_MAKEMASK1(3)
 316 #define M_OHCI_INT_UE           _OHCI_MAKEMASK1(4)
 317 #define M_OHCI_INT_FNO          _OHCI_MAKEMASK1(5)
 318 #define M_OHCI_INT_RHSC         _OHCI_MAKEMASK1(6)
 319 #define M_OHCI_INT_OC           _OHCI_MAKEMASK1(30)
 320 #define M_OHCI_INT_MIE          _OHCI_MAKEMASK1(31)
 321
 322 #define M_OHCI_INT_ALL  M_OHCI_INT_SO | M_OHCI_INT_WDH | M_OHCI_INT_SF | \
 323                         M_OHCI_INT_RD | M_OHCI_INT_UE | M_OHCI_INT_FNO | \
 324                         M_OHCI_INT_RHSC | M_OHCI_INT_OC | M_OHCI_INT_MIE
 325
 326 /*
 327  * R_OHCI_FMINTERVAL
 328  */
 329
 330
 331 #define S_OHCI_FMINTERVAL_FI            0
 332 #define M_OHCI_FMINTERVAL_FI            _OHCI_MAKEMASK(14,S_OHCI_FMINTERVAL_FI)
 333 #define V_OHCI_FMINTERVAL_FI(x)         _OHCI_MAKEVALUE(x,S_OHCI_FMINTERVAL_FI)
 334 #define G_OHCI_FMINTERVAL_FI(x)         _OHCI_GETVALUE(x,S_OHCI_FMINTERVAL_FI,M_OHCI_FMINTERVAL_FI)
 335
 336 #define S_OHCI_FMINTERVAL_FSMPS         16
 337 #define M_OHCI_FMINTERVAL_FSMPS         _OHCI_MAKEMASK(15,S_OHCI_FMINTERVAL_FSMPS)
 338 #define V_OHCI_FMINTERVAL_FSMPS(x)      _OHCI_MAKEVALUE(x,S_OHCI_FMINTERVAL_FSMPS)
 339 #define G_OHCI_FMINTERVAL_FSMPS(x)      _OHCI_GETVALUE(x,S_OHCI_FMINTERVAL_FSMPS,M_OHCI_FMINTERVAL_FSMPS)
 340
 341 #define OHCI_CALC_FSMPS(x) ((((x)-210)*6/7))
 342
 343
 344 #define M_OHCI_FMINTERVAL_FIT           _OHCI_MAKEMASK1(31)
 345
 346 /*
 347  * R_OHCI_FMREMAINING
 348  */
 349
 350
 351 #define S_OHCI_FMREMAINING_FR           0
 352 #define M_OHCI_FMREMAINING_FR           _OHCI_MAKEMASK(14,S_OHCI_FMREMAINING_FR)
 353 #define V_OHCI_FMREMAINING_FR(x)        _OHCI_MAKEVALUE(x,S_OHCI_FMREMAINING_FR)
 354 #define G_OHCI_FMREMAINING_FR(x)        _OHCI_GETVALUE(x,S_OHCI_FMREMAINING_FR,M_OHCI_FMREMAINING_FR)
 355
 356 #define M_OHCI_FMREMAINING_FRT          _OHCI_MAKEMASK1(31)
 357
 358 /*
 359  * R_OHCI_RHDSCRA
 360  */
 361
 362
 363 #define S_OHCI_RHDSCRA_NDP      0
 364 #define M_OHCI_RHDSCRA_NDP      _OHCI_MAKEMASK(8,S_OHCI_RHDSCRA_NDP)
 365 #define V_OHCI_RHDSCRA_NDP(x)   _OHCI_MAKEVALUE(x,S_OHCI_RHDSCRA_NDP)
 366 #define G_OHCI_RHDSCRA_NDP(x)   _OHCI_GETVALUE(x,S_OHCI_RHDSCRA_NDP,M_OHCI_RHDSCRA_NDP)
 367
 368 #define M_OHCI_RHDSCRA_PSM      _OHCI_MAKEMASK1(8)
 369 #define M_OHCI_RHDSCRA_NPS      _OHCI_MAKEMASK1(9)
 370 #define M_OHCI_RHDSCRA_DT       _OHCI_MAKEMASK1(10)
 371 #define M_OHCI_RHDSCRA_OCPM     _OHCI_MAKEMASK1(11)
 372 #define M_OHCI_RHDSCRA_NOCP     _OHCI_MAKEMASK1(12)
 373
 374 #define S_OHCI_RHDSCRA_POTPGT    24
 375 #define M_OHCI_RHDSCRA_POTPGT    _OHCI_MAKEMASK(8,S_OHCI_RHDSCRA_POTPGT)
 376 #define V_OHCI_RHDSCRA_POTPGT(x) _OHCI_MAKEVALUE(x,S_OHCI_RHDSCRA_POTPGT)
 377 #define G_OHCI_RHDSCRA_POTPGT(x) _OHCI_GETVALUE(x,S_OHCI_RHDSCRA_POTPGT,M_OHCI_RHDSCRA_POTPGT)
 378
 379 /*
 380  * R_OHCI_RHDSCRB
 381  */
 382
 383 #define S_OHCI_RHDSCRB_DR       0
 384 #define M_OHCI_RHDSCRB_DR       _OHCI_MAKEMASK(16,S_OHCI_RHDSCRB_DR)
 385 #define V_OHCI_RHDSCRB_DR(x)    _OHCI_MAKEVALUE(x,S_OHCI_RHDSCRB_DR)
 386 #define G_OHCI_RHDSCRB_DR(x)    _OHCI_GETVALUE(x,S_OHCI_RHDSCRB_DR,M_OHCI_RHDSCRB_DR)
 387
 388 #define S_OHCI_RHDSCRB_PPCM     16
 389 #define M_OHCI_RHDSCRB_PPCM     _OHCI_MAKEMASK(16,S_OHCI_RHDSCRB_PPCM)
 390 #define V_OHCI_RHDSCRB_PPCM(x)  _OHCI_MAKEVALUE(x,S_OHCI_RHDSCRB_PPCM)
 391 #define G_OHCI_RHDSCRB_PPCM(x)  _OHCI_GETVALUE(x,S_OHCI_RHDSCRB_PPCM,M_OHCI_RHDSCRB_PPCM)
 392
 393 /*
 394  * R_OHCI_RHSTATUS
 395  */
 396
 397 #define M_OHCI_RHSTATUS_LPS     _OHCI_MAKEMASK1(0)
 398 #define M_OHCI_RHSTATUS_OCI     _OHCI_MAKEMASK1(1)
 399 #define M_OHCI_RHSTATUS_DRWE    _OHCI_MAKEMASK1(15)
 400 #define M_OHCI_RHSTATUS_LPSC    _OHCI_MAKEMASK1(16)
 401 #define M_OHCI_RHSTATUS_OCIC    _OHCI_MAKEMASK1(17)
 402 #define M_OHCI_RHSTATUS_CRWE    _OHCI_MAKEMASK1(31)
 403
 404 /*
 405  * R_OHCI_RHPORTSTATUS
 406  */
 407
 408 #define M_OHCI_RHPORTSTAT_CCS   _OHCI_MAKEMASK1(0)
 409 #define M_OHCI_RHPORTSTAT_PES   _OHCI_MAKEMASK1(1)
 410 #define M_OHCI_RHPORTSTAT_PSS   _OHCI_MAKEMASK1(2)
 411 #define M_OHCI_RHPORTSTAT_POCI  _OHCI_MAKEMASK1(3)
 412 #define M_OHCI_RHPORTSTAT_PRS   _OHCI_MAKEMASK1(4)
 413 #define M_OHCI_RHPORTSTAT_PPS   _OHCI_MAKEMASK1(8)
 414 #define M_OHCI_RHPORTSTAT_LSDA  _OHCI_MAKEMASK1(9)
 415 #define M_OHCI_RHPORTSTAT_CSC   _OHCI_MAKEMASK1(16)
 416 #define M_OHCI_RHPORTSTAT_PESC  _OHCI_MAKEMASK1(17)
 417 #define M_OHCI_RHPORTSTAT_PSSC  _OHCI_MAKEMASK1(18)
 418 #define M_OHCI_RHPORTSTAT_OCIC  _OHCI_MAKEMASK1(19)
 419 #define M_OHCI_RHPORTSTAT_PRSC  _OHCI_MAKEMASK1(20)
 420
 421 #define M_OHCI_RHPORTSTAT_ALLC (M_OHCI_RHPORTSTAT_CSC | \
 422                                 M_OHCI_RHPORTSTAT_PSSC | \
 423                                 M_OHCI_RHPORTSTAT_OCIC | \
 424                                 M_OHCI_RHPORTSTAT_PRSC)
 425
 426 /*  *********************************************************************
 427     *  OHCI Structures
 428     ********************************************************************* */
 429
 430 #define beginningof(ptr,type,field) ((type *) (((int) (ptr)) - ((int) ((type *) 0)->field)))
 431
 432 #define OHCI_INTTREE_SIZE       63
 433
 434 #define OHCI_EDPOOL_SIZE        128
 435 #define OHCI_TDPOOL_SIZE        32
 436
 437 typedef struct ohci_endpoint_s {
 438     struct ohci_endpoint_s *ep_next;
 439     uint32_t ep_phys;
 440     int ep_flags;
 441     int ep_mps;
 442     int ep_num;
 443 } ohci_endpoint_t;
 444
 445 typedef struct ohci_transfer_s {
 446     void *t_ref;
 447     int t_length;
 448     struct ohci_transfer_s *t_next;
 449 } ohci_transfer_t;
 450
 451 typedef struct ohci_softc_s {
 452     ohci_endpoint_t *ohci_edtable[OHCI_INTTREE_SIZE];
 453     ohci_endpoint_t *ohci_inttable[OHCI_INTTABLE_SIZE];
 454     ohci_endpoint_t *ohci_isoc_list;
 455     ohci_endpoint_t *ohci_ctl_list;
 456     ohci_endpoint_t *ohci_bulk_list;
 457     ohci_hcca_t *ohci_hcca;
 458     ohci_endpoint_t *ohci_endpoint_pool;
 459     ohci_transfer_t *ohci_transfer_pool;
 460     ohci_ed_t *ohci_hwedpool;
 461     ohci_td_t *ohci_hwtdpool;
 462     ohci_endpoint_t *ohci_endpoint_freelist;
 463     ohci_transfer_t *ohci_transfer_freelist;
 464 #ifdef _CFE_
 465     physaddr_t ohci_regs;
 466 #else
 467     volatile uint32_t *ohci_regs;
 468 #endif
 469     int ohci_ndp;
 470     long ohci_addr;
 471     uint32_t ohci_intdisable;
 472
 473     int ohci_rh_newaddr;        /* Address to be set on next status update */
 474     int ohci_rh_addr;           /* address of root hub */
 475     int ohci_rh_conf;           /* current configuration # */
 476     uint8_t ohci_rh_buf[128];   /* buffer to hold hub responses */
 477     uint8_t *ohci_rh_ptr;       /* pointer into buffer */
 478     int ohci_rh_len;            /* remaining bytes to transfer */
 479     queue_t ohci_rh_intrq;      /* Interrupt request queue */
 480     usbbus_t *ohci_bus;         /* owning usbbus structure */
 481
 482 } ohci_softc_t;
 483
 484
 485 /*
 486  * Misc stuff
 487  */
 488 #define OHCI_RESET_DELAY        10