release/src-rt-6.x/cfe/cfe/net/mii.h

   1 /*  *********************************************************************
   2     *  Broadcom Common Firmware Environment (CFE)
   3     *
   4     *  MII register definitions                 File: mii.h
   5     *
   6     *  Register and bit definitions for the standard MII management
   7     *  interface.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48 #ifndef _MII_H_
  49 #define _MII_H_
  50
  51 /* Access/command codes */
  52
  53 #define MII_COMMAND_START       0x01
  54 #define MII_COMMAND_READ        0x02
  55 #define MII_COMMAND_WRITE       0x01
  56 #define MII_COMMAND_ACK         0x02
  57
  58
  59 /* Registers */
  60
  61 #define MII_BMCR        0x00    /* Basic Mode Control (rw) */
  62 #define MII_BMSR        0x01    /* Basic Mode Status (ro) */
  63 #define MII_PHYIDR1     0x02
  64 #define MII_PHYIDR2     0x03
  65 #define MII_ANAR        0x04    /* Autonegotiation Advertisement */
  66 #define MII_ANLPAR      0x05    /* Autonegotiation Link Partner Ability (rw) */
  67 #define MII_ANER        0x06    /* Autonegotiation Expansion */
  68 #define MII_K1CTL       0x09    /* 1000baseT control */
  69 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
  70 #define MII_AUXCTL      0x18    /* aux control register */
  71 #define MII_SHADOW      0x1C    /* shadow control register */
  72
  73 /* Basic Mode Control register (RW) */
  74
  75 #define BMCR_RESET              0x8000
  76 #define BMCR_LOOPBACK           0x4000
  77 #define BMCR_SPEED0             0x2000
  78 #define BMCR_ANENABLE           0x1000
  79 #define BMCR_POWERDOWN          0x0800
  80 #define BMCR_ISOLATE            0x0400
  81 #define BMCR_RESTARTAN          0x0200
  82 #define BMCR_DUPLEX             0x0100
  83 #define BMCR_COLTEST            0x0080
  84 #define BMCR_SPEED1             0x0040
  85 #define BMCR_SPEED1000          (BMCR_SPEED1)
  86 #define BMCR_SPEED100           (BMCR_SPEED0)
  87 #define BMCR_SPEED10            0
  88
  89
  90 /* Basic Mode Status register (RO) */
  91
  92 #define BMSR_100BT4             0x8000
  93 #define BMSR_100BT_FDX          0x4000
  94 #define BMSR_100BT_HDX          0x2000
  95 #define BMSR_10BT_FDX           0x1000
  96 #define BMSR_10BT_HDX           0x0800
  97 #define BMSR_100BT2_FDX         0x0400
  98 #define BMSR_100BT2_HDX         0x0200
  99 #define BMSR_1000BT_XSR         0x0100
 100 #define BMSR_PRESUP             0x0040
 101 #define BMSR_ANCOMPLETE         0x0020
 102 #define BMSR_REMFAULT           0x0010
 103 #define BMSR_AUTONEG            0x0008
 104 #define BMSR_LINKSTAT           0x0004
 105 #define BMSR_JABDETECT          0x0002
 106 #define BMSR_EXTCAPAB           0x0001
 107
 108
 109 /* PHY Identifer registers (RO) */
 110
 111 #define PHYIDR1                 0x2000
 112 #define PHYIDR2                 0x5C60
 113
 114
 115 /* Autonegotiation Advertisement register (RW) */
 116
 117 #define ANAR_NP                 0x8000
 118 #define ANAR_RF                 0x2000
 119 #define ANAR_ASYPAUSE           0x0800
 120 #define ANAR_PAUSE              0x0400
 121 #define ANAR_T4                 0x0200
 122 #define ANAR_TXFD               0x0100
 123 #define ANAR_TXHD               0x0080
 124 #define ANAR_10FD               0x0040
 125 #define ANAR_10HD               0x0020
 126 #define ANAR_PSB                0x001F
 127
 128 #define PSB_802_3               0x0001  /* 802.3 */
 129
 130 /* Autonegotiation Link Partner Abilities register (RW) */
 131
 132 #define ANLPAR_NP               0x8000
 133 #define ANLPAR_ACK              0x4000
 134 #define ANLPAR_RF               0x2000
 135 #define ANLPAR_ASYPAUSE         0x0800
 136 #define ANLPAR_PAUSE            0x0400
 137 #define ANLPAR_T4               0x0200
 138 #define ANLPAR_TXFD             0x0100
 139 #define ANLPAR_TXHD             0x0080
 140 #define ANLPAR_10FD             0x0040
 141 #define ANLPAR_10HD             0x0020
 142 #define ANLPAR_PSB              0x001F
 143
 144
 145 /* Autonegotiation Expansion register (RO) */
 146
 147 #define ANER_PDF                0x0010
 148 #define ANER_LPNPABLE           0x0008
 149 #define ANER_NPABLE             0x0004
 150 #define ANER_PAGERX             0x0002
 151 #define ANER_LPANABLE           0x0001
 152
 153
 154 #define ANNPTR_NP               0x8000
 155 #define ANNPTR_MP               0x2000
 156 #define ANNPTR_ACK2             0x1000
 157 #define ANNPTR_TOGTX            0x0800
 158 #define ANNPTR_CODE             0x0008
 159
 160 #define ANNPRR_NP               0x8000
 161 #define ANNPRR_MP               0x2000
 162 #define ANNPRR_ACK3             0x1000
 163 #define ANNPRR_TOGTX            0x0800
 164 #define ANNPRR_CODE             0x0008
 165
 166
 167 #define K1TCR_TESTMODE          0x0000
 168 #define K1TCR_MSMCE             0x1000
 169 #define K1TCR_MSCV              0x0800
 170 #define K1TCR_RPTR              0x0400
 171 #define K1TCR_1000BT_FDX        0x200
 172 #define K1TCR_1000BT_HDX        0x100
 173
 174 #define K1STSR_MSMCFLT          0x8000
 175 #define K1STSR_MSCFGRES         0x4000
 176 #define K1STSR_LRSTAT           0x2000
 177 #define K1STSR_RRSTAT           0x1000
 178 #define K1STSR_LP1KFD           0x0800
 179 #define K1STSR_LP1KHD           0x0400
 180 #define K1STSR_LPASMDIR         0x0200
 181
 182 #define K1SCR_1KX_FDX           0x8000
 183 #define K1SCR_1KX_HDX           0x4000
 184 #define K1SCR_1KT_FDX           0x2000
 185 #define K1SCR_1KT_HDX           0x1000
 186
 187 /* Shadow Register 0x1C */
 188 #define SHDW_SPR_CTRL   0x100C  /* shadow (1c) reg 00100 mask */
 189 #define SHDW_WR_EN      0x8000  /* shadow (1c) write enable bit mask */
 190 #define SHDW_NRG_DET    0x0002  /* shadow (1c) reg 00100 energy detect bit mask */
 191
 192 #endif /* _MII_H_ */