release/src-rt-6.x/cfe/cfe/arch/mips/cpu/rm7000/src/rm7000_l2cache.S

   1 /*  *********************************************************************
   2     *  RM7000 Board Support Package
   3     *
   4     *  L2 Cache initialization                  File: rm7000_l2cache.S
   5     *
   6     *  This module contains code to initialize the L1 cache.
   7     *
   8     *  Note: all the routines in this module rely on registers only,
   9     *        since DRAM may not be active yet.
  10     *
  11     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  12     *
  13     *********************************************************************
  14     *
  15     *  Copyright 2000,2001,2002,2003
  16     *  Broadcom Corporation. All rights reserved.
  17     *
  18     *  This software is furnished under license and may be used and
  19     *  copied only in accordance with the following terms and
  20     *  conditions.  Subject to these conditions, you may download,
  21     *  copy, install, use, modify and distribute modified or unmodified
  22     *  copies of this software in source and/or binary form.  No title
  23     *  or ownership is transferred hereby.
  24     *
  25     *  1) Any source code used, modified or distributed must reproduce
  26     *     and retain this copyright notice and list of conditions
  27     *     as they appear in the source file.
  28     *
  29     *  2) No right is granted to use any trade name, trademark, or
  30     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  31     *     name may not be used to endorse or promote products derived
  32     *     from this software without the prior written permission of
  33     *     Broadcom Corporation.
  34     *
  35     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  36     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  37     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  39     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  40     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  41     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  42     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  43     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  44     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  45     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  46     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  47     *     THE POSSIBILITY OF SUCH DAMAGE.
  48     ********************************************************************* */
  49
  50 #include "sbmips.h"
  51
  52                 .text
  53
  54
  55 /*  *********************************************************************
  56     *  Macros
  57     ********************************************************************* */
  58
  59 #define L2CACHE_NUMWAYS 4
  60 #define L2CACHE_NUMIDX  128                     /* RM7000 has only 16K */
  61 #define L2CACHE_LINESIZE 32
  62 #define L2CACHE_IDXHIGH (L2CACHE_LINESIZE*L2CACHE_NUMWAYS*L2CACHE_NUMIDX)
  63
  64 #define L2CACHEOP(cachename,op) ((cachename) | ((op) << 2))
  65
  66 #define L2C_OP_IDXINVAL     0
  67 #define L2C_OP_IDXLOADTAG   1
  68 #define L2C_OP_IDXSTORETAG  2
  69 #define L2C_OP_IMPLRSVD     3
  70 #define L2C_OP_HITINVAL     4
  71 #define L2C_OP_FILL         5
  72 #define L2C_OP_HITWRITEBACK 6
  73 #define L2C_OP_FETCHLOCK    7
  74
  75 #define L2C                 3
  76
  77
  78
  79 /*  *********************************************************************
  80     *  RM7000_L2CACHE_INIT()
  81     *
  82     *  Initialize the L1 Cache tags to be "invalid"
  83     *
  84     *  Input parameters:
  85     *      nothing
  86     *
  87     *  Return value:
  88     *      nothing
  89     *
  90     *  Registers used:
  91     *      t0,t1,t2,t3
  92     ********************************************************************* */
  93
  94
  95 LEAF(rm7000_l2cache_init)
  96
  97                 dmtc0   zero,C0_TAGLO
  98                 dmtc0   zero,C0_TAGHI
  99
 100
 101                 li      t2,K1BASE
 102                 li      t3,L2CACHE_IDXHIGH
 103
 104                 add     t0,t2,t3
 105 1:              cache   L2CACHEOP(L2C,L2C_OP_IDXSTORETAG),0(t2)
 106                 addu    t2,L2CACHE_LINESIZE
 107                 bne     t0,t2,1b
 108
 109                 dmtc0   zero,C0_TAGLO,2
 110                 dmtc0   zero,C0_TAGHI,2
 111
 112                 li      t2,K1BASE
 113                 add     t0,t2,t3
 114 1:              cache   L2CACHEOP(L2C,L2C_OP_IDXSTORETAG),0(t2)
 115                 addu    t2,L2CACHE_LINESIZE
 116                 bne     t0,t2,1b
 117
 118                 mfc0    t0,C0_CONFIG
 119                 li      t1,0x7FFFFFFF
 120                 and     t0,t0,t1
 121                 mtc0    t0,C0_CONFIG
 122
 123                 j       ra
 124
 125 END(rm7000_l2cache_init)
 126
 127
 128 /*  *********************************************************************
 129     *  RM7000_L2CACHE_INVAL_I()
 130     *
 131     *  Invalidate the L1 ICache
 132     *
 133     *  Input parameters:
 134     *      nothing
 135     *
 136     *  Return value:
 137     *      nothing
 138     *
 139     *  Registers used:
 140     *      t0,t1,t2,t3
 141     ********************************************************************* */
 142
 143
 144 LEAF(rm7000_l2cache_inval_i)
 145
 146
 147                 li      t2,K1BASE
 148                 li      t3,L2CACHE_IDXHIGH
 149
 150                 add     t0,t2,t3
 151 1:              cache   L2CACHEOP(L2C,L2C_OP_IDXINVAL),0(t2)
 152                 addu    t2,L2CACHE_LINESIZE
 153                 bne     t0,t2,1b
 154
 155                 j       ra
 156
 157 END(rm7000_l2cache_inval_i)
 158
 159
 160 /*  *********************************************************************
 161     *  RM7000_L2CACHE_FLUSH_D()
 162     *
 163     *  Flush the entire L1 DCache (write dirty lines back to memory)
 164     *
 165     *  Input parameters:
 166     *      nothing
 167     *
 168     *  Return value:
 169     *      nothing
 170     *
 171     *  Registers used:
 172     *      t0,t1,t2,t3
 173     ********************************************************************* */
 174
 175
 176 LEAF(rm7000_l2cache_flush)
 177
 178                 li      t2,K1BASE
 179                 li      t3,L2CACHE_IDXHIGH
 180
 181                 li      t2,K1BASE
 182                 add     t0,t2,t3
 183 1:              cache   L2CACHEOP(L2C,L2C_OP_IDXINVAL),0(t2)
 184                 addu    t2,L2CACHE_LINESIZE
 185                 bne     t0,t2,1b
 186
 187                 j       ra
 188
 189 END(rm7000_l2cache_flush)
 190
 191
 192 /*  *********************************************************************
 193     *  End
 194     ********************************************************************* */