1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * Board-specific initialization File: PT1125_INIT.S
6 * This module contains the assembly-language part of the init
7 * code for this board support package. The routine
8 * "board_earlyinit" lives here.
10 * Author: Mitch Lichtenberg (mpl@broadcom.com)
12 * modification history
13 * --------------------
14 * 01a,01aug02,gtb Ported from pt1120_init.S.
16 *********************************************************************
19 * Broadcom Corporation. All rights reserved.
21 * This software is furnished under license and may be used and
22 * copied only in accordance with the following terms and
23 * conditions. Subject to these conditions, you may download,
24 * copy, install, use, modify and distribute modified or unmodified
25 * copies of this software in source and/or binary form. No title
26 * or ownership is transferred hereby.
28 * 1) Any source code used, modified or distributed must reproduce
29 * and retain this copyright notice and list of conditions as
30 * they appear in the source file.
32 * 2) No right is granted to use any trade name, trademark, or
33 * logo of Broadcom Corporation. Neither the "Broadcom
34 * Corporation" name nor any trademark or logo of Broadcom
35 * Corporation may be used to endorse or promote products
36 * derived from this software without the prior written
37 * permission of Broadcom Corporation.
39 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
40 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
41 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
42 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
43 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
44 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
47 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
48 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
49 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
50 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
51 * THE POSSIBILITY OF SUCH DAMAGE.
52 ********************************************************************* */
56 #include "sb1250_genbus.h"
57 #include "sb1250_regs.h"
58 #include "sb1250_scd.h"
59 #include "bsp_config.h"
61 #include "sb1250_draminit.h"
62 #include "../dev/ns16550.h"
64 #if defined(_PT1125_DIAG_CFG_)
65 #undef SERIAL_PORT_LEDS
66 #define SERIAL_PORT_LEDS
70 /* *********************************************************************
72 ********************************************************************* */
76 #define CALLKSEG1(x) la k0,x ; or k0,K1BASE ; jal k0
78 #define CALLKSEG1(x) jal x
82 /* *********************************************************************
85 * Initialize board registers. This is the earliest
86 * time the BSP gets control. This routine cannot assume that
87 * memory is operational, and therefore all code in this routine
88 * must run from registers only. The $ra register must not
89 * be modified, as it contains the return address.
91 * This routine will be called from uncached space, before
92 * the caches are initialized. If you want to make
93 * subroutine calls from here, you must use the CALLKSEG1 macro.
95 * Among other things, this is where the GPIO registers get
96 * programmed to make on-board LEDs function, or other startup
97 * that has to be done before anything will work.
104 ********************************************************************* */
106 LEAF(board_earlyinit)
109 # Configure the GPIOs
112 # 1, 2, and 5 are interrupts
113 # remainder are input (unused)
116 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
117 li t1,GPIO_OUTPUT_MASK
120 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
121 li t1,GPIO_INTERRUPT_MASK
125 # Turn on the diagnostic LED
127 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
128 li t1,M_GPIO_DEBUG_LED
135 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
136 li t1,LEDS_PHYS >> S_IO_ADDRBASE
137 sd t1,R_IO_EXT_START_ADDR(t0)
139 li t1,LEDS_SIZE-1 /* Needs to be 1 smaller, se UM for details */
140 sd t1,R_IO_EXT_MULT_SIZE(t0)
143 sd t1,R_IO_EXT_TIME_CFG0(t0)
146 sd t1,R_IO_EXT_TIME_CFG1(t0)
149 sd t1,R_IO_EXT_CFG(t0)
152 # Configure the alternate boot ROM
155 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
157 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE
158 sd t1,R_IO_EXT_START_ADDR(t0)
160 li t1,ALT_BOOTROM_SIZE-1
161 sd t1,R_IO_EXT_MULT_SIZE(t0)
163 li t1,ALT_BOOTROM_TIMING0
164 sd t1,R_IO_EXT_TIME_CFG0(t0)
166 li t1,ALT_BOOTROM_TIMING1
167 sd t1,R_IO_EXT_TIME_CFG1(t0)
169 li t1,ALT_BOOTROM_CONFIG
170 sd t1,R_IO_EXT_CFG(t0)
173 # Configure I/O bus for an external UART
176 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(UART_CS))
178 li t1, UART_PHYS >> S_IO_ADDRBASE
179 sd t1,R_IO_EXT_START_ADDR(t0)
182 sd t1,R_IO_EXT_MULT_SIZE(t0)
184 li t1, (UART_TIMING0)
185 sd t1,R_IO_EXT_TIME_CFG0(t0)
187 li t1, (UART_TIMING1)
188 sd t1,R_IO_EXT_TIME_CFG1(t0)
191 sd t1,R_IO_EXT_CFG(t0)
193 #ifdef SERIAL_PORT_LEDS
196 * Initialize the UART well enough to output characters.
198 li t0, PHYS_TO_K1(UART_PHYS)
201 sb t1, R_UART_CFCR(t0)
203 li t1, BRTC(CFG_SERIAL_BAUD_RATE)
204 sb t1, R_UART_DATA(t0)
206 sb t1, R_UART_IER(t0)
209 sb t1, R_UART_CFCR(t0)
211 li t1, (MCR_DTR | MCR_RTS | MCR_IENABLE)
212 sb t1, R_UART_MCR(t0)
215 sb t1, R_UART_IER(t0)
218 sb t1, R_UART_FIFO(t0)
225 li t1, (FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST \
227 sb t1, R_UART_FIFO(t0)
234 /* if (value & MASK) != MASK, write 0 to fifo reg. */
235 lb t1, R_UART_IIR(t0)
236 andi t1, t1, IIR_FIFO_MASK
237 xori t1, t1, IIR_FIFO_MASK
241 sb t1, R_UART_FIFO(t0)
246 * If the CPU is a 1250 or hybrid, certain initialization has
247 * to be done so that the chip can be used like an 112x.
250 /* First, figure out what type of SOC we're on. */
251 ld t1, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
253 bne t3, K_SYS_SOC_TYPE_BCM1250, is_bcm112x
256 * We have a 1250 or hybrid. Initialize registers as appropriate.
260 * If we're not already running as a uniprocessor, get us there.
262 dsrl t1, t1, S_SYS_PART # part number now in t1
264 dsrl t3, t3, 8 # t3 = numcpus
266 ld t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
267 or t4, t4, M_SYS_SB_SOFTRES
268 xor t4, t4, M_SYS_SB_SOFTRES
269 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* clear soft reset */
273 or t4, t4, M_SYS_SB_SOFTRES | M_SYS_UNICPU0
274 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* go unicpu */
284 li t0, PHYS_TO_K1(A_MC_BASE_0)
285 dli t1, V_MC_CONFIG_DEFAULT | M_MC_ECC_DISABLE | \
287 sd t1, R_MC_CONFIG(t0)
288 sd zero, R_MC_CS_START(t0)
289 sd zero, R_MC_CS_END(t0)
290 sd zero, R_MC_CS_INTERLEAVE(t0)
291 sd zero, R_MC_CS_ATTR(t0)
292 sd zero, R_MC_TEST_DATA(t0)
293 sd zero, R_MC_TEST_ECC(t0)
296 * Zero out MAC 2's address register. (This has
297 * undefined value after reset, but OSes may check
298 * it on some parts to see if they should init
299 * the interface. This is a convenient place
303 li t0, PHYS_TO_K1(A_MAC_BASE_2)
304 sd zero, R_MAC_ETHERNET_ADDR(t0)
314 /* *********************************************************************
317 * Return the address of the DRAM information table
323 * v0 - DRAM info table, return 0 to use default table
324 ********************************************************************* */
326 #define _HARDWIRED_MEMORY_TABLE 1
328 #define CFG_DRAM_tROUNDTRIP DRT10(2,0)
329 /* CFG_DRAM_MIN_tMEMCLK must be set to 7. Some DIMMS cause diag failures
330 when the memclk is at 125 MHz but pass at 100 MHz or 133 MHz. Setting to 7 causes
331 memclk to be 133 MHz*/
332 #define CFG_DRAM_MIN_tMEMCLK DRT10(7,0)
333 #define DEVADDR (CFG_DRAM_SMBUS_BASE)
334 #define DEFCHAN (CFG_DRAM_SMBUS_CHANNEL)
337 #define LOADREL(reg,label) \
346 #define LOADREL(reg,label) \
354 #ifdef _HARDWIRED_MEMORY_TABLE
357 move v0,zero # auto configure
365 DRAM_GLOBALS(0) /* no port interleaving */
368 * Memory channel 0: Configure via SMBUS, Automatic Timing
369 * Assumes SMBus device numbers are arranged such
370 * that the first two addresses are CS0,1 and CS2,3 on MC0
371 * and the second two addresses are CS0,1 and CS2,3 on MC1
373 DRAM_CHAN_CFG2(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, CFG_DRAM_tROUNDTRIP, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
377 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+2)
378 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+3)
387 #ifdef SERIAL_PORT_LEDS
388 /* *********************************************************************
389 * BOARD_UART_TXCHAR(x)
391 * Transmit one character out the UART on the GENERIC bus.
394 * a0 - 8 bit character value.
401 ********************************************************************* */
403 LEAF(board_uart_txchar)
405 # Wait until there is space in the transmit buffer.
407 li t0, PHYS_TO_K1(UART_PHYS)
409 1: lb t1, R_UART_LSR(t0)
410 andi t1, t1, LSR_TXRDY
413 # OK, now send a character.
415 sb a0, R_UART_DATA(t0)
421 END(board_uart_txchar)
425 /* *********************************************************************
428 * Set LEDs for boot-time progress indication. Not used if
429 * the board does not have progress LEDs. This routine
430 * must not call any other routines, since it may be invoked
431 * either from KSEG0 or KSEG1 and it may be invoked
432 * whether or not the icache is operational.
435 * a0 - LED value (8 bits per character, 4 characters)
442 ********************************************************************* */
445 #define LED_CHAR0 (32+8*3)
446 #define LED_CHAR1 (32+8*2)
447 #define LED_CHAR2 (32+8*1)
448 #define LED_CHAR3 (32+8*0)
450 #ifdef SERIAL_PORT_LEDS
451 #define OUTPUT_CHAR(offset) \
452 li t0, PHYS_TO_K1(LEDS_PHYS) ; \
453 sb a0, offset(t0) ; \
454 bal board_uart_txchar
456 #define OUTPUT_CHAR(offset) \
457 li t0, PHYS_TO_K1(LEDS_PHYS) ; \
466 #ifdef SERIAL_PORT_LEDS
468 bal board_uart_txchar
473 OUTPUT_CHAR(LED_CHAR0)
476 OUTPUT_CHAR(LED_CHAR1)
479 OUTPUT_CHAR(LED_CHAR2)
482 OUTPUT_CHAR(LED_CHAR3)
484 #ifdef SERIAL_PORT_LEDS
486 bal board_uart_txchar
488 bal board_uart_txchar
490 bal board_uart_txchar
498 /* *********************************************************************
501 * Change the size of the bootrom area.
502 * This routine is called only after CFE has been relocated to DRAM
503 * and is executing from DRAM. After that point, the boot rom
504 * is serving as a flash file storage area. Note: this could be
505 * done in board_earlyinit since we're not changing the base address.
515 ********************************************************************* */
518 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BOOTROM_CS))
521 sd t1,R_IO_EXT_MULT_SIZE(t0)
526 /* *********************************************************************
529 * Change the size of the flash area.
530 * Usually CS1 is the promice, but if it's not, the flash is here.
540 ********************************************************************* */
543 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
546 sd t1,R_IO_EXT_MULT_SIZE(t0)