release/src-rt-6.x/cfe/cfe/arch/mips/board/bcm97115/src/bcm97115_init.S

   1 #include "sbmips.h"
   2 #include "bsp_config.h"
   3 #include "bcm97115.h"
   4
   5 #ifdef SERIALLEDS
   6                 #include "bcm97115_uart.h"
   7 #endif
   8
   9
  10 /*  *********************************************************************
  11     *  BOARD_EARLYINIT()
  12     *
  13     *  Initialize board registers.  This is the earliest
  14     *  time the BSP gets control.  This routine cannot assume that
  15     *  memory is operational, and therefore all code in this routine
  16     *  must run from registers only.  The $ra register must not
  17     *  be modified, as it contains the return address.
  18     *
  19     *  This routine will be called from uncached space, before
  20     *  the caches are initialized.  If you want to make
  21     *  subroutine calls from here, you must use the CALLKSEG1 macro.
  22     *
  23     *  Among other things, this is where the GPIO registers get
  24     *  programmed to make on-board LEDs function, or other startup
  25     *  that has to be done before anything will work.
  26     *
  27     *  Input parameters:
  28     *      nothing
  29     *
  30     *  Return value:
  31     *      nothing
  32     ********************************************************************* */
  33
  34 LEAF(board_earlyinit)
  35
  36                 .set    noreorder
  37
  38                 li      t1,EBI_ADR_BASE
  39
  40                 /* Chip Select # 0 */
  41                 li      t2,PHYS_ROM_BASE|EBI_SIZE_2M
  42                 sw      t2,CS0BASE(t1)        //# CS[0] Base
  43
  44                 /* Chip Select # 1 */
  45                 li      t2,PHYS_FLASH_BASE|EBI_SIZE_16M
  46                 sw      t2,CS1BASE(t1)        //# CS[1] Base
  47                 li      t2,SEVENWT|EBI_WORD_WIDE|EBI_ENABLE
  48                 sw      t2,CS1CNTL(t1)        //# CS[1] Control
  49
  50                 /* Chip Select # 2 */
  51                 li      t2,PHYS_FLASH2_BASE|EBI_SIZE_4M
  52                 sw      t2,CS2BASE(t1)        //# CS[2] Base
  53                 li      t2,SEVENWT|EBI_WORD_WIDE|EBI_ENABLE
  54                 sw      t2,CS2CNTL(t1)        //# CS[2] Control
  55
  56                 /* Chip Select # 8 */
  57                 li      t2,PHYS_BCM44XX_BASE|EBI_SIZE_8K
  58                 sw      t2,CS8BASE(t1)        //# CS[8] Base
  59 #ifdef __MIPSEB
  60                 li      t2,EBI_WORD_WIDE|EBI_ENABLE|EBI_TS_TA_MODE|0x800
  61 #else
  62                 li      t2,EBI_WORD_WIDE|EBI_ENABLE|EBI_TS_TA_MODE|EBI_REV_END|0x800
  63 #endif
  64                 sw      t2,CS8CNTL(t1)        //# CS[8] Control
  65
  66                 li      t2,0x00000400
  67                 sw      t2,EBICONFIG(t1)
  68                 nop
  69
  70         #
  71         # Turn off all timers.
  72         #
  73
  74                 li      t0,TIMR_ADR_BASE
  75                 sb      zero,TIMER_MASK(t0)
  76                 li      v0,0x0f
  77                 sb      v0,TIMER_INTS(t0)
  78
  79                 sw      zero,TIMER_0_CTL(t0)
  80                 sw      zero,TIMER_1_CTL(t0)
  81                 sw      zero,TIMER_2_CTL(t0)
  82                 sw      zero,TIMER_3_CTL(t0)
  83
  84
  85 #ifdef SERIALLEDS
  86
  87                 li t3, XTALFREQ / 115200 / 16
  88
  89                 /* Ugh!  Debugging hack! */
  90                 li      t1,   0xFFFE00B0
  91                 andi    t3,   t3, 0xff
  92                 sb      t3,   BAUDLO_OFFSET(t1)
  93                 srl     t3,   8
  94                 andi    t3,   t3, 0xff
  95                 sb      t3,   BAUDHI_OFFSET(t1)
  96
  97                 sb      zero, RXSTAT_OFFSET(t1)
  98                 sb      zero, TXSTAT_OFFSET(t1)
  99
 100                 li      t2,   TXEN | RXEN | BITM8
 101                 sb      t2,   CTRL_OFFSET(t1)
 102
 103 #endif
 104
 105                 j       ra
 106                 nop
 107
 108                 .set    reorder
 109
 110 END(board_earlyinit)
 111
 112
 113 /*  *********************************************************************
 114     *  BOARD_DRAMINFO
 115     *
 116     *  Return the address of the DRAM information table
 117     *
 118     *  Input parameters:
 119     *      nothing
 120     *
 121     *  Return value:
 122     *      v0 - DRAM info table, return 0 to use default table
 123     ********************************************************************* */
 124
 125
 126 LEAF(board_draminfo)
 127
 128                 move    v0,zero     # auto configure
 129                 j       ra
 130
 131 END(board_draminfo)
 132
 133
 134 /*  *********************************************************************
 135     *  BOARD_DRAMINIT
 136     *
 137     *  This routine should activate memory.
 138     *
 139     *  Input parameters:
 140     *      a0 - points to configuration table returned by board_draminfo
 141     *           or 0 to use an automatic table
 142     *
 143     *  Return value:
 144     *      v0 - total memory installed
 145     *
 146     *  Registers used:
 147     *      can use all registers.
 148     ********************************************************************* */
 149
 150 LEAF(board_draminit)
 151
 152 #ifndef DEBUG_ENV_ICE
 153
 154 /*
 155  * BCM711x Mips bootcode
 156  *
 157  * Notes:
 158  * BCM97115 DDRAM Configuration
 159  *      DDRAM configured for 2 chips of 16Mbits x 16 (total 64 Mbytes):
 160  *              - CS0: 1 chip of 256 Mbits, 16 bit wide, a total of 32 Mbytes
 161  *              - CS1: 1 chip of 256 Mbits, 16 bit wide, a total of 32 Mbytes
 162  *              - 16 bit mode of operation for the DDR interface
 163  * BCM97110 DDRAM Configuration
 164  *      DDRAM configured for 2 chips of 16Mbits x 16 (total 64 Mbytes):
 165  *              - CS0: 2 chips of 256 Mbits, 16-bit wide, a total of 64 Mbytes
 166  *              - CS1: No DDR device mounted on this chip select
 167  *              - 32 bit mode of operation for the DDR interface
 168  */
 169
 170         /*
 171          *      Setup for 2 chips 16Mbits x 16 Samsung K4H561638B.
 172          */
 173         li      v0,DDR_BASE_ADR_REG     /*  v0 contains DDR control reg. base.          */
 174
 175         li      v1,0x00008000
 176         sw      v1,0x1A0(v0)
 177
 178         /*
 179          *      Program RB_MMC_DRAM_TIMING_REG  (0x00)
 180          */
 181 #if defined(BCM97115)
 182         li      v1,0x0000BA2C   /* Set RB_MMC_DRAM_TIMING_REG = 0x0000BA2C      */
 183 #else
 184         li      v1,0x00001A2C   /* Set RB_MMC_DRAM_TIMING_REG = 0x00001A2C      */
 185 #endif
 186         sw      v1,0x00(v0)             /* Set RB_MMC_DRAM_TIMING_REG           */
 187
 188         /*
 189          *      Program RB_MMC_MEC_DRAM_MODE_REG (0x01)
 190          *      BCM97115 (default 64 Mbytes)
 191          *              - ExtBusWidth           16-bit external DDR interface
 192          *              - M256_CS1                      256 Mbits device mounted on chip select 1
 193          *              - M256_CS0                      256 Mbits device mounted on chip select 0
 194          *              - CAS Latency           2
 195          *      BCM97110 (default 64 Mbytes)
 196          *              - ExtBusWidth           32-bit external DDR interface
 197          *              - M256_CS0                      256 Mbits device mounted on chip select 0
 198          *              - CAS Latency           2
 199          *              - Burst Length          8 for 16bit mode  & 4 for 32bit mode
 200          */
 201 #if defined(BCM97115)
 202         li      v1,0x00007823   /* Setting for BCM7115                                          */
 203                                                 /* RB_MMC_MEC_DRAM_MODE_REG = 0x00007863        */
 204 #else
 205         li      v1,0x00001023   /* Setting for BCM7110                                          */
 206                                                 /* RB_MMC_MEC_DRAM_MODE_REG = 0x00001022        */
 207 #endif
 208
 209         sw      v1,0x04(v0)             /* Set RB_MMC_MEMC_DRAM_MODE_REG        */
 210
 211         /*
 212          *      Program RB_MMC_MEMC_DRAM_MODE2_REG (0x2A)
 213          *      BCM97115
 214          *              - MEMSIZE                       32 Mbytes mounted on CS0
 215          *              - CS1_NM                        there is DDR device mounted on the second chip select
 216          *      BCM97110
 217          *              - MEMSIZE                       64 Mbytes mounted on CS0
 218          *              - CS1_NM                        there is no DDR device mounted on the second chip select
 219          */
 220 #if defined(BCM97115)
 221         li      v1,0x0000C6F4
 222 #else
 223     li  v1,0x00006002
 224 #endif
 225
 226         sw      v1,0xA8(v0)             /* Set RB_MMC_MEMC_DRAM_MODE2_REG       */
 227
 228         /*
 229          *      Program RB_MMC_MMU_REG0 (0x06)
 230          *                      RB_MMC_MMU_REG1 (0x07)
 231          *                      RB_MMC_MMU_REG2 (0x08)
 232          *                      RB_MMC_MMU_REG3 (0x09)
 233          *      BCM97115
 234          *              - CS0                           32 Mbytes mounted on CS0 (4M x 16 x 4) * 1 chip
 235          *              - CS1                           32 Mbytes mounted on CS1 (4M x 16 x 4) * 1 chip
 236          *      BCM97110
 237          *              - CS0                           64 Mbytes mounted on CS0 (4M x 16 x 4) * 2 chips
 238          *              - CS1                           there is no DDR device mounted on the second chip select
 239          */
 240 #if defined(BCM97115)
 241         li      v1,0x00003210
 242         sw      v1,0x18(v0)             /* Set RB_MMC_MMU_REG0 = 0x00003210     */
 243         li      v1,0x0000BA98
 244         sw      v1,0x1C(v0)             /* Set RB_MMC_MMU_REG1 = 0x0000BA98     */
 245         li      v1,0x0000ffff
 246         sw      v1,0x20(v0)             /* Set RB_MMC_MMU_REG2 = 0x0000ffff     */
 247         sw      v1,0x24(v0)             /* Set RB_MMC_MMU_REG3 = 0x0000ffff     */
 248 #else
 249         li      v1,0x00003210
 250         sw      v1,0x18(v0)             /* Set RB_MMC_MMU_REG0 = 0x00003210     */
 251         li      v1,0x00007654
 252         sw      v1,0x1C(v0)             /* Set RB_MMC_MMU_REG1 = 0x00007654     */
 253         li      v1,0x0000ffff
 254         sw      v1,0x20(v0)             /* Set RB_MMC_MMU_REG2 = 0x0000ffff     */
 255         sw      v1,0x24(v0)             /* Set RB_MMC_MMU_REG3 = 0x0000ffff     */
 256 #endif
 257
 258         /*
 259          *      Program RB_MMC_NMBX_TIMING_REG  (0x02)
 260          */
 261         li      v1,0x0000172E
 262         sw      v1,0x08(v0)             /* Set RB_MMC_NMBX_TIMING_REG = 0x0000172E      */
 263
 264         /*
 265          *      Program RB_MMC_READ01_NCDL_CORR_REG     (0x0D)
 266          *                      RB_MMC_READ23_NCDL_CORR_REG     (0x2B)
 267          */
 268         li      v1,0x00000101
 269         sw      v1,0x34(v0)             /* Set RB_MMC_READ01_NCDL_CORR_REG = 0x00007E7E */
 270         sw      v1,0xAC(v0)             /* Set RB_MMC_READ23_NCDL_CORR_REG = 0x00007E7E */
 271
 272         /*
 273          *      Program RB_MMC_RDWR_NCDL_CORR_REG       (0x0C)
 274          */
 275 #if defined(BCM97115)
 276         li      v1,0x00009D05   /* Set RB_MMC_RDWR_NCDL_CORR_REG = 0x00009D05   */
 277 #else
 278         li      v1,0x00000101   /* Set RB_MMC_RDWR_NCDL_CORR_REG = 0x00000101   */
 279 #endif
 280
 281         sw      v1,0x30(v0)             /* Set RB_MMC_RDWR_NCDL_CORR_REG        */
 282
 283         /*
 284          *      Program RB_MMC_MSA_MODE_REG     (0x1B)
 285          */
 286         sw      $0,0x6C(v0)     /* Set RB_MMC_MSA_MODE_REG: Normal mode */
 287
 288         /*
 289          * Program the client priority, timer value and
 290          * round robin membership etc.
 291          */
 292         sw      $0,0x0C(v0)     /* Set RB_MMC_CLIENT_INDEX_REG          */
 293         li      v1,0xA80
 294         sw      v1,0x10(v0)     /* Set RB_MMC_INDX_DATA_WR_REG          */
 295
 296         li      v1,0x1
 297         sw      v1,0x0C(v0)
 298         li      v1,0xFFF2
 299         sw      v1,0x10(v0)
 300
 301         li      v1,0x2
 302         sw      v1,0x0C(v0)
 303         li      v1,0xFFF3
 304         sw      v1,0x10(v0)
 305
 306         li      v1,0x3
 307         sw      v1,0x0C(v0)
 308         li      v1,0xFFF4
 309         sw      v1,0x10(v0)
 310
 311         li      v1,0x4
 312         sw      v1,0x0C(v0)
 313         li      v1,0xC00F
 314         sw      v1,0x10(v0)
 315
 316         li      v1,0x5
 317         sw      v1,0x0C(v0)
 318         li      v1,0xFFD6
 319         sw      v1,0x10(v0)
 320
 321         li      v1,0x6
 322         sw      v1,0x0C(v0)
 323         li      v1,0xC010
 324         sw      v1,0x10(v0)
 325
 326         li      v1,0x7
 327         sw      v1,0x0C(v0)
 328         li      v1,0x1985
 329         sw      v1,0x10(v0)
 330
 331         li      v1,0x8
 332         sw      v1,0x0C(v0)
 333         li      v1,0x1984
 334         sw      v1,0x10(v0)
 335
 336         li      v1,0x9
 337         sw      v1,0x0C(v0)
 338         li      v1,0x2A0A
 339         sw      v1,0x10(v0)
 340
 341         li      v1,0xA
 342         sw      v1,0x0C(v0)
 343         li      v1,0xFFD7
 344         sw      v1,0x10(v0)
 345
 346         li      v1,0xB
 347         sw      v1,0x0C(v0)
 348         li      v1,0xFC2
 349         sw      v1,0x10(v0)
 350
 351         li      v1,0xC
 352         sw      v1,0x0C(v0)
 353         li      v1,0xBF8E
 354         sw      v1,0x10(v0)
 355
 356         li      v1,0xD
 357         sw      v1,0x0C(v0)
 358         li      v1,0x2B0B
 359         sw      v1,0x10(v0)
 360
 361         li      v1,0xE
 362         sw      v1,0x0C(v0)
 363         li      v1,0xF41
 364         sw      v1,0x10(v0)
 365
 366         li      v1,0xF
 367         sw      v1,0x0C(v0)
 368         li      v1,0xFFD8
 369         sw      v1,0x10(v0)
 370
 371         li      v1,0x10
 372         sw      v1,0x0C(v0)
 373         li      v1,0x2849
 374         sw      v1,0x10(v0)
 375
 376         li      v1,0x11
 377         sw      v1,0x0C(v0)
 378         li      v1,0x3CAC
 379         sw      v1,0x10(v0)
 380
 381         li      v1,0x12
 382         sw      v1,0x0C(v0)
 383         li      v1,0x650D
 384         sw      v1,0x10(v0)
 385
 386         li      v1,0x13
 387         sw      v1,0x0C(v0)
 388         li      v1,0xFFD9
 389         sw      v1,0x10(v0)
 390
 391         li      v1,0x14
 392         sw      v1,0x0C(v0)
 393         li      v1,0xFFDA
 394         sw      v1,0x10(v0)
 395
 396         li      v1,0x15
 397         sw      v1,0x0C(v0)
 398         li      v1,0xFFDB
 399         sw      v1,0x10(v0)
 400
 401         li      v1,0x16
 402         sw      v1,0x0C(v0)
 403         li      v1,0xFFDC
 404         sw      v1,0x10(v0)
 405
 406         li      v1,0x17
 407         sw      v1,0x0C(v0)
 408         li      v1,0xFFDD
 409         sw      v1,0x10(v0)
 410
 411         li      v1,0x18
 412         sw      v1,0x0C(v0)
 413         li      v1,0x1583
 414         sw      v1,0x10(v0)
 415
 416         li      v1,0x19
 417         sw      v1,0x0C(v0)
 418         li      v1,0x31
 419         sw      v1,0x10(v0)
 420
 421         li      v1,0x1A
 422         sw      v1,0x0C(v0)
 423         li      v1,0x1FC6
 424         sw      v1,0x10(v0)
 425
 426         li      v1,0x1B
 427         sw      v1,0x0C(v0)
 428         li      v1,0x25C7
 429         sw      v1,0x10(v0)
 430
 431         li      v1,0x1C
 432         sw      v1,0x0C(v0)
 433         li      v1,0xFFDE
 434         sw      v1,0x10(v0)
 435
 436         li      v1,0x1D
 437         sw      v1,0x0C(v0)
 438         li      v1,0xFFDF
 439         sw      v1,0x10(v0)
 440
 441         li      v1,0x1E
 442         sw      v1,0x0C(v0)
 443         li      v1,0xFFF5
 444         sw      v1,0x10(v0)
 445
 446         li      v1,0x1F
 447         sw      v1,0x0C(v0)
 448         li      v1,0x4E8
 449         sw      v1,0x10(v0)
 450
 451         li              v1,0x11F5
 452         sw              v1,0x28(v0)
 453
 454         /*
 455          *      Program RB_SOFT_RESET1_WITHDRAW_REG     (0x69)
 456          */
 457         li      v1,0x0080
 458         sw      v1,0x01A4(v0)
 459
 460         nop
 461
 462 #endif
 463
 464                 li      v0, 64
 465                 j       ra
 466
 467 END(board_draminit)
 468
 469
 470 /*  *********************************************************************
 471     *  BOARD_SETLEDS(x)
 472     *
 473     *  Set LEDs for boot-time progress indication.  Not used if
 474     *  the board does not have progress LEDs.  This routine
 475     *  must not call any other routines, since it may be invoked
 476     *  either from KSEG0 or KSEG1 and it may be invoked
 477     *  whether or not the icache is operational.
 478     *
 479     *  Input parameters:
 480     *      a0 - LED value (8 bits per character, 4 characters)
 481     *
 482     *  Return value:
 483     *      nothing
 484     *
 485     *  Registers used:
 486     *      t0,t1,t2,t3
 487     ********************************************************************* */
 488
 489
 490 LEAF(board_setleds)
 491
 492 #ifdef SERIALLEDS
 493
 494                 li      t0, UARTA_BASE
 495                 li      t3, 0x0
 496
 497                 li      t2, TXDRE
 498 1:              lb      t1, TXSTAT_OFFSET(t0)
 499                 and     t1, t2
 500                 bne     t1, t2, 1b
 501                 nop
 502                 sb      a0, TXDATA_OFFSET(t0)
 503
 504                 rol     a0, 8
 505                 addu    t3, t3, 1
 506                 bne     t3, 4, 1b
 507                 nop
 508
 509                 /* Now write \r\n */
 510
 511                 li      t3, '\r'
 512 1:              lb      t1, TXSTAT_OFFSET(t0)
 513                 and     t1, t2
 514                 bne     t1, t2, 1b
 515                 nop
 516                 sb      t3, TXDATA_OFFSET(t0)
 517
 518                 li      t3, '\n'
 519 1:              lb      t1, TXSTAT_OFFSET(t0)
 520                 and     t1, t2
 521                 bne     t1, t2, 1b
 522                 nop
 523                 sb      t3, TXDATA_OFFSET(t0)
 524
 525 #endif
 526
 527                 j       ra
 528
 529 END(board_setleds)