release/src-rt-6.x/cfe/cfe/arch/mips/board/bcm9635x/include/board.h

   1 /*
   2 <:copyright-broadcom
   3
   4  Copyright (c) 2002 Broadcom Corporation
   5  All Rights Reserved
   6  No portions of this material may be reproduced in any form without the
   7  written permission of:
   8           Broadcom Corporation
   9           16215 Alton Parkway
  10           Irvine, California 92619
  11  All information contained in this document is Broadcom Corporation
  12  company private, proprietary, and trade secret.
  13
  14 :>
  15 */
  16 /***********************************************************************/
  17 /*                                                                     */
  18 /*   MODULE:  board.h                                                  */
  19 /*   DATE:    97/02/18                                                 */
  20 /*   PURPOSE: Board specific information.  This module should include  */
  21 /*            all base device addresses and board specific macros.     */
  22 /*                                                                     */
  23 /***********************************************************************/
  24 #ifndef _BOARD_H
  25 #define _BOARD_H
  26
  27 #if __cplusplus
  28 extern "C" {
  29 #endif
  30 /*****************************************************************************/
  31 /*                    Misc board definitions                                 */
  32 /*****************************************************************************/
  33
  34 /*****************************************************************************/
  35 /*                    Physical Memory Map                                    */
  36 /*****************************************************************************/
  37
  38 #define PHYS_DRAM_BASE           0x00000000     /* Dynamic RAM Base */
  39 #define PHYS_FLASH_BASE          0x1FC00000     /* Flash Memory         */
  40 #define PHYS_BCM42xx_BASE        0x1B000000     /* HPNA */
  41 #define PHYS_ITEX_BASE           0x1CC00000     /* ITEX Card            */
  42
  43 /*****************************************************************************/
  44 /* Note that the addresses above are physical addresses and that programs    */
  45 /* have to use converted addresses defined below:                            */
  46 /*****************************************************************************/
  47 #define DRAM_BASE           (0x80000000 | PHYS_DRAM_BASE)   /* cached DRAM */
  48 #define DRAM_BASE_NOCACHE   (0xA0000000 | PHYS_DRAM_BASE)   /* uncached DRAM */
  49 #define FLASH_BASE          (0xA0000000 | PHYS_FLASH_BASE)  /* uncached Flash  */
  50 #define BCM42xx_BASE        (0xA0000000 | PHYS_BCM42xx_BASE)
  51 #define ITEX_BASE           (0xA0000000 | PHYS_ITEX_BASE)   /* uncached ITeX Card */
  52
  53 /*****************************************************************************/
  54 /*  Select the PLL value to get the desired CPU clock frequency.             */
  55 /*                                                                           */
  56 /*  Use the following equation to calculate what value should be used for    */
  57 /*  a given clock frequency:                                                 */
  58 /*                                                                           */
  59 /*  freq = (value + 1) * XTALFREQ/2 MHz                                      */
  60 /*****************************************************************************/
  61 #define CLK_FREQ_122MHz     8     /* Fastest operation supported. */
  62 #define CLK_FREQ_108MHz     7
  63 #define CLK_FREQ_95MHz      6
  64 #define CLK_FREQ_81MHz      5
  65 #define CLK_FREQ_68MHz      4
  66 #define CLK_FREQ_54MHz      3
  67 #define CLK_FREQ_50MHz      3
  68 #define CLK_FREQ_41MHz      2
  69 #define CLK_FREQ_27MHz      1
  70 #define CLK_FREQ_14MHz      0
  71
  72 #define XTALFREQ            25000000
  73
  74 // 635X board sdram type definition and flash location
  75 #define MEMORY_635X_16MB_1_CHIP         0
  76 #define MEMORY_635X_32MB_2_CHIP         1
  77 #define MEMORY_635X_64MB_2_CHIP         2
  78 // board memory type offset
  79 #define SDRAM_TYPE_ADDRESS_OFFSET       16
  80 #define BOARD_SDRAM_TYPE_ADDRESS        FLASH_BASE + SDRAM_TYPE_ADDRESS_OFFSET
  81 #define BOARD_SDRAM_TYPE                *(unsigned long *)(FLASH_BASE + SDRAM_TYPE_ADDRESS_OFFSET)
  82
  83 /*****************************************************************************/
  84 /*          board ioctl calls for flash, led and some other utilities        */
  85 /*****************************************************************************/
  86
  87 /* GPIO Definitions */
  88 #define GPIO_BOARD_ID_1             0x0020
  89 #define GPIO_BOARD_ID_2             0x0040
  90
  91 /* Identify BCM96352 board type.
  92  * BCM86352SV - GPIO bit 6 = 1, GPIO bit 5 = 1 (GPIOIO = 0x60)
  93  * BCM86352R  - GPIO bit 6 = 0, GPIO bit 5 = 1 (GPIOIO = 0x20)
  94  * BCM96350   - GPIO bit 6 = 1, GPIO bit 5 = 0 (GPIOIO = 0x40)
  95  */
  96 #define BOARD_ID_BCM9635X_MASK      (GPIO_BOARD_ID_1 | GPIO_BOARD_ID_2)
  97 #define BOARD_ID_BCM96352SV         (GPIO_BOARD_ID_1 | GPIO_BOARD_ID_2)
  98 #define BOARD_ID_BCM96352R          (GPIO_BOARD_ID_1)
  99 #define BOARD_ID_BCM96350           (GPIO_BOARD_ID_2)
 100
 101 /*****************************************************************************/
 102 /*          External interrupt mapping                                       */
 103 /*****************************************************************************/
 104 #define INTERRUPT_ID_ITEX   INTERRUPT_ID_EXTERNAL_0
 105 #define MSI_IRQ             INTERRUPT_ID_EXTERNAL_1
 106
 107 #if __cplusplus
 108 }
 109 #endif
 110
 111 #endif /* _BOARD_H */