2 * Copyright (C) 2008, Broadcom Corporation
5 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10 * $Id: time.c,v 1.9 2009/07/17 06:23:12 Exp $
12 #include <linux/config.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/serial_reg.h>
17 #include <linux/interrupt.h>
18 #include <asm/addrspace.h>
34 /* Global SB handle */
35 extern si_t
*bcm947xx_sih
;
36 extern spinlock_t bcm947xx_sih_lock
;
39 #define sih bcm947xx_sih
40 #define sih_lock bcm947xx_sih_lock
42 #define WATCHDOG_MIN 3000 /* milliseconds */
43 extern int panic_timeout
;
44 static int watchdog
= 0;
47 static u8
*mcr
= NULL
;
48 #endif /* CONFIG_HWSIM */
51 bcm947xx_time_init(void)
57 * Use deterministic values for initial counter interrupt
58 * so that calibrate delay avoids encountering a counter wrap.
61 write_c0_compare(0xffff);
63 /* 5354 could run both on 200 & 240 Mhz -- use nvram setting */
64 if (sih
->chip
== BCM5354_CHIP_ID
&& nvram_match("clkfreq", "200"))
67 if (!(hz
= si_cpu_clock(sih
)))
70 bcm_chipname(sih
->chip
, cn
, 8);
71 printk("CPU: BCM%s rev %d pkg %d at %d MHz\n", cn
, sih
->chiprev
, sih
->chippkg
,
72 (hz
+ 500000) / 1000000);
74 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
75 if (sih
->chip
== BCM5354_CHIP_ID
&&
76 strncmp(nvram_safe_get("hardware_version"), "WL520G", 6) == 0)
77 mips_hpt_frequency
= 100000000; // Fix WL520GUGC clock
79 mips_hpt_frequency
= hz
/ 2;
81 /* Set watchdog interval in ms */
82 watchdog
= simple_strtoul(nvram_safe_get("watchdog"), NULL
, 0);
84 /* Ensure at least WATCHDOG_MIN */
85 if ((watchdog
> 0) && (watchdog
< WATCHDOG_MIN
))
86 watchdog
= WATCHDOG_MIN
;
88 /* Set panic timeout in seconds */
89 panic_timeout
= watchdog
/ 1000;
92 #ifdef CONFIG_HND_BMIPS3300_PROF
93 extern bool hndprofiling
;
95 typedef u_int64_t sbprof_pc
;
97 typedef u_int32_t sbprof_pc
;
99 extern void sbprof_cpu_intr(sbprof_pc restartpc
);
100 #endif /* CONFIG_HND_BMIPS3300_PROF */
103 bcm947xx_timer_interrupt(int irq
, void *dev_id
)
105 #ifdef CONFIG_HND_BMIPS3300_PROF
107 * Are there any ExcCode or other mean(s) to determine what has caused
108 * the timer interrupt? For now simply stop the normal timer proc if
109 * count register is less than compare register.
112 sbprof_cpu_intr(read_c0_epc() +
113 ((read_c0_cause() >> (CAUSEB_BD
- 2)) & 4));
114 if (read_c0_count() < read_c0_compare())
115 return (IRQ_HANDLED
);
117 #endif /* CONFIG_HND_BMIPS3300_PROF */
119 /* Generic MIPS timer code */
120 timer_interrupt(irq
, dev_id
);
122 /* Set the watchdog timer to reset after the specified number of ms */
124 if (((si_t
*)sih
)->chip
== BCM5354_CHIP_ID
)
125 si_watchdog(sih
, WATCHDOG_CLOCK_5354
/ 1000 * watchdog
);
127 si_watchdog_ms(sih
, watchdog
);
131 (*((int *)0xa0000f1c))++;
133 /* Blink one of the LEDs in the external UART */
134 if (mcr
&& !(jiffies
% (HZ
/2)))
135 writeb(readb(mcr
) ^ UART_MCR_OUT2
, mcr
);
138 return (IRQ_HANDLED
);
141 static struct irqaction bcm947xx_timer_irqaction
= {
142 bcm947xx_timer_interrupt
,
153 plat_timer_setup(struct irqaction
*irq
)
155 /* Enable the timer interrupt */
156 setup_irq(7, &bcm947xx_timer_irqaction
);
159 #define CFE_UPDATE 1 // added by Chen-I for mac/regulation update
162 void bcm947xx_watchdog_disable(void)