release/src/linux/linux/arch/mips/kernel/pci_auto.c

   1 /*
   2  * PCI autoconfiguration library
   3  *
   4  * Author: Matt Porter <mporter@mvista.com>
   5  *
   6  * Copyright 2000, 2001 MontaVista Software Inc.
   7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 /*
  16  * Modified for MIPS by Jun Sun, jsun@mvista.com
  17  *
  18  * . Simplify the interface between pci_auto and the rest: a single function.
  19  * . Assign resources from low address to upper address.
  20  * . change most int to u32.
  21  *
  22  * Further modified to include it as mips generic code, ppopov@mvista.com.
  23  *
  24  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  25  * - Add a top_bus argument to the "early config" functions so that
  26  *   they can set a fake parent bus pointer to convince the underlying
  27  *   pci ops to use type 1 configuration for sub busses.
  28  * - Set bridge base and limit registers correctly.
  29  * - Align io and memory base properly before and after bridge setup.
  30  * - Don't fall through to pci_setup_bars for bridge.
  31  * - Reformat the debug output to look more like lspci's output.
  32  */
  33
  34 #include <linux/kernel.h>
  35 #include <linux/init.h>
  36 #include <linux/types.h>
  37 #include <linux/pci.h>
  38
  39 #include <asm/pci_channel.h>
  40
  41 #define DEBUG
  42 #ifdef  DEBUG
  43 #define DBG(x...)       printk(x)
  44 #else
  45 #define DBG(x...)
  46 #endif
  47
  48 /*
  49  * These functions are used early on before PCI scanning is done
  50  * and all of the pci_dev and pci_bus structures have been created.
  51  */
  52 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  53         int top_bus, int busnr, int devfn)
  54 {
  55         static struct pci_dev dev;
  56         static struct pci_bus bus;
  57
  58         dev.bus = &bus;
  59         dev.sysdata = hose;
  60         dev.devfn = devfn;
  61         bus.number = busnr;
  62         bus.ops = hose->pci_ops;
  63
  64         if(busnr != top_bus)
  65                 /* Fake a parent bus structure. */
  66                 bus.parent = &bus;
  67         else
  68                 bus.parent = NULL;
  69
  70         return &dev;
  71 }
  72
  73 #define EARLY_PCI_OP(rw, size, type)                                    \
  74 int early_##rw##_config_##size(struct pci_channel *hose,                \
  75         int top_bus, int bus, int devfn, int offset, type value)        \
  76 {                                                                       \
  77         return pci_##rw##_config_##size(                                \
  78                 fake_pci_dev(hose, top_bus, bus, devfn),                \
  79                 offset, value);                                         \
  80 }
  81
  82 EARLY_PCI_OP(read, byte, u8 *)
  83 EARLY_PCI_OP(read, word, u16 *)
  84 EARLY_PCI_OP(read, dword, u32 *)
  85 EARLY_PCI_OP(write, byte, u8)
  86 EARLY_PCI_OP(write, word, u16)
  87 EARLY_PCI_OP(write, dword, u32)
  88
  89 static struct resource *io_resource_inuse;
  90 static struct resource *mem_resource_inuse;
  91
  92 static u32 pciauto_lower_iospc;
  93 static u32 pciauto_upper_iospc;
  94
  95 static u32 pciauto_lower_memspc;
  96 static u32 pciauto_upper_memspc;
  97
  98 void __init
  99 pciauto_setup_bars(struct pci_channel *hose,
 100                    int top_bus,
 101                    int current_bus,
 102                    int pci_devfn)
 103 {
 104         u32 bar_response, bar_size, bar_value;
 105         u32 bar, addr_mask, bar_nr = 0;
 106         u32 * upper_limit;
 107         u32 * lower_limit;
 108         int found_mem64 = 0;
 109
 110         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) {
 111                 /* Tickle the BAR and get the response */
 112                 early_write_config_dword(hose, top_bus,
 113                                          current_bus,
 114                                          pci_devfn,
 115                                          bar,
 116                                          0xffffffff);
 117                 early_read_config_dword(hose, top_bus,
 118                                         current_bus,
 119                                         pci_devfn,
 120                                         bar,
 121                                         &bar_response);
 122
 123                 /* If BAR is not implemented go to the next BAR */
 124                 if (!bar_response)
 125                         continue;
 126
 127                 if (!(bar_response & 0xffff0000))
 128                         bar_response |= 0xffff0000;
 129
 130 retry:
 131                 /* Check the BAR type and set our address mask */
 132                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 133                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 134                         upper_limit = &pciauto_upper_iospc;
 135                         lower_limit = &pciauto_lower_iospc;
 136                         DBG("        I/O");
 137                 } else {
 138                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 139                             PCI_BASE_ADDRESS_MEM_TYPE_64)
 140                                 found_mem64 = 1;
 141
 142                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
 143                         upper_limit = &pciauto_upper_memspc;
 144                         lower_limit = &pciauto_lower_memspc;
 145                         DBG("        Mem");
 146                 }
 147
 148
 149                 /* Calculate requested size */
 150                 bar_size = ~(bar_response & addr_mask) + 1;
 151
 152                 /* Allocate a base address */
 153                 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 154
 155                 if ((bar_value + bar_size) > *upper_limit) {
 156                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 157                                 if (io_resource_inuse->child) {
 158                                         io_resource_inuse =
 159                                                 io_resource_inuse->child;
 160                                         pciauto_lower_iospc =
 161                                                 io_resource_inuse->start;
 162                                         pciauto_upper_iospc =
 163                                                 io_resource_inuse->end + 1;
 164                                         goto retry;
 165                                 }
 166
 167                         } else {
 168                                 if (mem_resource_inuse->child) {
 169                                         mem_resource_inuse =
 170                                                 mem_resource_inuse->child;
 171                                         pciauto_lower_memspc =
 172                                                 mem_resource_inuse->start;
 173                                         pciauto_upper_memspc =
 174                                                 mem_resource_inuse->end + 1;
 175                                         goto retry;
 176                                 }
 177                         }
 178                         DBG(" unavailable -- skipping\n");
 179                         continue;
 180                 }
 181
 182                 /* Write it out and update our limit */
 183                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 184                                          bar, bar_value);
 185
 186                 *lower_limit = bar_value + bar_size;
 187
 188                 /*
 189                  * If we are a 64-bit decoder then increment to the
 190                  * upper 32 bits of the bar and force it to locate
 191                  * in the lower 4GB of memory.
 192                  */
 193                 if (found_mem64) {
 194                         bar += 4;
 195                         early_write_config_dword(hose, top_bus,
 196                                                  current_bus,
 197                                                  pci_devfn,
 198                                                  bar,
 199                                                  0x00000000);
 200                 }
 201
 202                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 203
 204                 bar_nr++;
 205         }
 206
 207 }
 208
 209 void __init
 210 pciauto_prescan_setup_bridge(struct pci_channel *hose,
 211                              int top_bus,
 212                              int current_bus,
 213                              int pci_devfn,
 214                              int sub_bus)
 215 {
 216         /* Configure bus number registers */
 217         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 218                                 PCI_PRIMARY_BUS, current_bus);
 219         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 220                                 PCI_SECONDARY_BUS, sub_bus + 1);
 221         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 222                                 PCI_SUBORDINATE_BUS, 0xff);
 223
 224         /* Align memory and I/O to 1MB and 4KB boundaries. */
 225         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 226                 & ~(0x100000 - 1);
 227         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 228                 & ~(0x1000 - 1);
 229
 230         /* Set base (lower limit) of address range behind bridge. */
 231         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 232                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 233         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 234                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 235         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 236                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 237
 238         /* We don't support prefetchable memory for now, so disable */
 239         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 240                                 PCI_PREF_MEMORY_BASE, 0);
 241         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 242                                 PCI_PREF_MEMORY_LIMIT, 0);
 243 }
 244
 245 void __init
 246 pciauto_postscan_setup_bridge(struct pci_channel *hose,
 247                               int top_bus,
 248                               int current_bus,
 249                               int pci_devfn,
 250                               int sub_bus)
 251 {
 252         u32 temp;
 253
 254         /* Configure bus number registers */
 255         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 256                                 PCI_SUBORDINATE_BUS, sub_bus);
 257
 258         /* Set upper limit of address range behind bridge. */
 259         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 260                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 261         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 262                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 263         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 264                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 265
 266         /* Align memory and I/O to 1MB and 4KB boundaries. */
 267         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 268                 & ~(0x100000 - 1);
 269         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 270                 & ~(0x1000 - 1);
 271
 272         /* Enable memory and I/O accesses, enable bus master */
 273         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 274                 PCI_COMMAND, &temp);
 275         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 276                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 277                 | PCI_COMMAND_MASTER);
 278 }
 279
 280 #define      PCIAUTO_IDE_MODE_MASK           0x05
 281
 282 int __init
 283 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 284 {
 285         int sub_bus;
 286         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 287         unsigned short vid, did;
 288         unsigned char header_type;
 289         int devfn_start = 0;
 290         int devfn_stop = 0xff;
 291
 292         sub_bus = current_bus;
 293
 294         if (hose->first_devfn)
 295                 devfn_start = hose->first_devfn;
 296         if (hose->last_devfn)
 297                 devfn_stop = hose->last_devfn;
 298
 299         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 300
 301                 if (PCI_FUNC(pci_devfn) && !found_multi)
 302                         continue;
 303
 304                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 305                                        PCI_VENDOR_ID, &vid);
 306
 307                 if (vid == 0xffff) continue;
 308
 309                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 310                                        PCI_HEADER_TYPE, &header_type);
 311
 312                 if (!PCI_FUNC(pci_devfn))
 313                         found_multi = header_type & 0x80;
 314
 315                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 316                                        PCI_DEVICE_ID, &did);
 317
 318                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 319                                         PCI_CLASS_REVISION, &pci_class);
 320
 321                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 322                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 323                         pci_class >> 16, vid, did);
 324                 if (pci_class & 0xff)
 325                         DBG(" (rev %.2x)", pci_class & 0xff);
 326                 DBG("\n");
 327
 328                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 329                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 330                                 current_bus, sub_bus + 1);
 331                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 332                                                      pci_devfn, sub_bus);
 333                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 334                                 sub_bus + 1,
 335                                 pciauto_lower_iospc, pciauto_lower_memspc);
 336                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 337                         DBG("Back to bus %.2x\n", current_bus);
 338                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 339                                                       pci_devfn, sub_bus);
 340                         continue;
 341                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 342
 343                         unsigned char prg_iface;
 344
 345                         early_read_config_byte(hose, top_bus, current_bus,
 346                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
 347                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 348                                 DBG("Skipping legacy mode IDE controller\n");
 349                                 continue;
 350                         }
 351                 }
 352
 353                 /*
 354                  * Found a peripheral, enable some standard
 355                  * settings
 356                  */
 357                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 358                                         PCI_COMMAND, &cmdstat);
 359                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 360                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 361                                          PCI_COMMAND_MEMORY |
 362                                          PCI_COMMAND_MASTER);
 363                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 364                                         PCI_LATENCY_TIMER, 0x80);
 365
 366                 /* Allocate PCI I/O and/or memory space */
 367                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn);
 368         }
 369         return sub_bus;
 370 }
 371
 372 int __init
 373 pciauto_assign_resources(int busno, struct pci_channel *hose)
 374 {
 375         /* setup resource limits */
 376         io_resource_inuse = hose->io_resource;
 377         mem_resource_inuse = hose->mem_resource;
 378
 379         pciauto_lower_iospc = io_resource_inuse->start;
 380         pciauto_upper_iospc = io_resource_inuse->end + 1;
 381         pciauto_lower_memspc = mem_resource_inuse->start;
 382         pciauto_upper_memspc = mem_resource_inuse->end + 1;
 383         DBG("Autoconfig PCI channel 0x%p\n", hose);
 384         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 385                 busno, pciauto_lower_iospc, pciauto_upper_iospc,
 386                 pciauto_lower_memspc, pciauto_upper_memspc);
 387
 388         return pciauto_bus_scan(hose, busno, busno);
 389 }