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update #3 - include
[tomato.git] / release / src-rt-6.x.4708 / include / d11.h
blobe67481a024ae272209f2ea7c9114c02cca0850ef
1 /*
2 * Chip-specific hardware definitions for
3 * Broadcom 802.11abg Networking Device Driver
4 *
5 * Copyright (C) 2013, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
9 * the contents of this file may not be disclosed to third parties, copied
10 * or duplicated in any form, in whole or in part, without the prior
11 * written permission of Broadcom Corporation.
12 *
13 * $Id: d11.h 427773 2013-10-04 19:53:12Z $
14 */
15
16 #ifndef _D11_H
17 #define _D11_H
18
19 #include <typedefs.h>
20 #include <bcmdevs.h>
21 #include <hndsoc.h>
22 #include <sbhndpio.h>
23 #include <sbhnddma.h>
24 #include <proto/802.11.h>
25
26 #ifndef _TYPEDEFS_H_
27 #include <typedefs.h>
28 #endif
29
30 /* This marks the start of a packed structure section. */
31 #include <packed_section_start.h>
32
33 #ifndef WL_RSSI_ANT_MAX
34 #define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
35 #elif WL_RSSI_ANT_MAX != 4
36 #error "WL_RSSI_ANT_MAX does not match"
37 #endif
38
39
40 /* cpp contortions to concatenate w/arg prescan */
41 #ifndef PAD
42 #define _PADLINE(line) pad ## line
43 #define _XSTR(line) _PADLINE(line)
44 #define PAD _XSTR(__LINE__)
45 #endif
46
47 #define D11AC_BCN_TMPL_LEN 640 /* length of the BCN template area for 11AC */
48 #define BCN_TMPL_LEN 512 /* length of the BCN template area */
49 #define LPRS_TMPL_LEN 512 /* length of the legacy PRS template area */
50
51 /* RX FIFO numbers */
52 #ifdef BCMPCIDEV
53 #define RX_FIFO 1 /* data and ctl frames */
54 #else
55 #define RX_FIFO 0 /* data and ctl frames */
56 #endif
57 #define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
58
59 /* TX FIFO numbers using WME Access Classes */
60 #define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
61 #define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
62 #define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
63 #define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
64 #define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
65 #define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
66
67 /* Addr is byte address used by SW; offset is word offset used by uCode */
68
69 /* Per AC TX limit settings */
70 #define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
71 #define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
72
73 /* Legacy TX FIFO numbers */
74 #define TX_DATA_FIFO TX_AC_BE_FIFO
75 #define TX_CTL_FIFO TX_AC_VO_FIFO
76
77
78 /* delay from end of PLCP reception to RxTSFTime */
79 #define M_APHY_PLCPRX_DLY 3
80 #define M_BPHY_PLCPRX_DLY 4
81
82 typedef volatile struct {
83 uint32 intstatus;
84 uint32 intmask;
85 } intctrlregs_t;
86
87 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
88 * write: only low 16b-it half can be written
89 */
90 typedef volatile union {
91 uint32 pmqhostdata; /* read only! */
92 struct {
93 uint16 pmqctrlstatus; /* read/write */
94 uint16 PAD;
95 } w;
96 } pmqreg_t;
97
98 /* pio register set 2/4 bytes union for d11 fifo */
99 typedef volatile union {
100 pio2regp_t b2; /* < corerev 8 */
101 pio4regp_t b4; /* >= corerev 8 */
102 } u_pioreg_t;
103
104 /* dma/pio corerev < 11 */
105 typedef volatile struct {
106 dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */
107 u_pioreg_t pioregs[8]; /* 0x300 */
108 } fifo32_t;
109
110 /* dma/pio corerev >= 11 */
111 typedef volatile struct {
112 dma64regs_t dmaxmt; /* dma tx */
113 pio4regs_t piotx; /* pio tx */
114 dma64regs_t dmarcv; /* dma rx */
115 pio4regs_t piorx; /* pio rx */
116 } fifo64_t;
117
118 #ifdef BCMPCIDEV
119 #define GET_MACINTSTATUS(osh, regs) R_REG((osh), &((regs)->altmacintstatus))
120 #define SET_MACINTSTATUS(osh, regs, val) W_REG((osh), &((regs)->altmacintstatus), (val))
121 #define GET_MACINTMASK(osh, regs) R_REG((osh), &((regs)->altmacintmask))
122 #define SET_MACINTMASK(osh, regs, val) W_REG((osh), &((regs)->altmacintmask), (val))
123 #else
124 #define GET_MACINTSTATUS(osh, regs) R_REG((osh), &((regs)->macintstatus))
125 #define SET_MACINTSTATUS(osh, regs, val) W_REG((osh), &((regs)->macintstatus), (val))
126 #define GET_MACINTMASK(osh, regs) R_REG((osh), &((regs)->macintmask))
127 #define SET_MACINTMASK(osh, regs, val) W_REG((osh), &((regs)->macintmask), (val))
128 #endif
129
130 /*
131 * Host Interface Registers
132 * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
133 * - but definitely not complete
134 */
135 typedef volatile struct _d11regs {
136 /* Device Control ("semi-standard host registers") */
137 uint32 PAD[3]; /* 0x0 - 0x8 */
138 uint32 biststatus; /* 0xC */
139 uint32 biststatus2; /* 0x10 */
140 uint32 PAD; /* 0x14 */
141 uint32 gptimer; /* 0x18 */ /* for corerev >= 3 */
142 uint32 usectimer; /* 0x1c */ /* for corerev >= 26 */
143
144 /* DMA Interrupt Control */ /* 0x20 */
145 intctrlregs_t intctrlregs[8];
146
147 /* New DMA altintmask on corerev >=40 */
148 uint32 altintmask[6]; /* 0x60 - 0x74 */
149 uint32 PAD[34]; /* 0x74 - 0xFC */
150
151 /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
152 uint32 intrcvlazy[4]; /* 0x100 - 0x10C */
153
154 uint32 PAD[4]; /* 0x110 - 0x11c */
155
156 uint32 maccontrol; /* 0x120 */
157 uint32 maccommand; /* 0x124 */
158 uint32 macintstatus; /* 0x128 */
159 uint32 macintmask; /* 0x12C */
160
161 /* Transmit Template Access */
162 uint32 tplatewrptr; /* 0x130 */
163 uint32 tplatewrdata; /* 0x134 */
164 uint32 PAD[2]; /* 0x138 - 0x13C */
165
166 /* PMQ registers */
167 pmqreg_t pmqreg; /* 0x140 */
168 uint32 pmqpatl; /* 0x144 */
169 uint32 pmqpath; /* 0x148 */
170 uint32 PAD; /* 0x14C */
171
172 uint32 chnstatus; /* 0x150 */
173 uint32 psmdebug; /* 0x154 */ /* for corerev >= 3 */
174 uint32 phydebug; /* 0x158 */ /* for corerev >= 3 */
175 uint32 machwcap; /* 0x15C */ /* Corerev >= 13 */
176
177 /* Extended Internal Objects */
178 uint32 objaddr; /* 0x160 */
179 uint32 objdata; /* 0x164 */
180
181 /* New altmacintstatus/mask on corerev >=40 */
182 uint32 altmacintstatus; /* 0x168 */
183 uint32 altmacintmask; /* 0x16c */
184
185 /* New txstatus registers on corerev >= 5 */
186 uint32 frmtxstatus; /* 0x170 */
187 uint32 frmtxstatus2; /* 0x174 */
188 uint32 frmtxstatus3; /* 0x178 */ /* for corerev >= 40 */
189 uint32 frmtxstatus4; /* 0x17C */ /* for corerev >= 40 */
190
191 /* New TSF host access on corerev >= 3 */
192
193 uint32 tsf_timerlow; /* 0x180 */
194 uint32 tsf_timerhigh; /* 0x184 */
195 uint32 tsf_cfprep; /* 0x188 */
196 uint32 tsf_cfpstart; /* 0x18c */
197 uint32 tsf_cfpmaxdur32; /* 0x190 */
198 uint32 PAD[3]; /* 0x194 - 0x19c */
199
200 uint32 maccontrol1; /* 0x1a0 */
201 uint32 machwcap1; /* 0x1a4 */
202 uint32 PAD[14]; /* 0x1a8 - 0x1dc */
203
204 /* Clock control and hardware workarounds (corerev >= 13) */
205 uint32 clk_ctl_st; /* 0x1e0 */
206 uint32 hw_war;
207 uint32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
208 * moved to clk_ctl_st for corerev >= 17
209 */
210 uint32 PAD[5]; /* 0x1ec - 0x1fc */
211
212 /* 0x200-0x37F dma/pio registers */
213 volatile union {
214 fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */
215 fifo64_t f64regs[6]; /* on corerev >= 11 */
216 } fifo;
217
218 /* FIFO diagnostic port access */
219 dma32diag_t dmafifo; /* 0x380 - 0x38C */
220
221 uint32 aggfifocnt; /* 0x390 */
222 uint32 aggfifodata; /* 0x394 */
223 uint32 PAD[16]; /* 0x398 - 0x3d4 */
224 uint16 radioregaddr; /* 0x3d8 */
225 uint16 radioregdata; /* 0x3da */
226
227 /* time delay between the change on rf disable input and radio shutdown corerev 10 */
228 uint32 rfdisabledly; /* 0x3DC */
229
230 /* PHY register access */
231 uint16 phyversion; /* 0x3e0 - 0x0 */
232 uint16 phybbconfig; /* 0x3e2 - 0x1 */
233 uint16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
234 uint16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
235 uint16 phyrxstatus0; /* 0x3e8 - 0x4 */
236 uint16 phyrxstatus1; /* 0x3ea - 0x5 */
237 uint16 phycrsth; /* 0x3ec - 0x6 */
238 uint16 phytxerror; /* 0x3ee - 0x7 */
239 uint16 phychannel; /* 0x3f0 - 0x8 */
240 uint16 PAD[1]; /* 0x3f2 - 0x9 */
241 uint16 phytest; /* 0x3f4 - 0xa */
242 uint16 phy4waddr; /* 0x3f6 - 0xb */
243 uint16 phy4wdatahi; /* 0x3f8 - 0xc */
244 uint16 phy4wdatalo; /* 0x3fa - 0xd */
245 uint16 phyregaddr; /* 0x3fc - 0xe */
246 uint16 phyregdata; /* 0x3fe - 0xf */
247
248 /* IHR */ /* 0x400 - 0x7FE */
249
250 /* RXE Block */
251 uint16 PAD[3]; /* 0x400 - 0x406 */
252 uint16 rcv_fifo_ctl; /* 0x406 */
253 uint16 PAD; /* 0x408 - 0x40a */
254 uint16 rcv_frm_cnt; /* 0x40a */
255 uint16 PAD[4]; /* 0x40a - 0x414 */
256 uint16 rssi; /* 0x414 */
257 uint16 PAD[5]; /* 0x414 - 0x420 */
258
259 union {
260 struct {
261 uint16 rcm_ctl; /* 0x420 */
262 uint16 rcm_mat_data; /* 0x422 */
263 uint16 rcm_mat_mask; /* 0x424 */
264 uint16 rcm_mat_dly; /* 0x426 */
265 uint16 rcm_cond_mask_l; /* 0x428 */
266 uint16 rcm_cond_mask_h; /* 0x42A */
267 uint16 rcm_cond_dly; /* 0x42C */
268 uint16 PAD[1]; /* 0x42E */
269 uint16 ext_ihr_addr; /* 0x430 */
270 uint16 ext_ihr_data; /* 0x432 */
271 uint16 rxe_phyrs_2; /* 0x434 */
272 uint16 rxe_phyrs_3; /* 0x436 */
273 uint16 phy_mode; /* 0x438 */
274 uint16 rcmta_ctl; /* 0x43a */
275 uint16 rcmta_size; /* 0x43c */
276 uint16 rcmta_addr0; /* 0x43e */
277 uint16 rcmta_addr1; /* 0x440 */
278 uint16 rcmta_addr2; /* 0x442 */
279 uint16 PAD[30]; /* 0x444 - 0x480 */
280 } d11regs;
281
282 struct {
283 uint16 rcv_frm_cnt_q0; /* 0x420 */
284 uint16 rcv_frm_cnt_q1; /* 0x422 */
285 uint16 rcv_wrd_cnt_q0; /* 0x424 */
286 uint16 rcv_wrd_cnt_q1; /* 0x426 */
287 uint16 PAD[2]; /* 0x428 - 0x42A */
288 uint16 rcv_bm_sp_q0; /* 0x42C */
289 uint16 rcv_bm_ep_q0; /* 0x42E */
290 uint16 PAD[5]; /* 0x430 - 0x438 */
291 uint16 rcv_bm_sp_q1; /* 0x43a */
292 uint16 rcv_bm_ep_q1; /* 0x43c */
293 uint16 PAD[33]; /* 0x43e - 0x480 */
294 } d11acregs;
295 } u_rcv;
296
297 /* PSM Block */ /* 0x480 - 0x500 */
298
299 uint16 PAD; /* 0x480 */
300 uint16 psm_maccontrol_h; /* 0x482 */
301 uint16 psm_macintstatus_l; /* 0x484 */
302 uint16 psm_macintstatus_h; /* 0x486 */
303 uint16 psm_macintmask_l; /* 0x488 */
304 uint16 psm_macintmask_h; /* 0x48A */
305 uint16 PAD; /* 0x48C */
306 uint16 psm_maccommand; /* 0x48E */
307 uint16 psm_brc; /* 0x490 */
308 uint16 psm_phy_hdr_param; /* 0x492 */
309 uint16 psm_postcard; /* 0x494 */
310 uint16 psm_pcard_loc_l; /* 0x496 */
311 uint16 psm_pcard_loc_h; /* 0x498 */
312 uint16 psm_gpio_in; /* 0x49A */
313 uint16 psm_gpio_out; /* 0x49C */
314 uint16 psm_gpio_oe; /* 0x49E */
315
316 uint16 psm_bred_0; /* 0x4A0 */
317 uint16 psm_bred_1; /* 0x4A2 */
318 uint16 psm_bred_2; /* 0x4A4 */
319 uint16 psm_bred_3; /* 0x4A6 */
320 uint16 psm_brcl_0; /* 0x4A8 */
321 uint16 psm_brcl_1; /* 0x4AA */
322 uint16 psm_brcl_2; /* 0x4AC */
323 uint16 psm_brcl_3; /* 0x4AE */
324 uint16 psm_brpo_0; /* 0x4B0 */
325 uint16 psm_brpo_1; /* 0x4B2 */
326 uint16 psm_brpo_2; /* 0x4B4 */
327 uint16 psm_brpo_3; /* 0x4B6 */
328 uint16 psm_brwk_0; /* 0x4B8 */
329 uint16 psm_brwk_1; /* 0x4BA */
330 uint16 psm_brwk_2; /* 0x4BC */
331 uint16 psm_brwk_3; /* 0x4BE */
332
333 uint16 psm_base_0; /* 0x4C0 */
334 uint16 psm_base_1; /* 0x4C2 */
335 uint16 psm_base_2; /* 0x4C4 */
336 uint16 psm_base_3; /* 0x4C6 */
337 uint16 psm_base_4; /* 0x4C8 */
338 uint16 psm_base_5; /* 0x4CA */
339 uint16 psm_base_6; /* 0x4CC */
340 uint16 psm_ihr_err; /* 0x4CE */
341 uint16 psm_pc_reg_0; /* 0x4D0 */
342 uint16 psm_pc_reg_1; /* 0x4D2 */
343 uint16 psm_pc_reg_2; /* 0x4D4 */
344 uint16 psm_pc_reg_3; /* 0x4D6 */
345 uint16 psm_brc_1; /* 0x4D8 */
346 uint16 PAD[0xB]; /* 0x4DA - 0x4EE */
347 uint16 psm_corectlsts; /* 0x4f0 */ /* Corerev >= 13 */
348 uint16 PAD[0x7]; /* 0x4f2 - 0x4fE */
349
350 /* TXE0 Block */ /* 0x500 - 0x580 */
351 uint16 txe_ctl; /* 0x500 */
352 uint16 txe_aux; /* 0x502 */
353 uint16 txe_ts_loc; /* 0x504 */
354 uint16 txe_time_out; /* 0x506 */
355 uint16 txe_wm_0; /* 0x508 */
356 uint16 txe_wm_1; /* 0x50A */
357 uint16 txe_phyctl; /* 0x50C */
358 uint16 txe_status; /* 0x50E */
359 uint16 txe_mmplcp0; /* 0x510 */
360 uint16 txe_mmplcp1; /* 0x512 */
361 uint16 txe_phyctl1; /* 0x514 */
362
363 uint16 PAD[0x05]; /* 0x510 - 0x51E */
364
365 union {
366 struct {
367 /* Transmit control */
368 uint16 xmtfifodef; /* 0x520 */
369 uint16 xmtfifo_frame_cnt; /* 0x522 */ /* Corerev >= 16 */
370 uint16 xmtfifo_byte_cnt; /* 0x524 */ /* Corerev >= 16 */
371 uint16 xmtfifo_head; /* 0x526 */ /* Corerev >= 16 */
372 uint16 xmtfifo_rd_ptr; /* 0x528 */ /* Corerev >= 16 */
373 uint16 xmtfifo_wr_ptr; /* 0x52A */ /* Corerev >= 16 */
374 uint16 xmtfifodef1; /* 0x52C */ /* Corerev >= 16 */
375
376 /* AggFifo */
377 uint16 aggfifo_cmd; /* 0x52e */
378 uint16 aggfifo_stat; /* 0x530 */
379 uint16 aggfifo_cfgctl; /* 0x532 */
380 uint16 aggfifo_cfgdata; /* 0x534 */
381 uint16 aggfifo_mpdunum; /* 0x536 */
382 uint16 aggfifo_len; /* 0x538 */
383 uint16 aggfifo_bmp; /* 0x53A */
384 uint16 aggfifo_ackedcnt; /* 0x53C */
385 uint16 aggfifo_sel; /* 0x53E */
386
387 uint16 xmtfifocmd; /* 0x540 */
388 uint16 xmtfifoflush; /* 0x542 */
389 uint16 xmtfifothresh; /* 0x544 */
390 uint16 xmtfifordy; /* 0x546 */
391 uint16 xmtfifoprirdy; /* 0x548 */
392 uint16 xmtfiforqpri; /* 0x54A */
393 uint16 xmttplatetxptr; /* 0x54C */
394 uint16 PAD; /* 0x54E */
395 uint16 xmttplateptr; /* 0x550 */
396 uint16 smpl_clct_strptr; /* 0x552 */ /* Corerev >= 22 */
397 uint16 smpl_clct_stpptr; /* 0x554 */ /* Corerev >= 22 */
398 uint16 smpl_clct_curptr; /* 0x556 */ /* Corerev >= 22 */
399 uint16 aggfifo_data; /* 0x558 */
400 uint16 PAD[0x03]; /* 0x55A - 0x55E */
401 uint16 xmttplatedatalo; /* 0x560 */
402 uint16 xmttplatedatahi; /* 0x562 */
403
404 uint16 PAD[2]; /* 0x564 - 0x566 */
405
406 uint16 xmtsel; /* 0x568 */
407 uint16 xmttxcnt; /* 0x56A */
408 uint16 xmttxshmaddr; /* 0x56C */
409
410 uint16 PAD[0x09]; /* 0x56E - 0x57E */
411
412 /* TXE1 Block */
413 uint16 PAD[0x40]; /* 0x580 - 0x5FE */
414
415 /* TSF Block */
416 uint16 PAD[0X02]; /* 0x600 - 0x602 */
417 uint16 tsf_cfpstrt_l; /* 0x604 */
418 uint16 tsf_cfpstrt_h; /* 0x606 */
419 uint16 PAD[0X05]; /* 0x608 - 0x610 */
420 uint16 tsf_cfppretbtt; /* 0x612 */
421 uint16 PAD[0XD]; /* 0x614 - 0x62C */
422 uint16 tsf_clk_frac_l; /* 0x62E */
423 uint16 tsf_clk_frac_h; /* 0x630 */
424 uint16 PAD[0X14]; /* 0x632 - 0x658 */
425 uint16 tsf_random; /* 0x65A */
426 uint16 PAD[0x05]; /* 0x65C - 0x664 */
427 /* GPTimer 2 registers are corerev >= 3 */
428 uint16 tsf_gpt2_stat; /* 0x666 */
429 uint16 tsf_gpt2_ctr_l; /* 0x668 */
430 uint16 tsf_gpt2_ctr_h; /* 0x66A */
431 uint16 tsf_gpt2_val_l; /* 0x66C */
432 uint16 tsf_gpt2_val_h; /* 0x66E */
433 uint16 tsf_gptall_stat; /* 0x670 */
434 uint16 PAD[0x07]; /* 0x672 - 0x67E */
435
436 /* IFS Block */
437 uint16 ifs_sifs_rx_tx_tx; /* 0x680 */
438 uint16 ifs_sifs_nav_tx; /* 0x682 */
439 uint16 ifs_slot; /* 0x684 */
440 uint16 PAD; /* 0x686 */
441 uint16 ifs_ctl; /* 0x688 */
442 uint16 PAD[0x3]; /* 0x68a - 0x68F */
443 uint16 ifsstat; /* 0x690 */
444 uint16 ifsmedbusyctl; /* 0x692 */
445 uint16 iftxdur; /* 0x694 */
446 uint16 PAD[0x3]; /* 0x696 - 0x69b */
447 /* EDCF support in dot11macs with corerevs >= 16 */
448 uint16 ifs_aifsn; /* 0x69c */
449 uint16 ifs_ctl1; /* 0x69e */
450
451 /* New slow clock registers on corerev >= 5 */
452 uint16 scc_ctl; /* 0x6a0 */
453 uint16 scc_timer_l; /* 0x6a2 */
454 uint16 scc_timer_h; /* 0x6a4 */
455 uint16 scc_frac; /* 0x6a6 */
456 uint16 scc_fastpwrup_dly; /* 0x6a8 */
457 uint16 scc_per; /* 0x6aa */
458 uint16 scc_per_frac; /* 0x6ac */
459 uint16 scc_cal_timer_l; /* 0x6ae */
460 uint16 scc_cal_timer_h; /* 0x6b0 */
461 uint16 PAD; /* 0x6b2 */
462
463 /* BTCX block on corerev >=13 */
464 uint16 btcx_ctrl; /* 0x6b4 */
465 uint16 btcx_stat; /* 0x6b6 */
466 uint16 btcx_trans_ctrl; /* 0x6b8 */
467 uint16 btcx_pri_win; /* 0x6ba */
468 uint16 btcx_tx_conf_timer; /* 0x6bc */
469 uint16 btcx_ant_sw_timer; /* 0x6be */
470
471 uint16 btcx_prv_rfact_timer; /* 0x6c0 */
472 uint16 btcx_cur_rfact_timer; /* 0x6c2 */
473 uint16 btcx_rfact_dur_timer; /* 0x6c4 */
474
475 uint16 ifs_ctl_sel_pricrs; /* 0x6c6 */
476 uint16 ifs_ctl_sel_seccrs; /* 0x6c8 */
477 uint16 PAD[19]; /* 0x6ca - 0x6ee */
478
479 /* ECI regs on corerev >=14 */
480 uint16 btcx_eci_addr; /* 0x6f0 */
481 uint16 btcx_eci_data; /* 0x6f2 */
482
483 uint16 PAD[6];
484
485 /* NAV Block */
486 uint16 nav_ctl; /* 0x700 */
487 uint16 navstat; /* 0x702 */
488 uint16 PAD[0x3e]; /* 0x702 - 0x77E */
489
490 /* WEP/PMQ Block */ /* 0x780 - 0x7FE */
491 uint16 PAD[0x20]; /* 0x780 - 0x7BE */
492
493 uint16 wepctl; /* 0x7C0 */
494 uint16 wepivloc; /* 0x7C2 */
495 uint16 wepivkey; /* 0x7C4 */
496 uint16 wepwkey; /* 0x7C6 */
497
498 uint16 PAD[4]; /* 0x7C8 - 0x7CE */
499 uint16 pcmctl; /* 0X7D0 */
500 uint16 pcmstat; /* 0X7D2 */
501 uint16 PAD[6]; /* 0x7D4 - 0x7DE */
502
503 uint16 pmqctl; /* 0x7E0 */
504 uint16 pmqstatus; /* 0x7E2 */
505 uint16 pmqpat0; /* 0x7E4 */
506 uint16 pmqpat1; /* 0x7E6 */
507 uint16 pmqpat2; /* 0x7E8 */
508
509 uint16 pmqdat; /* 0x7EA */
510 uint16 pmqdator; /* 0x7EC */
511 uint16 pmqhst; /* 0x7EE */
512 uint16 pmqpath0; /* 0x7F0 */
513 uint16 pmqpath1; /* 0x7F2 */
514 uint16 pmqpath2; /* 0x7F4 */
515 uint16 pmqdath; /* 0x7F6 */
516
517 uint16 PAD[0x04]; /* 0x7F8 - 0x7FE */
518 /* SHM */ /* 0x800 - 0xEFE */
519 uint16 PAD[0x380]; /* 0x800 - 0xEFE */
520 } d11regs;
521
522 struct {
523 uint16 XmtFIFOFullThreshold; /* 0x520 */
524 uint16 XmtFifoFrameCnt; /* 0x522 */
525 uint16 PAD[1];
526 uint16 BMCReadReq; /* 0x526 */
527 uint16 BMCReadOffset; /* 0x528 */
528 uint16 BMCReadLength; /* 0x52a */
529 uint16 BMCReadStatus; /* 0x52c */
530 uint16 XmtShmAddr; /* 0x52e */
531 uint16 PsmMSDUAccess; /* 0x530 */
532 uint16 MSDUEntryBufCnt; /* 0x532 */
533 uint16 MSDUEntryStartIdx; /* 0x534 */
534 uint16 MSDUEntryEndIdx; /* 0x536 */
535 uint16 SampleCollectPlayPtrHigh; /* 0x538 */
536 uint16 SampleCollectCurPtrHigh; /* 0x53a */
537 uint16 BMCCmd1; /* 0x53c */
538 uint16 PAD[1];
539 uint16 BMCCTL; /* 0x540 */
540 uint16 BMCConfig; /* 0x542 */
541 uint16 BMCStartAddr; /* 0x544 */
542 uint16 BMCSize; /* 0x546 */
543 uint16 BMCCmd; /* 0x548 */
544 uint16 BMCMaxBuffers; /* 0x54a */
545 uint16 BMCMinBuffers; /* 0x54c */
546 uint16 BMCAllocCtl; /* 0x54e */
547 uint16 BMCDescrLen; /* 0x550 */
548 uint16 SampleCollectStartPtr; /* 0x552 */
549 uint16 SampleCollectStopPtr; /* 0x554 */
550 uint16 SampleCollectCurPtr; /* 0x556 */
551 uint16 SaveRestoreStartPtr; /* 0x558 */
552 uint16 SamplePlayStartPtr; /* 0x55a */
553 uint16 SamplePlayStopPtr; /* 0x55c */
554 uint16 XmtDMABusy; /* 0x55e */
555 uint16 XmtTemplateDataLo; /* 0x560 */
556 uint16 XmtTemplateDataHi; /* 0x562 */
557 uint16 XmtTemplatePtr; /* 0x564 */
558 uint16 XmtSuspFlush; /* 0x566 */
559 uint16 XmtFifoRqPrio; /* 0x568 */
560 uint16 BMCStatCtl; /* 0x56a */
561 uint16 BMCStatData; /* 0x56c */
562 uint16 BMCMSDUFifoStat; /* 0x56e */
563 uint16 PAD[328]; /* 0x570 - 0x800 */
564
565 /* AQM */
566 uint16 AQMConfig; /* 0x800 */
567 uint16 AQMFifoDef; /* 0x802 */
568 uint16 AQMMaxIdx; /* 0x804 */
569 uint16 AQMRcvdBA0; /* 0x806 */
570 uint16 AQMRcvdBA1; /* 0x808 */
571 uint16 AQMRcvdBA2; /* 0x80a */
572 uint16 AQMRcvdBA3; /* 0x80c */
573 uint16 AQMBaSSN; /* 0x80e */
574 uint16 AQMRefSN; /* 0x810 */
575 uint16 AQMMaxAggLenLow; /* 0x812 */
576 uint16 AQMMaxAggLenHi; /* 0x814 */
577 uint16 AQMAggParams; /* 0x816 */
578 uint16 AQMMinMpduLen; /* 0x818 */
579 uint16 AQMMacAdjLen; /* 0x81a */
580 uint16 DebugBusCtrl; /* 0x81c */
581 uint16 PAD[1];
582 uint16 AQMAggStats; /* 0x820 */
583 uint16 AQMAggLenLow; /* 0x822 */
584 uint16 AQMAggLenHi; /* 0x824 */
585 uint16 AQMIdxFifo; /* 0x826 */
586 uint16 AQMMpduLenFifo; /* 0x828 */
587 uint16 AQMTxCntFifo; /* 0x82a */
588 uint16 AQMUpdBA0; /* 0x82c */
589 uint16 AQMUpdBA1; /* 0x82e */
590 uint16 AQMUpdBA2; /* 0x830 */
591 uint16 AQMUpdBA3; /* 0x832 */
592 uint16 AQMAckCnt; /* 0x834 */
593 uint16 AQMConsCnt; /* 0x836 */
594 uint16 AQMFifoReady; /* 0x838 */
595 uint16 AQMStartLoc; /* 0x83a */
596 uint16 PAD[2];
597 uint16 TDCCTL; /* 0x840 */
598 uint16 TDC_Plcp0; /* 0x842 */
599 uint16 TDC_Plcp1; /* 0x844 */
600 uint16 TDC_FrmLen0; /* 0x846 */
601 uint16 TDC_FrmLen1; /* 0x848 */
602 uint16 TDC_Txtime; /* 0x84a */
603 uint16 TDC_VhtSigB0; /* 0x84c */
604 uint16 TDC_VhtSigB1; /* 0x84e */
605 uint16 TDC_LSigLen; /* 0x850 */
606 uint16 TDC_NSym0; /* 0x852 */
607 uint16 TDC_NSym1; /* 0x854 */
608 uint16 TDC_VhtPsduLen0; /* 0x856 */
609 uint16 TDC_VhtPsduLen1; /* 0x858 */
610 uint16 TDC_VhtMacPad; /* 0x85a */
611 uint16 PAD[2];
612 uint16 ShmDma_Ctl; /* 0x860 */
613 uint16 ShmDma_TxdcAddr; /* 0x862 */
614 uint16 ShmDma_ShmAddr; /* 0x864 */
615 uint16 ShmDma_XferCnt; /* 0x866 */
616 uint16 Txdc_Addr; /* 0x868 */
617 uint16 Txdc_Data; /* 0x86a */
618 uint16 PAD[10]; /* 0x86c - 0x880 */
619
620 /* RXE Register */
621 uint16 MHP_Status; /* 0x880 */
622 uint16 MHP_FC; /* 0x882 */
623 uint16 MHP_DUR; /* 0x884 */
624 uint16 MHP_SC; /* 0x886 */
625 uint16 MHP_QOS; /* 0x888 */
626 uint16 MHP_HTC_H; /* 0x88a */
627 uint16 MHP_HTC_L; /* 0x88c */
628 uint16 MHP_Addr1_H; /* 0x88e */
629 uint16 MHP_Addr1_M; /* 0x890 */
630 uint16 MHP_Addr1_L; /* 0x892 */
631 uint16 PAD[6]; /* 0x894 - 0x8a0 */
632 uint16 MHP_Addr2_H; /* 0x8a0 */
633 uint16 MHP_Addr2_M; /* 0x8a2 */
634 uint16 MHP_Addr2_L; /* 0x8a4 */
635 uint16 MHP_Addr3_H; /* 0x8a6 */
636 uint16 MHP_Addr3_M; /* 0x8a8 */
637 uint16 MHP_Addr3_L; /* 0x8aa */
638 uint16 MHP_Addr4_H; /* 0x8ac */
639 uint16 MHP_Addr4_M; /* 0x8ae */
640 uint16 MHP_Addr4_L; /* 0x8b0 */
641 uint16 MHP_CFC; /* 0x8b2 */
642 uint16 PAD[6]; /* 0x8b4 - 0x8c0 */
643 uint16 DAGG_CTL2; /* 0x8c0 */
644 uint16 DAGG_BYTESLEFT; /* 0x8c2 */
645 uint16 DAGG_SH_OFFSET; /* 0x8c4 */
646 uint16 DAGG_STAT; /* 0x8c6 */
647 uint16 DAGG_LEN; /* 0x8c8 */
648 uint16 TXBA_CTL; /* 0x8ca */
649 uint16 TXBA_DataSel; /* 0x8cc */
650 uint16 TXBA_Data; /* 0x8ce */
651 uint16 PAD[8]; /* 0x8d0 - 0x8e0 */
652 uint16 AMT_CTL; /* 0x8e0 */
653 uint16 AMT_Status; /* 0x8e2 */
654 uint16 AMT_Limit; /* 0x8e4 */
655 uint16 AMT_Attr; /* 0x8e6 */
656 uint16 AMT_Match1; /* 0x8e8 */
657 uint16 AMT_Match2; /* 0x8ea */
658 uint16 AMT_Table_Addr; /* 0x8ec */
659 uint16 AMT_Table_Data; /* 0x8ee */
660 uint16 AMT_Table_Val; /* 0x8f0 */
661 uint16 AMT_DBG_SEL; /* 0x8f2 */
662 uint16 PAD[6]; /* 0x8f4 - 0x900 */
663 uint16 RoeCtrl; /* 0x900 */
664 uint16 RoeStatus; /* 0x902 */
665 uint16 RoeIPChkSum; /* 0x904 */
666 uint16 RoeTCPUDPChkSum; /* 0x906 */
667 uint16 PAD[12]; /* 0x908 - 0x920 */
668 uint16 PSOCtl; /* 0x920 */
669 uint16 PSORxWordsWatermark; /* 0x922 */
670 uint16 PSORxCntWatermark; /* 0x924 */
671 uint16 PAD[5]; /* 0x926 - 0x930 */
672 uint16 OBFFCtl; /* 0x930 */
673 uint16 OBFFRxWordsWatermark; /* 0x932 */
674 uint16 OBFFRxCntWatermark; /* 0x934 */
675 uint16 PAD[101]; /* 0x936 - 0xa00 */
676
677 /* TOE */
678 uint16 ToECTL; /* 0xa00 */
679 uint16 ToERst; /* 0xa02 */
680 uint16 ToECSumNZ; /* 0xa04 */
681 uint16 PAD[29]; /* 0xa06 - 0xa40 */
682
683 uint16 TxSerialCtl; /* 0xa40 */
684 uint16 TxPlcpLSig0; /* 0xa42 */
685 uint16 TxPlcpLSig1; /* 0xa44 */
686 uint16 TxPlcpHtSig0; /* 0xa46 */
687 uint16 TxPlcpHtSig1; /* 0xa48 */
688 uint16 TxPlcpHtSig2; /* 0xa4a */
689 uint16 TxPlcpVhtSigB0; /* 0xa4c */
690 uint16 TxPlcpVhtSigB1; /* 0xa4e */
691 uint16 PAD[1];
692
693 uint16 MacHdrFromShmLen; /* 0xa52 */
694 uint16 TxPlcpLen; /* 0xa54 */
695 uint16 PAD[1];
696
697 uint16 TxBFRptLen; /* 0xa58 */
698 uint16 PAD[3];
699
700 uint16 TXBFCtl; /* 0xa60 */
701 uint16 BfmRptOffset; /* 0xa62 */
702 uint16 BfmRptLen; /* 0xa64 */
703 uint16 TXBFBfeRptRdCnt; /* 0xa66 */
704 uint16 PAD[588]; /* 0xa68 - 0xEFE */
705 } d11acregs;
706 } u;
707 /* SB configuration registers: 0xF00 */
708 sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
709 } d11regs_t;
710
711 #define PIHR_BASE 0x0400 /* byte address of packed IHR region */
712
713 /* biststatus */
714 #define BT_DONE (1U << 31) /* bist done */
715 #define BT_B2S (1 << 30) /* bist2 ram summary bit */
716
717 /* DMA intstatus and intmask */
718 #define I_PC (1 << 10) /* pci descriptor error */
719 #define I_PD (1 << 11) /* pci data error */
720 #define I_DE (1 << 12) /* descriptor protocol error */
721 #define I_RU (1 << 13) /* receive descriptor underflow */
722 #define I_RO (1 << 14) /* receive fifo overflow */
723 #define I_XU (1 << 15) /* transmit fifo underflow */
724 #define I_RI (1 << 16) /* receive interrupt */
725 #define I_XI (1 << 24) /* transmit interrupt */
726
727 /* interrupt receive lazy */
728 #define IRL_TO_MASK 0x00ffffff /* timeout */
729 #define IRL_FC_MASK 0xff000000 /* frame count */
730 #define IRL_FC_SHIFT 24 /* frame count */
731 #define IRL_DISABLE 0x01000000 /* Disabled value: int on 1 frame, zero time */
732
733 /* maccontrol register */
734 #define MCTL_GMODE (1U << 31)
735 #define MCTL_DISCARD_PMQ (1 << 30)
736 #define MCTL_DISCARD_TXSTATUS (1 << 29)
737 #define MCTL_TBTT_HOLD (1 << 28)
738 #define MCTL_CLOSED_NETWORK (1 << 27)
739 #define MCTL_WAKE (1 << 26)
740 #define MCTL_HPS (1 << 25)
741 #define MCTL_PROMISC (1 << 24)
742 #define MCTL_KEEPBADFCS (1 << 23)
743 #define MCTL_KEEPCONTROL (1 << 22)
744 #define MCTL_PHYLOCK (1 << 21)
745 #define MCTL_BCNS_PROMISC (1 << 20)
746 #define MCTL_LOCK_RADIO (1 << 19)
747 #define MCTL_AP (1 << 18)
748 #define MCTL_INFRA (1 << 17)
749 #define MCTL_BIGEND (1 << 16)
750 #define MCTL_GPOUT_SEL_MASK (3 << 14)
751 #define MCTL_GPOUT_SEL_SHIFT 14
752 #define MCTL_EN_PSMDBG (1 << 13)
753 #define MCTL_IHR_EN (1 << 10)
754 #define MCTL_SHM_UPPER (1 << 9)
755 #define MCTL_SHM_EN (1 << 8)
756 #define MCTL_PSM_JMP_0 (1 << 2)
757 #define MCTL_PSM_RUN (1 << 1)
758 #define MCTL_EN_MAC (1 << 0)
759
760 /* maccontrol1 register */
761 #define MCTL1_GCPS 0x00000001
762 #define MCTL1_EGS_MASK 0x0000c000
763 #define MCTL1_EGS_SHIFT 14
764 #define MCTL1_EGS_MASK_REV26 0x00001f00
765 #define MCTL1_EGS_SHIFT_REV26 8
766
767 /* maccommand register */
768 #define MCMD_BCN0VLD (1 << 0)
769 #define MCMD_BCN1VLD (1 << 1)
770 #define MCMD_DIRFRMQVAL (1 << 2)
771 #define MCMD_CCA (1 << 3)
772 #define MCMD_BG_NOISE (1 << 4)
773 #define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
774 #define MCMD_SLOWCAL (1 << 6)
775 #define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
776 #define MCMD_BCNREL (1 << 8 ) /* release anybuffered bcns from ucode */
777
778 /* macintstatus/macintmask */
779 #define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
780 #define MI_BCNTPL (1 << 1) /* beacon template available */
781 #define MI_TBTT (1 << 2) /* TBTT indication */
782 #define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
783 #define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
784 #define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
785 #define MI_PMQ (1 << 6) /* PMQ entries available */
786 #define MI_ALTTFS (1 << 7) /* non-specific gen-stat bits that are set by PSM */
787 #define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
788 #define MI_MACTXERR (1 << 9) /* MAC level Tx error */
789 #define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
790 #define MI_PHYTXERR (1 << 11) /* PHY Tx error */
791 #define MI_PME (1 << 12) /* Power Management Event */
792 #define MI_GP0 (1 << 13) /* General-purpose timer0 */
793 #define MI_GP1 (1 << 14) /* General-purpose timer1 */
794 #define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
795 #define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
796 #define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
797 #define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
798 #define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
799 #define MI_PRQ (1 << 20) /* Probe response queue needs attention */
800 #define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
801 #define MI_BT_RFACT_STUCK (1 << 22) /* MAC has detected invalid BT_RFACT pin,
802 * valid when rev < 15
803 */
804 #define MI_TTTT (1 << 22) /* Target TIM Transmission Time,
805 * valid in rev = 26/29, or rev >= 42
806 */
807 #define MI_BT_PRED_REQ (1 << 23) /* MAC requested driver BTCX predictor calc */
808 #define MI_P2P (1 << 25) /* WiFi P2P interrupt */
809 #define MI_DMATX (1 << 26) /* MAC new frame ready */
810 #define MI_TSSI_LIMIT (1 << 27) /* Tssi Limit Reach, TxIdx=0/127 Interrupt */
811 #define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input
812 * (corerev >= 10)
813 */
814 #define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */
815 #define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
816 #define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */
817
818 #define MI_RXOV MI_NSPECGEN_1 /* rxfifo overflow interrupt */
819
820 /* Mac capabilities registers */
821 /* machwcap */
822 #define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
823 #define MCAP_TKIPPH2KEY 0x40000000 /* TKIP phase 2 key hardware present */
824 #define MCAP_BTCX 0x20000000 /* BT coexistence hardware and pins present */
825 #define MCAP_MBSS 0x10000000 /* Multi-BSS hardware present */
826 #define MCAP_RXFSZ_MASK 0x03f80000 /* Rx fifo size (* 512 bytes) */
827 #define MCAP_RXFSZ_SHIFT 19
828 #define MCAP_NRXQ_MASK 0x00070000 /* Max Rx queues supported - 1 */
829 #define MCAP_NRXQ_SHIFT 16
830 #define MCAP_UCMSZ_MASK 0x0000e000 /* Ucode memory size */
831 #define MCAP_UCMSZ_3K3 0 /* 3328 Words Ucode memory, in unit of 50-bit */
832 #define MCAP_UCMSZ_4K 1 /* 4096 Words Ucode memory */
833 #define MCAP_UCMSZ_5K 2 /* 5120 Words Ucode memory */
834 #define MCAP_UCMSZ_6K 3 /* 6144 Words Ucode memory */
835 #define MCAP_UCMSZ_8K 4 /* 8192 Words Ucode memory */
836 #define MCAP_UCMSZ_SHIFT 13
837 #define MCAP_TXFSZ_MASK 0x00000ff8 /* Tx fifo size (* 512 bytes) */
838 #define MCAP_TXFSZ_SHIFT 3
839 #define MCAP_NTXQ_MASK 0x00000007 /* Max Tx queues supported - 1 */
840 #define MCAP_NTXQ_SHIFT 0
841
842 /* machwcap1 */
843 #define MCAP1_ERC_MASK 0x00000001 /* external radio coexistence */
844 #define MCAP1_ERC_SHIFT 0
845 #define MCAP1_SHMSZ_MASK 0x0000000e /* shm size (corerev >= 16) */
846 #define MCAP1_SHMSZ_SHIFT 1
847 #define MCAP1_SHMSZ_1K 0 /* 1024 words in unit of 32-bit */
848 #define MCAP1_SHMSZ_2K 1 /* 1536 words in unit of 32-bit */
849
850 /* BTCX control */
851 #define BTCX_CTRL_EN 0x0001 /* Enable BTCX module */
852 #define BTCX_CTRL_SW 0x0002 /* Enable software override */
853
854 /* BTCX status */
855 #define BTCX_STAT_RA 0x0001 /* RF_ACTIVE state */
856
857 /* BTCX transaction control */
858 #define BTCX_TRANS_ANTSEL 0x0040 /* ANTSEL output */
859 #define BTCX_TRANS_TXCONF 0x0080 /* TX_CONF output */
860
861 /* BTCX stats block */
862 #define M_BTCX_DBGBLK (0x3d2*2)
863 #define M_BTCX_DBGBLK_11AC (0x3fc*2)
864 #define C_BTCX_DBGBLK_SZ 6 /* Number of 16bit words */
865
866 /* pmqhost data */
867 #define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
868 #define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
869 #define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
870 #define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
871 #define PMQH_PMPS 0x00200000 /* PM Mode PRETEND */
872 #define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
873 #define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
874 #define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
875 #define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
876 #define PMQH_OFLO 0x00000004 /* pmq overflow indication */
877 #define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
878
879 /* phydebug (corerev >= 3) */
880 #define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
881 #define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
882 #define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
883 #define PDBG_TXE (1 << 3) /* phy is signaling a transmit Error to the mac */
884 #define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
885 #define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
886 #define PDBG_RXFRG (1 << 6) /* rx start not asserted */
887 #define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
888 #define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
889
890 /* objaddr register */
891 #define OBJADDR_SEL_MASK 0x000F0000
892 #define OBJADDR_UCM_SEL 0x00000000
893 #define OBJADDR_SHM_SEL 0x00010000
894 #define OBJADDR_SCR_SEL 0x00020000
895 #define OBJADDR_IHR_SEL 0x00030000
896 #define OBJADDR_RCMTA_SEL 0x00040000
897 #define OBJADDR_AMT_SEL 0x00040000
898 #define OBJADDR_SRCHM_SEL 0x00060000
899 #define OBJADDR_WINC 0x01000000
900 #define OBJADDR_RINC 0x02000000
901 #define OBJADDR_AUTO_INC 0x03000000
902
903 /* pcmaddr bits */
904 #define PCMADDR_INC 0x4000
905 #define PCMADDR_UCM_SEL 0x0000
906
907 #define WEP_PCMADDR 0x07d4
908 #define WEP_PCMDATA 0x07d6
909
910 /* frmtxstatus */
911 #define TXS_V (1 << 0) /* valid bit */
912
913 #define TXS_STATUS_MASK 0xffff
914 /* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
915 #define TXS_COMPAT_MASK 0x3
916 #define TXS_COMPAT_SHIFT 1
917 #define TXS_FID_MASK 0xffff0000
918 #define TXS_FID_SHIFT 16
919
920 /* frmtxstatus2 */
921 #define TXS_SEQ_MASK 0xffff
922 #define TXS_PTX_MASK 0xff0000
923 #define TXS_PTX_SHIFT 16
924 #define TXS_MU_MASK 0x01000000
925 #define TXS_MU_SHIFT 24
926
927 /* clk_ctl_st, corerev >= 17 */
928 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
929 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
930 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
931 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
932
933 /* HT Cloclk Ctrl and Clock Avail for 4313 */
934 #define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
935 #define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
936
937 /* d11_pwrctl, corerev16 only */
938 #define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */
939 #define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */
940
941
942 /* tsf_cfprep register */
943 #define CFPREP_CBI_MASK 0xffffffc0
944 #define CFPREP_CBI_SHIFT 6
945 #define CFPREP_CFPP 0x00000001
946
947 /* transmit fifo control for 2-byte pio */
948 #define XFC_BV_MASK 0x3 /* bytes valid */
949 #define XFC_LO (1 << 0) /* low byte valid */
950 #define XFC_HI (1 << 1) /* high byte valid */
951 #define XFC_BOTH (XFC_HI | XFC_LO) /* both bytes valid */
952 #define XFC_EF (1 << 2) /* end of frame */
953 #define XFC_FR (1 << 3) /* frame ready */
954 #define XFC_FL (1 << 5) /* flush request */
955 #define XFC_FP (1 << 6) /* flush pending */
956 #define XFC_SE (1 << 7) /* suspend request */
957 #define XFC_SP (1 << 8)
958 #define XFC_CC_MASK 0xfc00 /* committed count */
959 #define XFC_CC_SHIFT 10
960
961 /* transmit fifo control for 4-byte pio */
962 #define XFC4_BV_MASK 0xf /* bytes valid */
963 #define XFC4_EF (1 << 4) /* end of frame */
964 #define XFC4_FR (1 << 7) /* frame ready */
965 #define XFC4_SE (1 << 8) /* suspend request */
966 #define XFC4_SP (1 << 9)
967 #define XFC4_FL (1 << 10) /* flush request */
968 #define XFC4_FP (1 << 11) /* flush pending */
969
970 /* receive fifo control */
971 #define RFC_FR (1 << 0) /* frame ready */
972 #define RFC_DR (1 << 1) /* data ready */
973
974 /* tx fifo sizes for corerev >= 9 */
975 /* tx fifo sizes values are in terms of 256 byte blocks */
976 #define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
977 #define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
978 #define TXFIFOCMD_FIFOSEL_SET(val) ((val & 0x7) << TXFIFOCMD_FIFOSEL_SHIFT) /* fifo */
979 #define TXFIFOCMD_FIFOSEL_GET(val) ((val >> TXFIFOCMD_FIFOSEL_SHIFT) & 0x7) /* fifo */
980 #define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
981
982 #define TXFIFO_FIFO_START(def, def1) ((def & 0xFF) | ((def1 & 0xFF) << 8))
983 #define TXFIFO_FIFO_END(def, def1) (((def & 0xFF00) >> 8) | (def1 & 0xFF00))
984
985 /* Must redefine to 65 for 16 MBSS */
986 #ifdef WLLPRS
987 #define TXFIFO_START_BLK16 (65+16) /* Base address + 32 * 512 B/P + 8 * 512 11g P */
988 #else /* WLLPRS */
989 #define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
990 #endif /* WLLPRS */
991 #define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
992 #define TXFIFO_START_BLK_NIN 7 /* Base address + 6 * 256 B */
993 #define TXFIFO_SIZE_PER_UNIT 256 /* one unit corresponds to 256 bytes */
994 #define TXFIFO_AC_SIZE_PER_UNIT 512 /* one unit corresponds to 512 bytes */
995 #define TXFIFO_SIZE_UNIT (wlc->txfifo_size_unit)
996 #define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
997
998 /* phy versions, PhyVersion:Revision field */
999 #define PV_AV_MASK 0xf000 /* analog block version */
1000 #define PV_AV_SHIFT 12 /* analog block version bitfield offset */
1001 #define PV_PT_MASK 0x0f00 /* phy type */
1002 #define PV_PT_SHIFT 8 /* phy type bitfield offset */
1003 #define PV_PV_MASK 0x000f /* phy version */
1004 #define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
1005
1006 /* phy types, PhyVersion:PhyType field */
1007 #define PHY_TYPE_A 0 /* A-Phy value */
1008 #define PHY_TYPE_B 1 /* B-Phy value */
1009 #define PHY_TYPE_G 2 /* G-Phy value */
1010 #define PHY_TYPE_N 4 /* N-Phy value */
1011 #define PHY_TYPE_LP 5 /* LP-Phy value */
1012 #define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
1013 #define PHY_TYPE_HT 7 /* 3x3 HTPhy value */
1014 #define PHY_TYPE_LCN 8 /* LCN-Phy value */
1015 #define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
1016 #define PHY_TYPE_LCN40 10 /* LCN40-Phy value */
1017 #define PHY_TYPE_AC 11 /* AC-Phy value */
1018 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
1019
1020 /* analog types, PhyVersion:AnalogType field */
1021 #define ANA_11G_018 1
1022 #define ANA_11G_018_ALL 2
1023 #define ANA_11G_018_ALLI 3
1024 #define ANA_11G_013 4
1025 #define ANA_11N_013 5
1026 #define ANA_11LP_013 6
1027
1028 /* 802.11a PLCP header def */
1029 typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
1030 BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
1031 uint8 rlpt[3]; /* rate, length, parity, tail */
1032 uint16 service;
1033 uint8 pad;
1034 } BWL_POST_PACKED_STRUCT;
1035
1036 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
1037 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
1038 #define D11A_PHY_HDR_GLENGTH(phdr) (((*((uint32 *)((phdr)->rlpt))) >> 5) & 0x0fff)
1039 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
1040 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
1041
1042 /* rate encoded per 802.11a-1999 sec 17.3.4.1 */
1043 #define D11A_PHY_HDR_SRATE(phdr, rate) \
1044 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
1045 /* set reserved field to zero */
1046 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
1047 /* length is number of octets in PSDU */
1048 #define D11A_PHY_HDR_SLENGTH(phdr, length) \
1049 (*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \
1050 (((length) & 0x0fff) << 5))
1051 /* set the tail to all zeros */
1052 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
1053
1054 #define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
1055 #define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
1056
1057 #define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
1058
1059 #define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
1060 #define D11A_PHY_PRE_TIME (16)
1061 #define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
1062
1063 /* 802.11b PLCP header def */
1064 typedef struct cck_phy_hdr cck_phy_hdr_t;
1065 BWL_PRE_PACKED_STRUCT struct cck_phy_hdr {
1066 uint8 signal;
1067 uint8 service;
1068 uint16 length;
1069 uint16 crc;
1070 } BWL_POST_PACKED_STRUCT;
1071
1072 #define D11B_PHY_HDR_LEN 6
1073
1074 #define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
1075
1076 #define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
1077 #define D11B_PHY_LPRE_TIME (144)
1078 #define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
1079
1080 #define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
1081 #define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
1082 #define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
1083
1084 #define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
1085 #define D11B_PLCP_SIGNAL_LE (1 << 7)
1086
1087 /* AMPDUXXX: move to ht header file once it is ready: Mimo PLCP */
1088 #define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
1089 #define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
1090 #define MIMO_PLCP_AMPDU 0x08 /* ampdu */
1091
1092 #define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
1093 #define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
1094 #define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
1095 plcp[1] = len & 0xff; plcp[2] = ((len >> 8) & 0xff);
1096
1097 #define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
1098 #define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
1099 #define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
1100
1101 /* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
1102 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
1103 * padding added in the ucode.
1104 */
1105 #define D11_PHY_HDR_LEN 6
1106
1107 /* For the AC phy PLCP is 12 bytes and not all bytes are are used for all the modulations */
1108 #define D11AC_PHY_HDR_LEN 12
1109 #define D11AC_PHY_VHT_PLCP_OFFSET 0
1110 #define D11AC_PHY_HTMM_PLCP_OFFSET 0
1111 #define D11AC_PHY_HTGF_PLCP_OFFSET 3
1112 #define D11AC_PHY_OFDM_PLCP_OFFSET 3
1113 #define D11AC_PHY_CCK_PLCP_OFFSET 6
1114
1115 /* TX DMA buffer header */
1116 typedef struct d11txh d11txh_t;
1117 BWL_PRE_PACKED_STRUCT struct d11txh {
1118 uint16 MacTxControlLow; /* 0x0 */
1119 uint16 MacTxControlHigh; /* 0x1 */
1120 uint16 MacFrameControl; /* 0x2 */
1121 uint16 TxFesTimeNormal; /* 0x3 */
1122 uint16 PhyTxControlWord; /* 0x4 */
1123 uint16 PhyTxControlWord_1; /* 0x5 */
1124 uint16 PhyTxControlWord_1_Fbr; /* 0x6 */
1125 uint16 PhyTxControlWord_1_Rts; /* 0x7 */
1126 uint16 PhyTxControlWord_1_FbrRts; /* 0x8 */
1127 uint16 MainRates; /* 0x9 */
1128 uint16 XtraFrameTypes; /* 0xa */
1129 uint8 IV[16]; /* 0x0b - 0x12 */
1130 uint8 TxFrameRA[6]; /* 0x13 - 0x15 */
1131 uint16 TxFesTimeFallback; /* 0x16 */
1132 uint8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
1133 uint16 RTSDurFallback; /* 0x1a */
1134 uint8 FragPLCPFallback[6]; /* 0x1b - 1d */
1135 uint16 FragDurFallback; /* 0x1e */
1136 uint16 MModeLen; /* 0x1f */
1137 uint16 MModeFbrLen; /* 0x20 */
1138 uint16 TstampLow; /* 0x21 */
1139 uint16 TstampHigh; /* 0x22 */
1140 uint16 ABI_MimoAntSel; /* 0x23 */
1141 uint16 PreloadSize; /* 0x24 */
1142 uint16 AmpduSeqCtl; /* 0x25 */
1143 uint16 TxFrameID; /* 0x26 */
1144 uint16 TxStatus; /* 0x27 */
1145 uint16 MaxNMpdus; /* 0x28 corerev >=16 */
1146 BWL_PRE_PACKED_STRUCT union {
1147 uint16 MaxAggDur; /* 0x29 corerev >=16 */
1148 uint16 MaxAggLen;
1149 } BWL_POST_PACKED_STRUCT u1;
1150 BWL_PRE_PACKED_STRUCT union {
1151 uint16 MaxRNum; /* 0x2a corerev >=16 */
1152 uint16 MaxAggLen_FBR;
1153 } BWL_POST_PACKED_STRUCT u2;
1154 uint16 MinMBytes; /* 0x2b corerev >=16 */
1155 uint8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
1156 struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */
1157 uint16 pad; /* 0x37 */
1158 } BWL_POST_PACKED_STRUCT;
1159
1160 #define D11_TXH_LEN 112 /* bytes */
1161
1162 /* Frame Types */
1163 #define FT_CCK 0
1164 #define FT_OFDM 1
1165 #define FT_HT 2
1166 #define FT_VHT 3
1167
1168 /* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
1169 #define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
1170 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
1171 #define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
1172 #define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
1173 #define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
1174
1175 /* MacTxControlLow */
1176 #define TXC_AMIC 0x8000
1177 #define TXC_USERIFS 0x4000
1178 #define TXC_LIFETIME 0x2000
1179 #define TXC_FRAMEBURST 0x1000
1180 #define TXC_SENDCTS 0x0800
1181 #define TXC_AMPDU_MASK 0x0600
1182 #define TXC_BW_40 0x0100
1183 #define TXC_FREQBAND_5G 0x0080
1184 #define TXC_DFCS 0x0040
1185 #define TXC_IGNOREPMQ 0x0020
1186 #define TXC_HWSEQ 0x0010
1187 #define TXC_STARTMSDU 0x0008
1188 #define TXC_SENDRTS 0x0004
1189 #define TXC_LONGFRAME 0x0002
1190 #define TXC_IMMEDACK 0x0001
1191
1192 /* MacTxControlHigh */
1193 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
1194 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
1195 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
1196 * 1 = SHORT for OFDM/GF for MIMO
1197 * 0 = LONG for CCK/MM for MIMO
1198 */
1199 /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
1200 #define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
1201 #define TXC_SECKEY_MASK 0x0FF0
1202 #define TXC_SECKEY_SHIFT 4
1203 #define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
1204 #define TXC_SECTYPE_MASK 0x0007
1205 #define TXC_SECTYPE_SHIFT 0
1206
1207 /* Null delimiter for Fallback rate */
1208 #define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
1209
1210 /* PhyTxControl for Mimophy */
1211 #define PHY_TXC_PWR_MASK 0xFC00
1212 #define PHY_TXC_PWR_SHIFT 10
1213 #define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
1214 #define PHY_TXC_ANT_SHIFT 6
1215 #define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
1216 #define PHY_TXC_LPPHY_ANT_LAST 0x0000
1217 #define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
1218 #define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
1219 #define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
1220 #define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
1221 #define PHY_TXC_SHORT_HDR 0x0010
1222 #define PHY_TXC_FT_MASK 0x0003
1223 #define PHY_TXC_FT_CCK 0x0000
1224 #define PHY_TXC_FT_OFDM 0x0001
1225 #define PHY_TXC_FT_HT 0x0002
1226 #define PHY_TXC_FT_VHT 0x0003
1227
1228 #define PHY_TXC_OLD_ANT_0 0x0000
1229 #define PHY_TXC_OLD_ANT_1 0x0100
1230 #define PHY_TXC_OLD_ANT_LAST 0x0300
1231
1232 /* PhyTxControl_1 for Mimophy */
1233 #define PHY_TXC1_BW_MASK 0x0007
1234 #define PHY_TXC1_BW_10MHZ 0
1235 #define PHY_TXC1_BW_10MHZ_UP 1
1236 #define PHY_TXC1_BW_20MHZ 2
1237 #define PHY_TXC1_BW_20MHZ_UP 3
1238 #define PHY_TXC1_BW_40MHZ 4
1239 #define PHY_TXC1_BW_40MHZ_DUP 5
1240 #define PHY_TXC1_MODE_SHIFT 3
1241 #define PHY_TXC1_MODE_MASK 0x0038
1242 #define PHY_TXC1_MODE_SISO 0
1243 #define PHY_TXC1_MODE_CDD 1
1244 #define PHY_TXC1_MODE_STBC 2
1245 #define PHY_TXC1_MODE_SDM 3
1246 #define PHY_TXC1_CODE_RATE_SHIFT 8
1247 #define PHY_TXC1_CODE_RATE_MASK 0x0700
1248 #define PHY_TXC1_CODE_RATE_1_2 0
1249 #define PHY_TXC1_CODE_RATE_2_3 1
1250 #define PHY_TXC1_CODE_RATE_3_4 2
1251 #define PHY_TXC1_CODE_RATE_4_5 3
1252 #define PHY_TXC1_CODE_RATE_5_6 4
1253 #define PHY_TXC1_CODE_RATE_7_8 6
1254 #define PHY_TXC1_MOD_SCHEME_SHIFT 11
1255 #define PHY_TXC1_MOD_SCHEME_MASK 0x3800
1256 #define PHY_TXC1_MOD_SCHEME_BPSK 0
1257 #define PHY_TXC1_MOD_SCHEME_QPSK 1
1258 #define PHY_TXC1_MOD_SCHEME_QAM16 2
1259 #define PHY_TXC1_MOD_SCHEME_QAM64 3
1260 #define PHY_TXC1_MOD_SCHEME_QAM256 4
1261
1262 /* PhyTxControl for HTphy that are different from Mimophy */
1263 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
1264 #define PHY_TXC_HTCORE_MASK 0x03C0 /* core enable core3:core0, 1=enable, 0=disable */
1265 #define PHY_TXC_HTCORE_SHIFT 6 /* bit 6, 7, 8, 9 */
1266 #define PHY_TXC_HTANT_IDX_MASK 0x3C00 /* 4-bit, 16 possible antenna configuration */
1267 #define PHY_TXC_HTANT_IDX_SHIFT 10
1268 #define PHY_TXC_HTANT_IDX0 0
1269 #define PHY_TXC_HTANT_IDX1 1
1270 #define PHY_TXC_HTANT_IDX2 2
1271 #define PHY_TXC_HTANT_IDX3 3
1272
1273 /* PhyTxControl_1 for HTphy that are different from Mimophy */
1274 #define PHY_TXC1_HTSPARTIAL_MAP_MASK 0x7C00 /* bit 14:10 */
1275 #define PHY_TXC1_HTSPARTIAL_MAP_SHIFT 10
1276 #define PHY_TXC1_HTTXPWR_OFFSET_MASK 0x01f8 /* bit 8:3 */
1277 #define PHY_TXC1_HTTXPWR_OFFSET_SHIFT 3
1278 #define PHY_TXC1_TXBF_USR_IDX_SHIFT 10
1279
1280 /* XtraFrameTypes */
1281 #define XFTS_RTS_FT_SHIFT 2
1282 #define XFTS_FBRRTS_FT_SHIFT 4
1283 #define XFTS_CHANNEL_SHIFT 8
1284
1285 /* Antenna diversity bit in ant_wr_settle */
1286 #define PHY_AWS_ANTDIV 0x2000
1287
1288 /* PHY CRS states */
1289 #define APHY_CRS_RESET 0
1290 #define APHY_CRS_SEARCH 1
1291 #define APHY_CRS_CLIP 3
1292 #define APHY_CRS_G_CLIP_POW1 4
1293 #define APHY_CRS_G_CLIP_POW2 5
1294 #define APHY_CRS_G_CLIP_NRSSI1 6
1295 #define APHY_CRS_G_CLIP_NRSSI1_POW1 7
1296 #define APHY_CRS_G_CLIP_NRSSI2 8
1297
1298 /* IFS ctl */
1299 #define IFS_USEEDCF (1 << 2)
1300
1301 /* IFS ctl1 */
1302 #define IFS_CTL1_EDCRS (1 << 3)
1303 #define IFS_CTL1_EDCRS_20L (1 << 4)
1304 #define IFS_CTL1_EDCRS_40 (1 << 5)
1305 #define IFS_EDCRS_MASK (IFS_CTL1_EDCRS | IFS_CTL1_EDCRS_20L | IFS_CTL1_EDCRS_40)
1306 #define IFS_EDCRS_SHIFT 3
1307
1308 /* IFS ctl sel pricrs */
1309 #define IFS_CTL_CRS_SEL_20LL 1
1310 #define IFS_CTL_CRS_SEL_20LU 2
1311 #define IFS_CTL_CRS_SEL_20UL 4
1312 #define IFS_CTL_CRS_SEL_20UU 8
1313 #define IFS_CTL_CRS_SEL_MASK (IFS_CTL_CRS_SEL_20LL | IFS_CTL_CRS_SEL_20LU | \
1314 IFS_CTL_CRS_SEL_20UL | IFS_CTL_CRS_SEL_20UU)
1315 #define IFS_CTL_ED_SEL_20LL (1 << 8)
1316 #define IFS_CTL_ED_SEL_20LU (1 << 9)
1317 #define IFS_CTL_ED_SEL_20UL (1 << 10)
1318 #define IFS_CTL_ED_SEL_20UU (1 << 11)
1319 #define IFS_CTL_ED_SEL_MASK (IFS_CTL_ED_SEL_20LL | IFS_CTL_ED_SEL_20LU | \
1320 IFS_CTL_ED_SEL_20UL | IFS_CTL_ED_SEL_20UU)
1321
1322 /* ABI_MimoAntSel */
1323 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
1324 #define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
1325 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
1326 #define ABI_MAS_FBR_ANT_PTN_SHIFT 4
1327 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
1328 #ifdef WLAWDL
1329 #define ABI_MAS_AWDL_TS_INSERT 0x1000 /* bit 12 */
1330 #endif
1331 #define ABI_MAS_TIMBC_TSF 0x2000 /* Enable TIMBC tsf field present */
1332
1333 /* MinMBytes */
1334 #define MINMBYTES_PKT_LEN_MASK 0x0300
1335 #define MINMBYTES_FBRATE_PWROFFSET_MASK 0xFC00
1336 #define MINMBYTES_FBRATE_PWROFFSET_SHIFT 10
1337
1338 /* Rev40 template constants */
1339
1340 /* templates include a longer PLCP header that matches the MAC / PHY interface */
1341 #define D11_VHT_PLCP_LEN 12
1342
1343 /* 11AC TX DMA buffer header */
1344
1345 #define D11AC_TXH_NUM_RATES 4
1346 #define D11AC_MFBR_NUM 4
1347 #define D11AC_SFBR_NUM 2
1348 /* per rate info */
1349 typedef struct d11actxh_rate d11actxh_rate_t;
1350 BWL_PRE_PACKED_STRUCT struct d11actxh_rate {
1351 uint16 PhyTxControlWord_0; /* 0 - 1 */
1352 uint16 PhyTxControlWord_1; /* 2 - 3 */
1353 uint16 PhyTxControlWord_2; /* 4 - 5 */
1354 uint8 plcp[D11_PHY_HDR_LEN]; /* 6 - 11 */
1355 uint16 FbwInfo; /* 12 -13 */
1356 uint16 TxRate; /* 14 */
1357 uint16 RtsCtsControl; /* 16 */
1358 uint16 Bfm0; /* 18 */
1359 } BWL_POST_PACKED_STRUCT;
1360
1361 /* Bit definition for FbwInfo field */
1362 #define FBW_BW_MASK 3
1363 #define FBW_BW_SHIFT 0
1364 #define FBW_BW_INVALID (BW_20MHZ + 3)
1365 #define FBW_TXBF 4
1366 #define FBW_TXBF_SHIFT 2
1367 #define FBW_BFM0_TXPWR_MASK 0x1F8
1368 #define FBW_BFM0_TXPWR_SHIFT 3
1369 #define FBW_BFM_TXPWR_MASK 0x7E00
1370 #define FBW_BFM_TXPWR_SHIFT 9
1371
1372 /* Bit definition for Bfm0 field */
1373 #define BFM0_TXPWR_MASK 0x3f
1374 #define BFM0_STBC 0x40
1375 #define BFM0_STBC_SHIFT 6
1376
1377 /* per packet info */
1378 typedef struct d11actxh_pkt d11actxh_pkt_t;
1379 BWL_PRE_PACKED_STRUCT struct d11actxh_pkt {
1380 /* Per pkt info */
1381 uint16 TSOInfo; /* 0 */
1382 uint16 MacTxControlLow; /* 2 */
1383 uint16 MacTxControlHigh; /* 4 */
1384 uint16 Chanspec; /* 6 */
1385 uint8 IVOffset; /* 8 */
1386 uint8 PktCacheLen; /* 9 */
1387 uint16 FrameLen; /* 10 */
1388 uint16 TxFrameID; /* 12 */
1389 uint16 Seq; /* 14 */
1390 uint16 Tstamp; /* 16 */
1391 uint16 TxStatus; /* 18 */
1392 } BWL_POST_PACKED_STRUCT;
1393
1394 /* Per cache info */
1395 typedef struct d11actxh_cache d11actxh_cache_t;
1396 BWL_PRE_PACKED_STRUCT struct d11actxh_cache {
1397 uint8 BssIdEncAlg; /* 0 */
1398 uint8 KeyIdx; /* 1 */
1399 uint8 PrimeMpduMax; /* 2 */
1400 uint8 FallbackMpduMax; /* 3 */
1401 uint16 AmpduDur; /* 4 - 5 */
1402 uint8 BAWin; /* 6 */
1403 uint8 Pad; /* 7 */
1404 uint8 TkipPH1Key[10]; /* 8 - 17 */
1405 uint8 TSCPN[6]; /* 18 - 23 */
1406 } BWL_POST_PACKED_STRUCT;
1407
1408 /* Long format tx descriptor */
1409 typedef struct d11actxh d11actxh_t;
1410 BWL_PRE_PACKED_STRUCT struct d11actxh {
1411 /* Per pkt info */
1412 d11actxh_pkt_t PktInfo; /* 0 - 19 */
1413
1414 /* Per rate info */
1415 d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 20 - 99 */
1416
1417 /* Per cache info */
1418 d11actxh_cache_t CacheInfo; /* 100 - 123 */
1419
1420 } BWL_POST_PACKED_STRUCT;
1421
1422 #define D11AC_TXH_LEN sizeof(d11actxh_t) /* 124 bytes */
1423
1424 /* Short format tx descriptor only has per packet info */
1425 #define D11AC_TXH_SHORT_LEN sizeof(d11actxh_pkt_t) /* 20 bytes */
1426
1427 /* MacTxControlLow */
1428 #define D11AC_TXC_HDR_FMT_SHORT 0x0001 /* 0: long format, 1: short format */
1429 #define D11AC_TXC_UPD_CACHE 0x0002
1430 #define D11AC_TXC_CACHE_IDX_MASK 0x003C /* Cache index 0 .. 15 */
1431 #define D11AC_TXC_CACHE_IDX_SHIFT 2
1432 #define D11AC_TXC_AMPDU 0x0040 /* Is aggregate-able */
1433 #define D11AC_TXC_IACK 0x0080 /* Expect immediate ACK */
1434 #define D11AC_TXC_LFRM 0x0100 /* Use long/short retry frame count/limit */
1435 #define D11AC_TXC_IPMQ 0x0200 /* Ignore PMQ */
1436 #define D11AC_TXC_MBURST 0x0400 /* Burst mode */
1437 #define D11AC_TXC_ASEQ 0x0800 /* Add ucode generated seq num */
1438 #define D11AC_TXC_AGING 0x1000 /* Use lifetime */
1439 #define D11AC_TXC_AMIC 0x2000 /* Compute and add TKIP MIC */
1440 #define D11AC_TXC_STMSDU 0x4000 /* Fist MSDU */
1441 #define D11AC_TXC_URIFS 0x8000 /* Use RIFS */
1442
1443 /* MacTxControlHigh */
1444 #define D11AC_TXC_DISFCS 0x0001 /* Discard FCS */
1445 #define D11AC_TXC_FIX_RATE 0x0002 /* Use primary rate only */
1446 #define D11AC_TXC_SVHT 0x0004 /* Single VHT mpdu ampdu */
1447 #define D11AC_TXC_PPS 0x0008 /* Enable PS Pretend feature */
1448 #define D11AC_TXC_UCODE_SEQ 0x0010 /* Sequence counter for BK traffic, for offloads */
1449 #define D11AC_TXC_TIMBC_TSF 0x0020 /* Enable TIMBC tsf field present */
1450
1451 /* PhyTxControlWord_0 */
1452 #define D11AC_PHY_TXC_FT_MASK 0x0003
1453 #define D11AC_PHY_TXC_FT_CCK 0x0000
1454 #define D11AC_PHY_TXC_FT_OFDM 0x0001
1455 #define D11AC_PHY_TXC_FT_11N 0x0002
1456 #define D11AC_PHY_TXC_FT_11AC 0x0003
1457 /* vht txctl0 */
1458 #define D11AC_PHY_TXC_NON_SOUNDING 0x0004
1459 #define D11AC_PHY_TXC_BFM 0x0008
1460 #define D11AC_PHY_TXC_SHORT_PREAMBLE 0x0010
1461 #define D11AC_PHY_TXC_NON_LAST_PSDU 0x0020
1462 #define D11AC_PHY_TXC_ANT_MASK 0x3FC0
1463 #define D11AC_PHY_TXC_CORE_MASK 0x03C0
1464 #define D11AC_PHY_TXC_CORE_SHIFT 6
1465 #define D11AC_PHY_TXC_ANT_IDX_MASK 0x3C00
1466 #define D11AC_PHY_TXC_ANT_IDX_SHIFT 10
1467 #define D11AC_PHY_TXC_BW_MASK 0xC000
1468 #define D11AC_PHY_TXC_BW_SHIFT 14
1469 #define D11AC_PHY_TXC_BW_20MHZ 0x0000
1470 #define D11AC_PHY_TXC_BW_40MHZ 0x4000
1471 #define D11AC_PHY_TXC_BW_80MHZ 0x8000
1472 #define D11AC_PHY_TXC_BW_160MHZ 0xC000
1473
1474 /* PhyTxControlWord_1 */
1475 #define D11AC_PHY_TXC_PRIM_SUBBAND_MASK 0x0007
1476 #define D11AC_PHY_TXC_PRIM_SUBBAND_LLL 0x0000
1477 #define D11AC_PHY_TXC_PRIM_SUBBAND_LLU 0x0001
1478 #define D11AC_PHY_TXC_PRIM_SUBBAND_LUL 0x0002
1479 #define D11AC_PHY_TXC_PRIM_SUBBAND_LUU 0x0003
1480 #define D11AC_PHY_TXC_PRIM_SUBBAND_ULL 0x0004
1481 #define D11AC_PHY_TXC_PRIM_SUBBAND_ULU 0x0005
1482 #define D11AC_PHY_TXC_PRIM_SUBBAND_UUL 0x0006
1483 #define D11AC_PHY_TXC_PRIM_SUBBAND_UUU 0x0007
1484 #define D11AC_PHY_TXC_TXPWR_OFFSET_MASK 0x01F8
1485 #define D11AC_PHY_TXC_TXPWR_OFFSET_SHIFT 3
1486 #define D11AC_PHY_TXC_TXBF_USER_IDX_MASK 0x7C00
1487 #define D11AC_PHY_TXC_TXBF_USER_IDX_SHIFT 10
1488
1489 /* PhyTxControlWord_2 phy rate */
1490 #define D11AC_PHY_TXC_PHY_RATE_MASK 0x003F
1491
1492 /* 11b phy rate */
1493 #define D11AC_PHY_TXC_11B_PHY_RATE_MASK 0x0003
1494 #define D11AC_PHY_TXC_11B_PHY_RATE_1 0x0000
1495 #define D11AC_PHY_TXC_11B_PHY_RATE_2 0x0001
1496 #define D11AC_PHY_TXC_11B_PHY_RATE_5_5 0x0002
1497 #define D11AC_PHY_TXC_11B_PHY_RATE_11 0x0003
1498
1499 /* 11a/g phy rate */
1500 #define D11AC_PHY_TXC_11AG_PHY_RATE_MASK 0x0007
1501 #define D11AC_PHY_TXC_11AG_PHY_RATE_6 0x0000
1502 #define D11AC_PHY_TXC_11AG_PHY_RATE_9 0x0001
1503 #define D11AC_PHY_TXC_11AG_PHY_RATE_12 0x0002
1504 #define D11AC_PHY_TXC_11AG_PHY_RATE_18 0x0003
1505 #define D11AC_PHY_TXC_11AG_PHY_RATE_24 0x0004
1506 #define D11AC_PHY_TXC_11AG_PHY_RATE_36 0x0005
1507 #define D11AC_PHY_TXC_11AG_PHY_RATE_48 0x0006
1508 #define D11AC_PHY_TXC_11AG_PHY_RATE_54 0x0007
1509
1510 /* 11ac phy rate */
1511 #define D11AC_PHY_TXC_11AC_MCS_MASK 0x000F
1512 #define D11AC_PHY_TXC_11AC_NSS_MASK 0x0030
1513 #define D11AC_PHY_TXC_11AC_NSS_SHIFT 4
1514
1515 /* 11n phy rate */
1516 #define D11AC_PHY_TXC_11N_MCS_MASK 0x003F
1517
1518 /* PhyTxControlWord_2 rest */
1519 #define D11AC_PHY_TXC_STBC 0x0040
1520 #define D11AC_PHY_TXC_DYN_BW_IN_NON_HT_PRESENT 0x0080
1521 #define D11AC_PHY_TXC_DYN_BW_IN_NON_HT_DYNAMIC 0x0100
1522
1523 /* RtsCtsControl */
1524 #define D11AC_RTSCTS_FRM_TYPE_MASK 0x0001 /* frame type */
1525 #define D11AC_RTSCTS_FRM_TYPE_11B 0x0000 /* 11b */
1526 #define D11AC_RTSCTS_FRM_TYPE_11AG 0x0001 /* 11a/g */
1527 #define D11AC_RTSCTS_USE_RTS 0x0004 /* Use RTS */
1528 #define D11AC_RTSCTS_USE_CTS 0x0008 /* Use CTS */
1529 #define D11AC_RTSCTS_SHORT_PREAMBLE 0x0010 /* Long/short preamble: 0 - long, 1 - short? */
1530 #define D11AC_RTSCTS_LAST_RATE 0x0020 /* this is last rate */
1531 #define D11AC_RTSCTS_IMBF 0x0040 /* Implicit TxBF */
1532 #define D11AC_RTSCTS_BF_IDX_MASK 0x7000 /* 3-bit index to the beamforming block */
1533 #define D11AC_RTSCTS_BF_IDX_SHIFT 12
1534
1535 /* BssIdEncAlg */
1536 #define D11AC_BSSID_MASK 0x000F /* BSS index */
1537 #define D11AC_BSSID_SHIFT 0
1538 #define D11AC_ENCRYPT_ALG_MASK 0x00F0 /* Encryption algoritm */
1539 #define D11AC_ENCRYPT_ALG_SHIFT 4
1540 #define D11AC_ENCRYPT_ALG_NOSEC 0x0000 /* No security */
1541 #define D11AC_ENCRYPT_ALG_WEP 0x0010 /* WEP */
1542 #define D11AC_ENCRYPT_ALG_TKIP 0x0020 /* TKIP */
1543 #define D11AC_ENCRYPT_ALG_AES 0x0030 /* AES */
1544 #define D11AC_ENCRYPT_ALG_WEP128 0x0040 /* WEP128 */
1545 #define D11AC_ENCRYPT_ALG_NA 0x0050 /* N/A */
1546 #define D11AC_ENCRYPT_ALG_WAPI 0x0060 /* WAPI */
1547
1548 /* AmpduDur */
1549 #define D11AC_AMPDU_MIN_DUR_IDX_MASK 0x000F /* AMPDU minimum duration index */
1550 #define D11AC_AMPDU_MIN_DUR_IDX_SHIFT 0
1551 #define D11AC_AMPDU_MAX_DUR_MASK 0xFFF0 /* AMPDU maximum duration in unit 16 usec */
1552 #define D11AC_AMPDU_MAX_DUR_SHIFT 4
1553
1554
1555 /* Generic tx status packet for software use. This is independent of hardware
1556 * structure for a particular core. Hardware structure should be read and converted
1557 * to this structure before being sent for the sofware consumption.
1558 */
1559 typedef struct tx_status tx_status_t;
1560 typedef struct tx_status_fields tx_status_macinfo_t;
1561
1562 BWL_PRE_PACKED_STRUCT struct tx_status_fields {
1563 int8 pad0;
1564 int8 is_intermediate;
1565 int8 pm_indicated;
1566 int8 pad1;
1567 uint8 suppr_ind;
1568 int8 was_acked;
1569
1570 uint16 rts_tx_cnt;
1571 uint16 frag_tx_cnt;
1572 uint16 cts_rx_cnt;
1573
1574 uint16 raw_bits;
1575
1576 uint32 s3;
1577 uint32 s4;
1578 uint32 s5;
1579 uint32 ack_map1;
1580 uint32 ack_map2;
1581 uint32 s8;
1582 } BWL_POST_PACKED_STRUCT;
1583
1584 /* tx status packet for core rev 4 */
1585 typedef struct tx_status_cr4 tx_status_cr4_t;
1586 BWL_PRE_PACKED_STRUCT struct tx_status_cr4 {
1587 uint16 framelen;
1588 uint16 PAD;
1589 uint16 frameid;
1590 uint16 status;
1591 uint16 lasttxtime;
1592 uint16 sequence;
1593 uint16 phyerr;
1594 uint16 ackphyrxsh;
1595 } BWL_POST_PACKED_STRUCT;
1596
1597
1598 BWL_PRE_PACKED_STRUCT struct tx_status {
1599 uint16 framelen;
1600 uint16 frameid;
1601 tx_status_macinfo_t status;
1602 uint16 sequence;
1603 uint32 lasttxtime;
1604 uint16 phyerr;
1605 uint16 ackphyrxsh;
1606 } BWL_POST_PACKED_STRUCT;
1607
1608 /* status field bit definitions */
1609 #define TX_STATUS_FRM_RTX_MASK 0xF000
1610 #define TX_STATUS_FRM_RTX_SHIFT 12
1611 #define TX_STATUS_RTS_RTX_MASK 0x0F00
1612 #define TX_STATUS_RTS_RTX_SHIFT 8
1613 #define TX_STATUS_MASK 0x00FE
1614 #define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
1615 #define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
1616 #define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
1617 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
1618 #define TX_STATUS_SUPR_SHIFT 2
1619 #define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
1620 #define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */
1621 #define TX_STATUS_NO_ACK 0
1622 #define TX_STATUS_BE (TX_STATUS_ACK_RCV | TX_STATUS_PMINDCTD)
1623
1624 /* status field bit definitions phy rev > 40 */
1625 #define TX_STATUS40_FIRST 0x0002
1626 #define TX_STATUS40_INTERMEDIATE 0x0004
1627 #define TX_STATUS40_PMINDCTD 0x0008
1628
1629 #define TX_STATUS40_SUPR 0x00f0
1630 #define TX_STATUS40_SUPR_SHIFT 4
1631
1632 #define TX_STATUS40_NCONS 0x7f00
1633
1634 #define TX_STATUS40_NCONS_SHIFT 8
1635
1636 #define TX_STATUS40_ACK_RCV 0x8000
1637
1638 /* tx status bytes 8-16 */
1639 #define TX_STATUS40_TXCNT_RATE0_MASK 0x000000ff
1640 #define TX_STATUS40_TXCNT_RATE0_SHIFT 0
1641
1642 #define TX_STATUS40_TXCNT_RATE1_MASK 0x00ff0000
1643 #define TX_STATUS40_TXCNT_RATE1_SHIFT 16
1644
1645 #define TX_STATUS40_MEDIUM_DELAY_MASK 0xFFFF
1646
1647 #define TX_STATUS40_TXCNT(s3, s4) \
1648 (((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) + \
1649 ((s3 & TX_STATUS40_TXCNT_RATE1_MASK) >> TX_STATUS40_TXCNT_RATE1_SHIFT) + \
1650 ((s4 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) + \
1651 ((s4 & TX_STATUS40_TXCNT_RATE1_MASK) >> TX_STATUS40_TXCNT_RATE1_SHIFT))
1652
1653 #define TX_STATUS40_TX_MEDIUM_DELAY(txs) ((txs)->status.s8 & TX_STATUS40_MEDIUM_DELAY_MASK)
1654
1655 /* chip rev 40 pkg 2 fields */
1656 #define TX_STATUS40_IMPBF_MASK 0x0000000C /* implicit bf applied */
1657 #define TX_STATUS40_IMPBF_BAD_MASK 0x00000010 /* impl bf applied but acked frame has no bfm */
1658 #define TX_STATUS40_IMPBF_LOW_MASK 0x00000020 /* ack received with low rssi */
1659
1660 #define TX_STATUS40_RTS_RTX_MASK 0x00ff0000
1661 #define TX_STATUS40_RTS_RTX_SHIFT 16
1662 #define TX_STATUS40_CTS_RRX_MASK 0xff000000
1663 #define TX_STATUS40_CTS_RRX_SHIFT 24
1664
1665 /* suppress status reason codes */
1666 enum {
1667 TX_STATUS_SUPR_PMQ = 1, /* PMQ entry */
1668 TX_STATUS_SUPR_FLUSH = 2, /* flush request */
1669 TX_STATUS_SUPR_FRAG = 3, /* previous frag failure */
1670 TX_STATUS_SUPR_TBTT = 3, /* SHARED: Probe response supr for TBTT */
1671 TX_STATUS_SUPR_BADCH = 4, /* channel mismatch */
1672 TX_STATUS_SUPR_EXPTIME = 5, /* lifetime expiry */
1673 TX_STATUS_SUPR_UF = 6, /* underflow */
1674 #ifdef WLP2P_UCODE
1675 TX_STATUS_SUPR_NACK_ABS = 7, /* BSS entered ABSENCE period */
1676 #endif
1677 TX_STATUS_SUPR_PPS = 8, /* Pretend PS */
1678 TX_STATUS_SUPR_PHASE1_KEY = 9, /* Request new TKIP phase-1 key */
1679 NUM_TX_STATUS_SUPR
1680 };
1681
1682 /* Unexpected tx status for rate update */
1683 #define TX_STATUS_UNEXP(status) \
1684 ((((status.is_intermediate))) && \
1685 TX_STATUS_UNEXP_AMPDU(status))
1686
1687 /* Unexpected tx status for A-MPDU rate update */
1688 #ifdef WLP2P_UCODE
1689 #define TX_STATUS_UNEXP_AMPDU(status) \
1690 ((((status.suppr_ind)) != 0) && \
1691 (((status.suppr_ind)) != TX_STATUS_SUPR_EXPTIME) && \
1692 (((status.suppr_ind)) != TX_STATUS_SUPR_NACK_ABS))
1693 #else
1694 #define TX_STATUS_UNEXP_AMPDU(status) \
1695 ((((status.suppr_ind)) != 0) && \
1696 (((status.suppr_ind)) != TX_STATUS_SUPR_EXPTIME))
1697 #endif
1698
1699 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
1700 #define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
1701 #define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
1702 #define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
1703
1704
1705 /* RXE (Receive Engine) */
1706
1707 /* RCM_CTL */
1708 #define RCM_INC_MASK_H 0x0080
1709 #define RCM_INC_MASK_L 0x0040
1710 #define RCM_INC_DATA 0x0020
1711 #define RCM_INDEX_MASK 0x001F
1712 #define RCM_SIZE 15
1713
1714 #define RCM_MAC_OFFSET 0 /* current MAC address */
1715 #define RCM_BSSID_OFFSET 3 /* current BSSID address */
1716 #define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
1717 #define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
1718 #define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
1719
1720 #define RCM_WEP_TA0_OFFSET 16
1721 #define RCM_WEP_TA1_OFFSET 19
1722 #define RCM_WEP_TA2_OFFSET 22
1723 #define RCM_WEP_TA3_OFFSET 25
1724
1725 /* AMT - Address Match Table */
1726
1727 /* AMT Attribute bits */
1728 #define AMT_ATTR_VALID 0x8000 /* Mark the table entry valid */
1729 #define AMT_ATTR_A1 0x0008 /* Match for A1 */
1730 #define AMT_ATTR_A2 0x0004 /* Match for A2 */
1731 #define AMT_ATTR_A3 0x0002 /* Match for A3 */
1732
1733 /* AMT Index defines */
1734 #define AMT_SIZE 64 /* number of AMT entiries */
1735 #define AMT_IDX_MAC 63 /* device MAC */
1736 #define AMT_IDX_BSSID 62 /* BSSID match */
1737 #define AMT_IDX_MCAST_ADDR 61 /* MCAST address for Reliable Mcast feature */
1738 #define AMT_MAXIDX_P2P_USE 60 /* Max P2P entry to use */
1739
1740 #define AMT_MAX_TXBF_ENTRIES 7 /* Max tx beamforming entry */
1741 /* PSTA AWARE AP: Max PSTA Tx beamforming entry */
1742 #define AMT_MAX_TXBF_PSTA_ENTRIES 20
1743
1744 /* PSM Block */
1745
1746 /* psm_phy_hdr_param bits */
1747 #define MAC_PHY_RESET 1
1748 #define MAC_PHY_CLOCK_EN 2
1749 #define MAC_PHY_FORCE_CLK 4
1750
1751 /* PSMCoreControlStatus (IHR Address 0x078) bit definitions */
1752 #define PSM_CORE_CTL_AR (1 << 0)
1753 #define PSM_CORE_CTL_HR (1 << 1)
1754 #define PSM_CORE_CTL_IR (1 << 2)
1755 #define PSM_CORE_CTL_AAR (1 << 3)
1756 #define PSM_CORE_CTL_HAR (1 << 4)
1757 #define PSM_CORE_CTL_PPAR (1 << 5)
1758 #define PSM_CORE_CTL_SS (1 << 6)
1759 #define PSM_CORE_CTL_REHE (1 << 7)
1760 #define PSM_CORE_CTL_PPAS (1 << 13)
1761 #define PSM_CORE_CTL_AAS (1 << 14)
1762 #define PSM_CORE_CTL_HAS (1 << 15)
1763
1764 #define PSM_CORE_CTL_LTR_BIT 9
1765 #define PSM_CORE_CTL_LTR_MASK 0x3
1766
1767 /* WEP Block */
1768
1769 /* WEP_WKEY */
1770 #define WKEY_START (1 << 8)
1771 #define WKEY_SEL_MASK 0x1F
1772
1773 /* WEP data formats */
1774
1775 /* the number of RCMTA entries */
1776 #define RCMTA_SIZE 50
1777
1778 /* max keys in M_TKMICKEYS_BLK */
1779 #define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
1780
1781 /* max keys in M_WAPIMICKEYS_BLK */
1782 #define WSEC_MAX_SMS4MIC_ENGINE_REAL_KEYS 12 /* (4 * 2) + 4 default */
1783 #define WSEC_MAX_SMS4MIC_ENGINE_KEYS 8 /* (4 * 2) + 4 default */
1784
1785 /* max RXE match registers */
1786 #define WSEC_MAX_RXE_KEYS 4
1787
1788 /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
1789 /* SKL (Security Key Lookup) */
1790 #define SKL_ALGO_MASK 0x0007
1791 #define SKL_ALGO_SHIFT 0
1792 #define SKL_KEYID_MASK 0x0008
1793 #define SKL_KEYID_SHIFT 3
1794 #define SKL_INDEX_MASK 0x03F0
1795 #define SKL_INDEX_SHIFT 4
1796 #define SKL_GRP_ALGO_MASK 0x1c00
1797 #define SKL_GRP_ALGO_SHIFT 10
1798 #define SKL_STAMON_NBIT (1 << 15) /* STA monitor bit */
1799
1800 /* additional bits defined for IBSS group key support */
1801 #define SKL_IBSS_INDEX_MASK 0x01F0
1802 #define SKL_IBSS_INDEX_SHIFT 4
1803 #define SKL_IBSS_KEYID1_MASK 0x0600
1804 #define SKL_IBSS_KEYID1_SHIFT 9
1805 #define SKL_IBSS_KEYID2_MASK 0x1800
1806 #define SKL_IBSS_KEYID2_SHIFT 11
1807 #define SKL_IBSS_KEYALGO_MASK 0xE000
1808 #define SKL_IBSS_KEYALGO_SHIFT 13
1809
1810 #define WSEC_MODE_OFF 0
1811 #define WSEC_MODE_HW 1
1812 #define WSEC_MODE_SW 2
1813
1814 #define WSEC_ALGO_OFF 0
1815 #define WSEC_ALGO_WEP1 1
1816 #define WSEC_ALGO_TKIP 2
1817 #define WSEC_ALGO_WEP128 3
1818 #define WSEC_ALGO_AES_LEGACY 4
1819 #define WSEC_ALGO_AES 5
1820 #define WSEC_ALGO_SMS4 6
1821 #define WSEC_ALGO_SMS4_DFT_2005_09_07 7
1822 #define WSEC_ALGO_NALG 8
1823
1824 #define D11_PRE40_WSEC_ALGO_AES 3
1825 #define D11_PRE40_WSEC_ALGO_WEP128 4
1826 #define D11_PRE40_WSEC_ALGO_AES_LEGACY 5
1827 #define D11_PRE40_WSEC_ALGO_SMS4 6
1828 #define D11_PRE40_WSEC_ALGO_NALG 7
1829
1830
1831 #define AES_MODE_NONE 0
1832 #define AES_MODE_CCM 1
1833 #define AES_MODE_OCB_MSDU 2
1834 #define AES_MODE_OCB_MPDU 3
1835
1836 /* WEP_CTL (Rev 0) */
1837 #define WECR0_KEYREG_SHIFT 0
1838 #define WECR0_KEYREG_MASK 0x7
1839 #define WECR0_DECRYPT (1 << 3)
1840 #define WECR0_IVINLINE (1 << 4)
1841 #define WECR0_WEPALG_SHIFT 5
1842 #define WECR0_WEPALG_MASK (0x7 << 5)
1843 #define WECR0_WKEYSEL_SHIFT 8
1844 #define WECR0_WKEYSEL_MASK (0x7 << 8)
1845 #define WECR0_WKEYSTART (1 << 11)
1846 #define WECR0_WEPINIT (1 << 14)
1847 #define WECR0_ICVERR (1 << 15)
1848
1849 /* Frame template map byte offsets */
1850 #define T_ACTS_TPL_BASE (0)
1851 #define T_NULL_TPL_BASE (0xc * 2)
1852 #define T_QNULL_TPL_BASE (0x1c * 2)
1853 #define T_RR_TPL_BASE (0x2c * 2)
1854 #define T_BCN0_TPL_BASE (0x34 * 2)
1855 #define T_PRS_TPL_BASE (0x134 * 2)
1856 #define T_BCN1_TPL_BASE (0x234 * 2)
1857
1858
1859
1860 #define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1861
1862 #define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1863
1864 #define TPLBLKS_PER_BCN_NUM 2
1865 #define TPLBLKS_AC_PER_BCN_NUM 1
1866
1867 #if defined(WLLPRS) && defined(MBSS)
1868 #define TPLBLKS_PER_PRS_NUM 4
1869 #define TPLBLKS_AC_PER_PRS_NUM 2
1870 #else
1871 #define TPLBLKS_PER_PRS_NUM 2
1872 #define TPLBLKS_AC_PER_PRS_NUM 1
1873 #endif /* WLLPRS && MBSS */
1874
1875 #define TPLBLKS_PER_BCN (wlc->tplblks_per_bcn)
1876 #define TPLBLKS_PER_PRS (wlc->tplblks_per_prs)
1877
1878 /* calculate the number of template mem blks needed for beacons
1879 * and probe responses of all the BSSs. add one additional block
1880 * to account for 104 bytes of space reserved (?) at the start of
1881 * template memory.
1882 */
1883 #define MBSS_TPLBLKS(n) (1 + ((n) * (TPLBLKS_PER_BCN + TPLBLKS_PER_PRS)))
1884 #define MBSS_TXFIFO_START_BLK(n) MBSS_TPLBLKS(n)
1885 #define MBSS_PRS_BLKS_START(n) (wlc->shm_bcn0_tpl_base + \
1886 ((n) * (D11REV_GE(wlc->pub->corerev, 40) ? \
1887 wlc->pub->bcn_tmpl_len : (TPLBLKS_PER_BCN * TXFIFO_SIZE_UNIT))))
1888
1889 /* Shared Mem byte offsets */
1890
1891 /* Location where the ucode expects the corerev */
1892 #define M_MACHW_VER (0x00b * 2)
1893
1894 /* Location where the ucode expects the MAC capabilities */
1895 #define M_MACHW_CAP_L (0x060 * 2)
1896 #define M_MACHW_CAP_H (0x061 * 2)
1897
1898 /* WME shared memory */
1899 #define M_EDCF_STATUS_OFF (0x007 * 2)
1900 #define M_TXF_CUR_INDEX (0x018 * 2)
1901 #define M_EDCF_QINFO (0x120 * 2)
1902
1903 /* PS-mode related parameters */
1904 #define M_DOT11_SLOT (0x008 * 2)
1905 #define M_DOT11_DTIMPERIOD (0x009 * 2)
1906 #define M_NOSLPZNATDTIM (0x026 * 2)
1907
1908 /* Beacon-related parameters */
1909 #define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1910 #define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1911 #define M_BCN_TXTSF_OFFSET (0x00e * 2)
1912 #define M_TIMBPOS_INBEACON (0x00f * 2)
1913 #define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1914 #define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1915 #define M_BCN_PCTLWD (0x02a * 2)
1916 #define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1917
1918 /* extended beacon phyctl bytes for 11N */
1919 #define M_BCN_PCTL1WD (0x058 * 2)
1920
1921 /* MAX Rx Frame len */
1922 #define M_MAXRXFRM_LEN (0x010 * 2)
1923
1924 /* rxfifo mpdu high watermark */
1925 #define M_RXOV_HIWAT (0x3f8 * 2)
1926
1927 /* ACK/CTS related params */
1928 #define M_RSP_PCTLWD (0x011 * 2)
1929
1930 #define D11AC_RSP_TXPCTL0 (0x4c * 2)
1931 #define D11AC_RSP_TXPCTL1 (0x4d * 2)
1932 #define D11AC_RSP_TXPCTL2 (0x4e * 2)
1933
1934 #define M_STA_MONITOR_N (0x012 * 2)
1935
1936 /* Hardware Power Control */
1937 #define M_TXPWR_N (0x012 * 2)
1938 #define M_TXPWR_TARGET (0x013 * 2)
1939 #define M_TXPWR_MAX (0x014 * 2)
1940 #define M_TXPWR_CUR (0x019 * 2)
1941
1942 /* Rx-related parameters */
1943 #define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1944
1945 /* WEP Shared mem data */
1946 #define M_SEC_DEFIVLOC (0x01e * 2)
1947 #define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1948 #define M_PHYVER (0x028 * 2)
1949 #define M_PHYTYPE (0x029 * 2)
1950 #define M_SECRXKEYS_PTR (0x02b * 2)
1951 #define M_TKMICKEYS_PTR (0x059 * 2)
1952 #define M_WAPIMICKEYS_PTR (0x051 * 2)
1953
1954 #define D11_PRE40_M_SECKINDXALGO_BLK_SZ 54
1955 #define D11_PRE40_M_SECKINDXALGO_BLK (0x2ea * 2)
1956
1957 #define M_SECKINDXALGO_BLK_SZ 68 /* AMT_SIZE + default Keys */
1958 #define M_SECKINDXALGO_BLK (0x2f0 * 2)
1959
1960 #define D11AC_M_SECKINDXALGO_BLK (0x1b6 * 2)
1961 #define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1962 #define M_TKIP_TSC_TTAK (0x18c * 2)
1963 #define D11_MAX_KEY_SIZE 16
1964
1965 #define M_AMT_INFO_BLK (0x334 * 2)
1966
1967 #define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1968
1969 /* Probe response related parameters */
1970 #define M_SSIDLEN (0x024 * 2)
1971 #define M_PRB_RESP_FRM_LEN (0x025 * 2)
1972 #define M_PRS_MAXTIME (0x03a * 2)
1973 #define M_SSID (0xb0 * 2)
1974 #define M_CTXPRS_BLK (0xc0 * 2) /* obselete in corerev >= 40 */
1975 #define C_CTX_PCTLWD_POS (0x4 * 2)
1976
1977
1978 /* Delta between OFDM and CCK power in CCK power boost mode */
1979 #define M_OFDM_OFFSET (0x027 * 2)
1980
1981 /* TSSI for last 4 11b/g CCK packets transmitted */
1982 #define M_B_TSSI_0 (0x02c * 2)
1983 #define M_B_TSSI_1 (0x02d * 2)
1984
1985 /* Host flags to turn on ucode options */
1986 #define M_HOST_FLAGS1 (0x02f * 2)
1987 #define M_HOST_FLAGS2 (0x030 * 2)
1988 #define M_HOST_FLAGS3 (0x031 * 2)
1989 #define M_HOST_FLAGS4 (0x03c * 2)
1990 #define M_HOST_FLAGS5 (0x06a * 2)
1991 #define M_HOST_FLAGS_SZ 16
1992
1993 #define M_RADAR_REG (0x033 * 2)
1994
1995 /* TSSI for last 4 11a OFDM packets transmitted */
1996 #define M_A_TSSI_0 (0x034 * 2)
1997 #define M_A_TSSI_1 (0x035 * 2)
1998
1999 /* noise interference measurement */
2000 #define M_NOISE_IF_COUNT (0x034 * 2)
2001 #define M_NOISE_IF_TIMEOUT (0x035 * 2)
2002
2003
2004 #define M_RF_RX_SP_REG1 (0x036 * 2)
2005
2006 /* TSSI for last 4 11g OFDM packets transmitted */
2007 #define M_G_TSSI_0 (0x038 * 2)
2008 #define M_G_TSSI_1 (0x039 * 2)
2009
2010 /* Background noise measure */
2011 #define M_JSSI_0 (0x44 * 2)
2012 #define M_JSSI_1 (0x45 * 2)
2013 #define M_JSSI_AUX (0x46 * 2)
2014
2015 #define M_CUR_2050_RADIOCODE (0x47 * 2)
2016
2017 /* TX fifo sizes */
2018 #define M_FIFOSIZE0 (0x4c * 2)
2019 #define M_FIFOSIZE1 (0x4d * 2)
2020 #define M_FIFOSIZE2 (0x4e * 2)
2021 #define M_FIFOSIZE3 (0x4f * 2)
2022 #define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
2023
2024 /* Current channel number plus upper bits */
2025 #define M_CURCHANNEL (0x50 * 2)
2026 #define D11_CURCHANNEL_5G 0x0100;
2027 #define D11_CURCHANNEL_40 0x0200;
2028 #define D11_CURCHANNEL_MAX 0x00FF;
2029
2030 /* last posted frameid on the bcmc fifo */
2031 #define M_BCMC_FID (0x54 * 2)
2032 #define INVALIDFID 0xffff
2033
2034
2035 /* idle busy ratio to duty_cycle requirement */
2036 #define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
2037 #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
2038 #define M_DUTY_STRRATE (0x6B * 2)
2039
2040 /* SHM_reg = 2*(wlc_read_shm(M_SSLPNPHYREGS_PTR) + offset) */
2041 #define M_SSLPNPHYREGS_PTR (71 * 2)
2042
2043 /* CW RSSI for SSLPNPHY */
2044 #define M_SSLPN_RSSI_0 0x1332
2045 #define M_SSLPN_RSSI_1 0x1338
2046 #define M_SSLPN_RSSI_2 0x133e
2047 #define M_SSLPN_RSSI_3 0x1344
2048
2049 /* SNR for SSLPNPHY */
2050 #define M_SSLPN_SNR_A_0 0x1334
2051 #define M_SSLPN_SNR_B_0 0x1336
2052
2053 #define M_SSLPN_SNR_A_1 0x133a
2054 #define M_SSLPN_SNR_B_1 0x133c
2055
2056 #define M_SSLPN_SNR_A_2 0x1340
2057 #define M_SSLPN_SNR_B_2 0x1342
2058
2059 #define M_SSLPN_SNR_A_3 0x1346
2060 #define M_SSLPN_SNR_B_3 0x1348
2061
2062 /* hardware assisted noise cal for lcn40phy */
2063 #define M_NOISE_CAL_TIMEOUT_LCN40PHY 19
2064 #define M_NOISE_CAL_CMD_LCN40PHY 20
2065 #define M_NOISE_CAL_RSP_LCN40PHY 21
2066 #define M_NOISE_CAL_DATA_LCN40PHY 23
2067
2068 /* Olympic N9037.4Mhz crystal change */
2069 #define M_SSLPNPHY_REG_55f_REG_VAL 16
2070 #define M_SSLPNPHY_REG_4F2_2_4 17
2071 #define M_SSLPNPHY_REG_4F3_2_4 18
2072 #define M_SSLPNPHY_REG_4F2_16_64 19
2073 #define M_SSLPNPHY_REG_4F3_16_64 20
2074 #define M_SSLPNPHY_REG_4F2_CCK 21
2075 #define M_SSLPNPHY_REG_4F3_CCK 22
2076 #define M_SSLPNPHY_ANTDIV_REG 27
2077
2078 /* Olympic N9037.4Mhz crystal change */
2079 #define M_55f_REG_VAL 16
2080 #define M_SSLPNPHY_REG_4F2_2_4 17
2081 #define M_SSLPNPHY_REG_4F3_2_4 18
2082 #define M_SSLPNPHY_REG_4F2_16_64 19
2083 #define M_SSLPNPHY_REG_4F3_16_64 20
2084 #define M_SSLPNPHY_REG_4F2_CCK 21
2085 #define M_SSLPNPHY_REG_4F3_CCK 22
2086 #define M_SSLPNPHY_ANTDIV_REG 27
2087 #define M_SSLPNPHY_NOISE_SAMPLES 34
2088 #define M_SSLPNPHY_TSSICAL_EN 35
2089 #define M_SSLPNPHY_LNA_TX 36
2090 #define M_SSLPNPHY_TXPWR_BLK 40
2091
2092 /* For noise cal */
2093 #define M_NOISE_CAL_MIN 35
2094 #define M_NOISE_CAL_MAX 36
2095 #define M_NOISE_CAL_METRIC 37
2096 #define M_NOISE_CAL_ACC 38
2097 #define M_NOISE_CAL_CMD 39
2098 #define M_NOISE_CAL_RSP 40
2099
2100 #define M_SSLPN_ACI_TMOUT 0x1308
2101 #define M_SSLPN_ACI_CNT 0x130a
2102
2103 #define M_SSLPN_LAST_RESET (81*2)
2104 #define M_SSLPN_LAST_LOC (63*2)
2105 #define M_SSLPNPHY_RESET_STATUS (4902)
2106 #define M_SSLPNPHY_DSC_TIME (0x98d*2)
2107 #define M_SSLPNPHY_RESET_CNT_DSC (0x98b*2)
2108 #define M_SSLPNPHY_RESET_CNT (0x98c*2)
2109
2110 #define M_LCNPHYREGS_PTR M_SSLPNPHYREGS_PTR
2111 #define M_LCN40PHYREGS_PTR M_SSLPNPHYREGS_PTR
2112 #define M_SWDIV_BLK_PTR M_LCN40PHYREGS_PTR
2113
2114 /* CW RSSI and SNR for LCNPHY */
2115 #define M_LCN_RSSI_0 (4 *2)
2116 #define M_LCN_SNR_A_0 (5 *2)
2117 #define M_LCN_SNR_B_0 (6 *2)
2118
2119 #define M_LCN_RSSI_1 (7 *2)
2120 #define M_LCN_SNR_A_1 (8 *2)
2121 #define M_LCN_SNR_B_1 (9 *2)
2122
2123 #define M_LCN_RSSI_2 (10*2)
2124 #define M_LCN_SNR_A_2 (11*2)
2125 #define M_LCN_SNR_B_2 (12*2)
2126
2127 #define M_LCN_RSSI_3 (13*2)
2128 #define M_LCN_SNR_A_3 (14*2)
2129 #define M_LCN_SNR_B_3 (15*2)
2130
2131 /* hardware assisted noise cal for lcn40phy */
2132 #define M_NOISE_CAL_TIMEOUT_LCN40PHY 19
2133 #define M_NOISE_CAL_CMD_LCN40PHY 20
2134 #define M_NOISE_CAL_RSP_LCN40PHY 21
2135 #define M_NOISE_CAL_DATA_LCN40PHY 23
2136
2137 #define M_SWDIV_EN (38*2)
2138 #define M_SWDIV_PREF_ANT (39*2)
2139 #define M_SWDIV_GPIO_MASK (40*2)
2140
2141 #define M_RSSI_BOARDATTEN (41*2)
2142 #define M_RSSI_NSAMPS (42*2)
2143 #define M_RSSI_LOGNSAMPS (43*2)
2144 #define M_RSSI_IQPWR (44*2)
2145 #define M_RSSI_IQPWR_DB (45*2)
2146 #define M_RSSI_LOCK (46*2)
2147 #define M_RSSI_IQEST_EN (47*2)
2148 #define M_RSSI_BOARDATTEN_DBG (48*2)
2149 #define M_RSSI_IQPWR_DBG (49*2)
2150 #define M_RSSI_IQPWR_DB_DBG (50*2)
2151
2152 #define M_NOISE_IQPWR (54*2)
2153 #define M_NOISE_IQPWR_DB (55*2)
2154 #define M_NOISE_LOGNSAMPS (56*2)
2155 #define M_NOISE_NSAMPS (57*2)
2156 #define M_NOISE_IQEST_EN (58*2)
2157 #define M_NOISE_IQEST_TIMEOUT (59*2)
2158 #define M_NOISE_IQEST_PENDING (60*2)
2159 #define M_RSSI_IQEST_PENDING (61*2)
2160
2161 /* Offsets for qdB portion of RSSI */
2162 #define M_LCN40_RSSI_QDB_0 (63 *2)
2163 #define M_LCN40_RSSI_QDB_1 (64 *2)
2164 #define M_LCN40_RSSI_QDB_2 (65 *2)
2165 #define M_LCN40_RSSI_QDB_3 (66 *2)
2166
2167 #define M_NOISE_LTE_IQPWR_DB (72*2)
2168 #define M_NOISE_LTE_ON (73*2)
2169
2170 /* Rate table offsets */
2171 #define M_RT_DIRMAP_A (0xe0 * 2)
2172 #define M_RT_BBRSMAP_A (0xf0 * 2)
2173 #define M_RT_DIRMAP_B (0x100 * 2)
2174 #define M_RT_BBRSMAP_B (0x110 * 2)
2175 #define D11_RT_DIRMAP_SIZE 16
2176
2177 /* Rate table entry offsets */
2178 #define M_RT_PRS_PLCP_POS 10
2179 #define M_RT_PRS_DUR_POS 16
2180 #define M_RT_OFDM_PCTL1_POS 18
2181 #define M_RT_TXPWROFF_POS 20
2182 #define M_REV40_RT_TXPWROFF_POS 14
2183
2184 #define M_20IN40_IQ (0x380 * 2)
2185
2186 /* SHM locations where ucode stores the current power index */
2187 #define M_CURR_IDX1 (0x384 *2)
2188 #define M_CURR_IDX2 (0x387 *2)
2189
2190 #define M_BSCALE_ANT0 (0x5e * 2)
2191 #define M_BSCALE_ANT1 (0x5f * 2)
2192
2193 /* Antenna Diversity Testing */
2194 #define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
2195 #define M_ANTSEL_CLKDIV (0x61 * 2)
2196 #define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
2197
2198 #define M_MIMO_MAXSYM (0x5d * 2)
2199 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */
2200 #define MIMO_MAXSYM_MAX 0xffff /* 64k */
2201
2202 #define M_WATCHDOG_8TU (0x1e * 2)
2203 #define WATCHDOG_8TU_DEF 5
2204 #define WATCHDOG_8TU_MAX 10
2205
2206 /* Manufacturing Test Variables */
2207 #define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
2208 #define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
2209 #define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
2210 #define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
2211
2212 /* Index variation in vbat ripple */
2213 #define M_SSLPN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
2214 #define M_SSLPN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
2215 #define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
2216 #define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
2217
2218 /* Index variation in vbat ripple */
2219 #define M_SSLPN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
2220 #define M_SSLPN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
2221
2222 /* M_PKTENG_CTRL bit definitions */
2223 #define M_PKTENG_MODE_TX 0x0001
2224 #define M_PKTENG_MODE_TX_RIFS 0x0004
2225 #define M_PKTENG_MODE_TX_CTS 0x0008
2226 #define M_PKTENG_MODE_RX 0x0002
2227 #define M_PKTENG_MODE_RX_WITH_ACK 0x0402
2228 #define M_PKTENG_MODE_MASK 0x0003
2229 #define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
2230
2231 /* Sample Collect parameters (bitmap and type) */
2232 #define M_SMPL_COL_BMP (0x372 * 2) /* Trigger bitmap for sample collect */
2233 #define M_SMPL_COL_CTL (0x373 * 2) /* Sample collect type */
2234
2235 #define D11AC_M_SMPL_COL_BMP (0x3c9 * 2) /* Trigger bitmap for sample collect */
2236 #define D11AC_M_SMPL_COL_CTL (0x3ca * 2) /* Sample collect type */
2237
2238 #define ANTSEL_CLKDIV_4MHZ 6
2239 #define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
2240 #define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
2241 #define MIMO_ANTSEL_WAIT 50 /* 50us wait */
2242 #define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
2243
2244 #define M_AFEOVR_PTR (0x2c*2)
2245 #define M_IFSCTL1 (0x2d*2)
2246
2247 #define M_MYMAC_ADDR_L (0x3c6 *2)
2248 #define M_MYMAC_ADDR_M (0x3c7 *2)
2249 #define M_MYMAC_ADDR_H (0x3c8 *2)
2250
2251
2252 typedef struct shm_acparams shm_acparams_t;
2253 BWL_PRE_PACKED_STRUCT struct shm_acparams {
2254 uint16 txop;
2255 uint16 cwmin;
2256 uint16 cwmax;
2257 uint16 cwcur;
2258 uint16 aifs;
2259 uint16 bslots;
2260 uint16 reggap;
2261 uint16 status;
2262 uint16 txcnt;
2263 uint16 rsvd[7];
2264 } BWL_POST_PACKED_STRUCT;
2265 #define M_EDCF_QLEN (16 * 2)
2266
2267 #define WME_STATUS_NEWAC (1 << 8)
2268
2269 #define M_LCNXN_SWCTRL_MASK (M_PSM_SOFT_REGS + (0x67 * 2))
2270
2271 /* M_HOST_FLAGS */
2272 #define MHFMAX 5 /* Number of valid hostflag half-word (uint16) */
2273 #define MHF1 0 /* Hostflag 1 index */
2274 #define MHF2 1 /* Hostflag 2 index */
2275 #define MHF3 2 /* Hostflag 3 index */
2276 #define MHF4 3 /* Hostflag 4 index */
2277 #define MHF5 4 /* Hostflag 5 index */
2278
2279 /* Flags in M_HOST_FLAGS */
2280 #define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
2281 #define MHF1_WLAN_CRITICAL 0x0002 /* WLAN is in critical state */
2282 #define MHF1_MBSS_EN 0x0004 /* Enable MBSS: RXPUWAR deprecated for rev >= 9 */
2283 #define MHF1_CCKPWR 0x0008 /* Enable 4 Db CCK power boost */
2284 #define MHF1_4331EPA_WAR 0x0008 /* WAR ePA control by the ucode */
2285 #define MHF1_BTCOEXIST 0x0010 /* Enable Bluetooth / WLAN coexistence */
2286 #define MHF1_DCFILTWAR 0x0020 /* Enable g-mode DC canceler filter bw WAR */
2287 #define MHF1_P2P_SKIP_TIME_UPD 0x0020 /* Skip P2P SHM updates and P2P event generations */
2288 #define MHF1_PACTL 0x0040 /* Enable PA gain boost for OFDM frames */
2289 #define MHF1_ACPRWAR 0x0080 /* Enable ACPR. Disable for Japan, channel 14 */
2290 #define MHF1_RXFIFO1 0x0080 /* Switch data reception from RX fifo 0 to fifo 1 */
2291 #define MHF1_EDCF 0x0100 /* Enable EDCF access control */
2292 #define MHF1_IQSWAP_WAR 0x0200
2293 #define MHF1_ULP 0x0200 /* Force Ucode to put chip in low power state */
2294 #define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
2295 #define MHF1_ACIWAR 0x0800 /* Enable ACI war: shiftbits by 2 on PHY_CRS */
2296 #define MHF1_A2060WAR 0x1000 /* PR15874WAR */
2297 #define MHF1_TIMBC_EN 0x1000 /* Enable Target TIM Transmission Time function */
2298 #define MHF1_RADARWAR 0x2000
2299 #define MHF1_DEFKEYVALID 0x4000 /* Enable use of the default keys */
2300 #define MHF1_CTS2SELF 0x8000 /* Enable CTS to self full phy bw protection */
2301
2302 /* Definition changed in corerev >= 40 */
2303 #define MHF1_D11AC_DYNBW 0x0001 /* dynamic bw */
2304 #define MHF2_RSPBW20 0x0020 /* Uses bw20 for response frames ack/ba/cts */
2305
2306 /* Flags in M_HOST_FLAGS2 */
2307 #define MHF2_DISABLE_PRB_RESP 0x0001 /* disable Probe Response in ucode */
2308 #define MHF2_4317FWAKEWAR 0x0002 /* PR19311WAR: 4317PCMCIA, fast wakeup ucode */
2309 #define MHF2_SYNTHPUWAR 0x0004
2310 #define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
2311 #define MHF2_SKIP_ADJTSF 0x0010 /* skip TSF update when receiving bcn/probeRsp */
2312 #define MHF2_4317PIORXWAR 0x0020 /* PR38778WAR : PIO receiving */
2313 #define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
2314 #define MHF2_PPR_HWPWRCTL 0x0080 /* For corerev24+, ppr; for GPHY, Hwpwrctrl */
2315 #define MHF2_BTC2WIRE_ALTGPIO 0x0100 /* BTC 2wire in alternate pins */
2316 #define MHF2_BTCPREMPT 0x0200 /* BTC enable bluetooth check during tx */
2317 #define MHF2_SKIP_CFP_UPDATE 0x0400 /* Skip CFP update */
2318 #define MHF2_NPHY40MHZ_WAR 0x0800
2319 #define MHF2_TMP_HTRSP 0x1000 /* Temp hack to use HT response frames in ucode */
2320 #define MHF2_PAPD_FLT_DIS 0x2000 /* LPPHY adjust tx filter */
2321 #define MHF2_BTCANTMODE 0x4000 /* BTC ant mode ?? */
2322 #define MHF2_NITRO_MODE 0x8000 /* Enable Nitro mode */
2323
2324 /* Flags in M_HOST_FLAGS3 */
2325 #define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
2326 #define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
2327 #define MHF3_BTCX_DEF_BT 0x0004 /* corerev >= 13 BT Coex. */
2328 #define MHF3_BTCX_ACTIVE_PROT 0x0008 /* corerev >= 13 BT Coex. */
2329 #define MHF3_USB_OLD_NPHYMLADVWAR 0x0010
2330 #define MHF3_KNOISE 0x0020 /* Use this to enable/disable knoise. */
2331 #define MHF3_UCAMPDU_RETX 0x0040 /* ucode handles AMPDU retransmission */
2332 #define MHF3_BTCX_DELL_WAR 0x0080
2333 #define MHF3_BTCX_SIM_RSP 0x0100 /* allow limited lwo power tx when BT is active */
2334 #define MHF3_BTCX_PS_PROTECT 0x0200 /* use PS mode to protect BT activity */
2335 #define MHF3_BTCX_SIM_TX_LP 0x0400 /* use low power for simultaneous tx responses */
2336 #define MHF3_PR45960_WAR 0x0800
2337 #define MHF3_BTCX_ECI 0x1000 /* Enable BTCX ECI interface */
2338 #define MHF3_BTCX_EXTRA_PRI 0x2000 /* Extra priority for 4th wire */
2339 #define MHF3_PAPD_OFF_CCK 0x4000 /* Disable PAPD comp for CCK frames */
2340 #define MHF3_PAPD_OFF_OFDM 0x8000 /* Disable PAPD comp for OFDM frames */
2341
2342 /* Flags in M_HOST_FLAGS4 */
2343 #define MHF4_CISCOTKIP_WAR 0x0001 /* Change WME timings under certain conditions */
2344 #define MHF4_RCMTA_BSSID_EN 0x0002 /* BTAMP: multiSta BSSIDs matching in RCMTA area */
2345 #define MHF4_BCN_ROT_RR 0x0004 /* MBSSID: beacon rotate in round-robin fashion */
2346 #define MHF4_OPT_SLEEP 0x0008 /* enable opportunistic sleep */
2347 #define MHF4_PROXY_STA 0x0010 /* enable proxy-STA feature */
2348 #define MHF4_AGING 0x0020 /* Enable aging threshold for RF awareness */
2349 #define MHF4_BPHY_2TXCORES 0x0040 /* bphy Tx on both cores (negative logic) */
2350 #define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
2351 #define MHF4_BTAMP_TXLOWPWR 0x0100 /* BTAMP, low tx-power mode */
2352 #define MHF4_WMAC_ACKTMOUT 0x0200 /* reserved for WMAC testing */
2353 #define MHF4_IBSS_SEC 0x0800 /* IBSS WPA2-PSK operating mode */
2354 #define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
2355
2356 /* Flags in M_HOST_FLAGS5 */
2357 #define MHF5_4313_BTCX_GPIOCTRL 0x0001 /* Enable gpio for bt/wlan sel for 4313 */
2358 #define MHF5_4331_BTCX_LOWISOLATION 0x0001 /* Turn off txpu due to low antenna isolation */
2359 #define MHF5_BTCX_LIGHT 0x0002 /* light coex mode, off txpu only for critical BT */
2360 #define MHF5_BTCX_PARALLEL 0x0004 /* BT and WLAN run in parallel. */
2361 #define MHF5_BTCX_DEFANT 0x0008 /* default position for shared antenna */
2362 #define MHF5_P2P_MODE 0x0010 /* Enable P2P mode */
2363 #define MHF5_LEGACY_PRS 0x0020 /* Enable legacy probe resp support */
2364 #define MHF5_LCN40PHY_ANTDIV_WAR 0x0040 /* Enable LCN40PHY antidv WAR in ucode */
2365 #define MHF5_HTPHY_RSSI_PWRDN 0x0080 /* Disable RSSI_PWRDN feature */
2366 #define MHF5_TONEJAMMER_WAR 0x0100 /* Enable Tone Jammer war */
2367 #define MHF5_SPIN_AT_SLEEP 0x0800 /* Let ucode spin instead of setting SLOWCTL_PDE */
2368 #define MHF5_TXLOFT_WAR 0x1000 /* Enable TX LOFT supression war */
2369 #define MHF5_BTCX_GPIO_DEBUG 0x4000 /* Enable gpio pins for btcoex ECI signals */
2370 #define MHF5_SUPPRESS_PRB_REQ 0x8000 /* Suppress probe requests at ucode level */
2371 #define MHF5_TXLOFT_WAR 0x1000 /* Enable TX LOFT supression war */
2372
2373 /* Radio power setting for ucode */
2374 #define M_RADIO_PWR (0x32 * 2)
2375
2376 /* phy noise recorded by ucode right after tx */
2377 #define M_PHY_NOISE (0x037 * 2)
2378 #define PHY_NOISE_MASK 0x00ff
2379
2380 /* Receive Frame Data Header for 802.11b DCF-only frames */
2381 typedef struct d11rxhdr d11rxhdr_t;
2382 BWL_PRE_PACKED_STRUCT struct d11rxhdr {
2383 uint16 RxFrameSize; /* Actual byte length of the frame data received */
2384 uint16 PAD;
2385 uint16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
2386 uint16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
2387 uint16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
2388 uint16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
2389 uint16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
2390 uint16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
2391 uint16 RxStatus1; /* MAC Rx Status */
2392 uint16 RxStatus2; /* extended MAC Rx status */
2393 uint16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
2394 uint16 RxChan; /* Rx channel info or chanspec */
2395 } BWL_POST_PACKED_STRUCT;
2396
2397 #define RXHDR_LEN 24 /* sizeof d11rxhdr_t */
2398 #define FRAMELEN(h) ((h)->RxFrameSize)
2399
2400 typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
2401 BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
2402 d11rxhdr_t rxhdr;
2403 uint32 tsf_l; /* TSF_L reading */
2404 int8 rssi; /* computed instantaneous rssi in BMAC */
2405 int8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
2406 int8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
2407 int8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
2408 int8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
2409 int8 rssi_qdb; /* qdB portion of the computed rssi */
2410 } BWL_POST_PACKED_STRUCT;
2411
2412 #define WRXHDR_LEN 37 /* sizeof wlc_d11rxhdr_t */
2413
2414 /* PhyRxStatus_0: */
2415 #define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, HT, VHT */
2416 #define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
2417 #define PRXS0_CLIP_SHIFT 2
2418 #define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
2419 #define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
2420 #define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
2421 #define PRXS0_SHORTH 0x0080 /* Short Preamble */
2422 #define PRXS0_PLCPFV 0x0100 /* PLCP violation */
2423 #define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
2424 #define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
2425 #define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
2426 #define PRXS0_ANTSEL_SHIFT 0x12
2427
2428 /* subfield PRXS0_FT_MASK */
2429 #define PRXS0_CCK 0x0000
2430 #define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
2431 #define PRXS0_PREN 0x0002
2432 #define PRXS0_STDN 0x0003
2433
2434 /* subfield PRXS0_ANTSEL_MASK */
2435 #define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
2436 #define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
2437 #define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
2438 #define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
2439
2440 /* PhyRxStatus_1: */
2441 #define PRXS1_JSSI_MASK 0x00FF
2442 #define PRXS1_JSSI_SHIFT 0
2443 #define PRXS1_SQ_MASK 0xFF00
2444 #define PRXS1_SQ_SHIFT 8
2445
2446 /* nphy PhyRxStatus_1: */
2447 #define PRXS1_nphy_PWR0_MASK 0x00FF
2448 #define PRXS1_nphy_PWR1_MASK 0xFF00
2449
2450 /* PhyRxStatus_2: */
2451 #define PRXS2_LNAGN_MASK 0xC000
2452 #define PRXS2_LNAGN_SHIFT 14
2453 #define PRXS2_PGAGN_MASK 0x3C00
2454 #define PRXS2_PGAGN_SHIFT 10
2455 #define PRXS2_FOFF_MASK 0x03FF
2456
2457 /* nphy PhyRxStatus_2: */
2458 #define PRXS2_nphy_SQ_ANT0 0x000F /* nphy overall signal quality for antenna 0 */
2459 #define PRXS2_nphy_SQ_ANT1 0x00F0 /* nphy overall signal quality for antenna 0 */
2460 #define PRXS2_nphy_cck_SQ 0x00FF /* bphy signal quality(when FT field is 0) */
2461 #define PRXS3_nphy_SSQ_MASK 0xFF00 /* spatial conditioning of the two receive channels */
2462 #define PRXS3_nphy_SSQ_SHIFT 8
2463
2464 /* PhyRxStatus_3: */
2465 #define PRXS3_DIGGN_MASK 0x1800
2466 #define PRXS3_DIGGN_SHIFT 11
2467 #define PRXS3_TRSTATE 0x0400
2468
2469 /* nphy PhyRxStatus_3: */
2470 #define PRXS3_nphy_MMPLCPLen_MASK 0x0FFF /* Mixed-mode preamble PLCP length */
2471 #define PRXS3_nphy_MMPLCP_RATE_MASK 0xF000 /* Mixed-mode preamble rate field */
2472 #define PRXS3_nphy_MMPLCP_RATE_SHIFT 12
2473
2474 #define NPHY_MMPLCPLen(rxs) ((rxs)->PhyRxStatus_3 & PRXS3_nphy_MMPLCPLen_MASK)
2475
2476 /* HTPHY Rx Status defines */
2477 /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
2478 #define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
2479 #define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
2480 #define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
2481
2482 /* htphy PhyRxStatus_1: */
2483 #define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
2484 #define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configuration */
2485 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
2486
2487 /* htphy PhyRxStatus_2: */
2488 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
2489 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
2490 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
2491
2492 /* htphy PhyRxStatus_3: */
2493 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
2494 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
2495
2496 /* htphy PhyRxStatus_4: */
2497 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
2498 #define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
2499
2500 /* htphy PhyRxStatus_5: */
2501 #define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
2502 #define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
2503
2504 /* ACPHY RxStatus defs */
2505
2506 /* ACPHY PhyRxStatus_0: */
2507 #define PRXS0_ACPHY_FT_MASK 0x0003 /* CCK, OFDM, HT, VHT */
2508 #define PRXS0_ACPHY_CLIP_MASK 0x000C /* clip count adjustment steps by AGC */
2509 #define PRXS0_ACPHY_CLIP_SHIFT 2
2510 #define PRXS0_ACPHY_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
2511 #define PRXS0_ACPHY_BAND5G 0x0020 /* Rx Band indication: 0 -> 2G, 1 -> 5G */
2512 #define PRXS0_ACPHY_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
2513 #define PRXS0_ACPHY_SHORTH 0x0080 /* Short Preamble (CCK), GF preamble (HT) */
2514 #define PRXS0_ACPHY_PLCPFV 0x0100 /* PLCP violation */
2515 #define PRXS0_ACPHY_PLCPHCF 0x0200 /* PLCP header integrity check failed */
2516 #define PRXS0_ACPHY_MFCRS 0x0400 /* Matched Filter CRS fired */
2517 #define PRXS0_ACPHY_ACCRS 0x0800 /* Autocorrelation CRS fired */
2518 #define PRXS0_ACPHY_SUBBAND_MASK 0xF000 /* FinalBWClassification:
2519 * Bitfield of sub-bands occupied by Rx frame
2520 */
2521 /* acphy PhyRxStatus_3: */
2522 #define PRXS2_ACPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 1 */
2523 #define PRXS3_ACPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
2524 #define PRXS3_ACPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
2525
2526 /* acphy PhyRxStatus_4: */
2527 #define PRXS4_ACPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
2528
2529 /* Get Rx power on core 0 */
2530 #define ACPHY_RXPWR_ANT0(rxs) ((ltoh16((rxs)->PhyRxStatus_2) & PRXS2_ACPHY_RXPWR_ANT0) >> 8)
2531 /* Get Rx power on core 1 */
2532 #define ACPHY_RXPWR_ANT1(rxs) (ltoh16((rxs)->PhyRxStatus_3) & PRXS3_ACPHY_RXPWR_ANT1)
2533 /* Get Rx power on core 2 */
2534 #define ACPHY_RXPWR_ANT2(rxs) ((ltoh16((rxs)->PhyRxStatus_3) & PRXS3_ACPHY_RXPWR_ANT2) >> 8)
2535 /* Get whether the rxpwr is hacked for 11b rssi WAR */
2536 /* Tells whether the PhyRxStatus_2 & 0xFF00, PhyRxStatus_3 & 0xFFFF,
2537 * PhyRxStatus_4 & 0xFF are hacked or not,0=disabled, 1=enabled
2538 */
2539 #define PRXS1_ACPHY_BIT_HACK 0x0008
2540 #define PRXS3_ACPHY_RXPWR_ANT4 0x00FF /* Rx power on core 4 */
2541 #define ACPHY_HACK_PWR_STATUS(rxs) ((ltoh16((rxs)->PhyRxStatus_1) & PRXS1_ACPHY_BIT_HACK) >> 3)
2542 #define ACPHY_RXPWR_ANT4(rxs) (ltoh16((rxs)->PhyRxStatus_4) & PRXS3_ACPHY_RXPWR_ANT4)
2543
2544 #define PRXS5_ACPHY_DYNBWINNONHT_MASK 0x0004
2545 #define PRXS5_ACPHY_DYNBWINNONHT(rxs) (\
2546 (rxs)->PhyRxStatus_5 & PRXS5_ACPHY_DYNBWINNONHT_MASK)
2547
2548 #define PRXS5_ACPHY_CHBWINNONHT_MASK 0x0003
2549 #define PRXS5_ACPHY_CHBWINNONHT(rxs) (\
2550 (rxs)->PhyRxStatus_5 & PRXS5_ACPHY_CHBWINNONHT_MASK)
2551 #define PRXS5_ACPHY_CHBWINNONHT_20MHZ 0
2552 #define PRXS5_ACPHY_CHBWINNONHT_40MHZ 1
2553 #define PRXS5_ACPHY_CHBWINNONHT_80MHZ 2
2554 #define PRXS5_ACPHY_CHBWINNONHT_160MHZ 3 /* includes 80+80 */
2555
2556 /* ACPHY PhyRxStatus0 SubBand (FinalBWClassification) bit defs
2557 * FinalBWClassification is a 4 bit field, each bit representing one 20MHz sub-band
2558 * of a channel.
2559 */
2560 enum prxs_subband {
2561 PRXS_SUBBAND_20LL = 0x1000,
2562 PRXS_SUBBAND_20LU = 0x2000,
2563 PRXS_SUBBAND_20UL = 0x4000,
2564 PRXS_SUBBAND_20UU = 0x8000,
2565 PRXS_SUBBAND_40L = 0x3000,
2566 PRXS_SUBBAND_40U = 0xC000,
2567 PRXS_SUBBAND_80 = 0xF000
2568 };
2569
2570 enum prxs_subband_bphy {
2571 PRXS_SUBBAND_BPHY_20L = 0x0000,
2572 PRXS_SUBBAND_BPHY_20U = 0x1000
2573 };
2574
2575 /* ucode RxStatus1: */
2576 #define RXS_BCNSENT 0x8000
2577 #define RXS_SECKINDX_MASK 0x07e0
2578 #define RXS_SECKINDX_SHIFT 5
2579 #define RXS_DECERR (1 << 4)
2580 #define RXS_DECATMPT (1 << 3)
2581 #define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
2582 #define RXS_RESPFRAMETX (1 << 1)
2583 #define RXS_FCSERR (1 << 0)
2584
2585 /* ucode RxStatus2: */
2586 #define RXS_AMSDU_MASK 1
2587 #define RXS_AGGTYPE_MASK 0x6
2588 #define RXS_AGGTYPE_SHIFT 1
2589 #define RXS_AMSDU_FIRST 1
2590 #define RXS_AMSDU_INTERMEDIATE 0
2591 #define RXS_AMSDU_LAST 2
2592 #define RXS_AMSDU_N_ONE 3
2593 #define RXS_TKMICATMPT (1 << 3)
2594 #define RXS_TKMICERR (1 << 4)
2595 #define RXS_PHYRXST_PRISEL_CLR (1 << 5)
2596 /* packet was received while the antenna */
2597 /* (prisel) had been granted to BT. */
2598 #define RXS_PHYRXST_VALID (1 << 8)
2599 #define RXS_BCNCLSG (1 << 9) /* Coleasced beacon packet */
2600 #define RXS_RXANT_MASK 0x3
2601 #define RXS_RXANT_SHIFT 12
2602
2603
2604 /* RxChan */
2605 #define RXS_CHAN_40 0x1000
2606 #define RXS_CHAN_5G 0x0800
2607 #define RXS_CHAN_ID_MASK 0x07f8
2608 #define RXS_CHAN_ID_SHIFT 3
2609
2610 /* Index of attenuations used during ucode power control. */
2611 #define M_PWRIND_BLKS (0x184 * 2)
2612 #define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
2613 #define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
2614 #define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
2615 #define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
2616 #define M_PWRIND_MAP4 (M_PWRIND_BLKS + 0x8)
2617 #define M_PWRIND_MAP5 (M_PWRIND_BLKS + 0xa)
2618 /* M_PWRIND_MAP(core) macro */
2619 #define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
2620
2621 /* CCA Statistics */
2622 /* core_rev < 40 */
2623 #define M_CCA_STATS_BLK_PRE40 (0x360 * 2)
2624 #define M_CCA_STATS_BLK (0x3b4 * 2)
2625 #define M_CCA_TXDUR_L (M_CCA_STATS_BLK + 0x0)
2626 #define M_CCA_TXDUR_H (M_CCA_STATS_BLK + 0x2)
2627 #define M_CCA_INBSS_L (M_CCA_STATS_BLK + 0x4)
2628 #define M_CCA_INBSS_H (M_CCA_STATS_BLK + 0x6)
2629 #define M_CCA_OBSS_L (M_CCA_STATS_BLK + 0x8)
2630 #define M_CCA_OBSS_H (M_CCA_STATS_BLK + 0xa)
2631 #define M_CCA_NOCTG_L (M_CCA_STATS_BLK + 0xc)
2632 #define M_CCA_NOCTG_H (M_CCA_STATS_BLK + 0xe)
2633 #define M_CCA_NOPKT_L (M_CCA_STATS_BLK + 0x10)
2634 #define M_CCA_NOPKT_H (M_CCA_STATS_BLK + 0x12)
2635 #define M_MAC_DOZE_L (M_CCA_STATS_BLK + 0x14)
2636 #define M_MAC_DOZE_H (M_CCA_STATS_BLK + 0x16)
2637
2638 #define M_CCA_FLAGS (0x9b7 * 2)
2639
2640 /* PSM SHM variable offsets */
2641 #define M_PSM_SOFT_REGS 0x0
2642 #define M_PSM_SOFT_REGS_EXT (0xc0*2) /* corerev >= 40 only */
2643 #define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
2644 #define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
2645 #define M_UCODE_DATE (M_PSM_SOFT_REGS + 0x4) /* 4:4:8 year:month:day format */
2646 #define M_UCODE_TIME (M_PSM_SOFT_REGS + 0x6) /* 5:6:5 hour:min:sec format */
2647 #define M_SHM_BYT_CNT (M_PSM_SOFT_REGS + (0x0a * 2))
2648 #define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
2649 #define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
2650 #define M_UCODE_MACSTAT1 (0x3d8*2) /* macstat1 counters : corerev >= 40 only */
2651 #define M_UCODE_BSSBCNCNT (M_UCODE_MACSTAT + 0x4e) /* rxbeaconmbss */
2652
2653 #define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
2654 #define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
2655 #define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
2656 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
2657 #define M_PRETBTT (0x4b * 2)
2658
2659 #define M_BTCX_MAX_INDEX 130
2660 #define M_BTCX_BLK_PTR (M_PSM_SOFT_REGS + (0x49 * 2))
2661 #define M_BTCX_PRED_PER (4 * 2)
2662 #define M_BTCX_LAST_SCO (12 * 2)
2663 #define M_BTCX_LAST_SCO_H (13 * 2)
2664 #define M_BTCX_NEXT_SCO (14 * 2)
2665 #define M_BTCX_LAST_DATA (23 * 2)
2666 #define M_BTCX_A2DP_BUFFER (30 * 2)
2667 #define M_BTCX_LAST_A2DP (38 * 2)
2668 #define M_BTCX_A2DP_BUFFER_LOWMARK (40 * 2)
2669 #define M_BTCX_PRED_PER_COUNT (72 * 2)
2670 #define M_BTCX_PROT_RSSI_THRESH (73 * 2)
2671 #define M_BTCX_AMPDUTX_RSSI_THRESH (74 * 2)
2672 #define M_BTCX_AMPDURX_RSSI_THRESH (75 * 2)
2673 #define M_BTCX_WARS (82 * 2)
2674 #define M_BTCX_SNIFF_LO_THRESHOLD (84 * 2)
2675 #define M_BTCX_DIVERSITY_SAVE (89 * 2)
2676 /* the threshold to switch to btc_mode 4 simulteneous coex */
2677 #define M_BTCX_HIGH_THRESH (100 * 2)
2678 /* the threshold to switch to btc_mode 1 strict tdd coex */
2679 #define M_BTCX_LOW_THRESH (101 * 2)
2680 #define M_BTCX_CONFIG (103 * 2)
2681 #define M_BTCX_NUM_TASKS (118 * 2)
2682 #define M_BTCX_VSDB (120 * 2)
2683
2684
2685 #define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
2686 #define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
2687 #define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
2688 #define M_SSLPN_OLYMPIC (M_PSM_SOFT_REGS + (0x68 * 2))
2689 #define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
2690
2691 /* ARM offloads */
2692 #define M_ARM_PSO_BLK_PTR (0x4F * 2)
2693 #define M_PSO_ENBL_FLGS 0 /* 1 word: Flags to enable various PSO offload modes */
2694 #define M_DEFER_RXCNT 2 /* 1 word: Rx Count Watermark for PSO deferral */
2695 #define M_RXF0_SUPR_PTRS 4 /* 2 words: Frame pointers used for suppression/deletion */
2696
2697 /* ARM offloads- TX Status offsets */
2698 #define M_TXS_FIFO_RPTR 8 /* 1 word: Read pointer of ARM txstatus fifo */
2699 #define M_TXS_FIFO_WPTR 10 /* 1 word: Write pointer of ARM txstatus fifo */
2700 #define M_TXS_FIFO_BLK 12 /* 25 words: ARM txstatus fifo (each txstatus has 5 words) */
2701 #define M_TXS_FIFO_BLK_SIZE 50 /* mark the end of the txstatus fifo */
2702 #define M_TXS_SIZE 10
2703 #define M_TXS_MAX_ENTRIES (M_TXS_FIFO_BLK_SIZE/M_TXS_SIZE)
2704
2705
2706 #ifdef WLP2P_UCODE
2707 /* WiFi P2P SHM location */
2708 #define M_P2P_BLK_PTR (M_PSM_SOFT_REGS + (0x57 * 2))
2709
2710 /* The number of scheduling blocks */
2711 #define M_P2P_BSS_MAX 4
2712
2713 /* WiFi P2P interrupt block positions */
2714 #define M_P2P_I_BLK_SZ 4
2715 #define M_P2P_I_BLK(b) ((0x0 * 2) + (M_P2P_I_BLK_SZ * (b) * 2))
2716 #define M_P2P_I(b, i) (M_P2P_I_BLK(b) + ((i) * 2))
2717
2718 #define M_P2P_I_PRE_TBTT 0 /* pretbtt */
2719 #define M_P2P_I_CTW_END 1 /* CTWindow ends */
2720 #define M_P2P_I_ABS 2 /* absence period starts */
2721 #define M_P2P_I_PRS 3 /* presence period starts */
2722
2723 /* P2P hps flags */
2724 #define M_P2P_HPS ((0x10 * 2))
2725 #define M_P2P_HPS_CTW(b) (1 << (b))
2726 #define M_P2P_HPS_NOA(b) (1 << ((b) + M_P2P_BSS_MAX))
2727
2728 /* WiFi P2P address attribute block */
2729 #define M_ADDR_BMP_BLK_SZ 12
2730 #define M_ADDR_BMP_BLK(b) ((0x11 * 2) + ((b) * 2))
2731
2732 #define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
2733 #define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
2734 #define ADDR_BMP_BSSID (1 << 2) /* BSSID */
2735 #define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
2736 #define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
2737 #define ADDR_BMP_P2P_DISC (1 << 5) /* P2P Device */
2738 #define ADDR_BMP_P2P_GO (1 << 6) /* P2P Group Owner */
2739 #define ADDR_BMP_P2P_GC (1 << 7) /* P2P Client */
2740 #define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
2741 #define ADDR_BMP_BSS_IDX_SHIFT 8
2742
2743 /* WiFi P2P address starts from this entry in RCMTA */
2744 #define P2P_ADDR_STRT_INDX (RCMTA_SIZE - M_ADDR_BMP_BLK_SZ)
2745
2746 /* WiFi P2P per BSS control block positions.
2747 * all time related fields are in units of 128us unless noted otherwise.
2748 */
2749 #define P2P_UCODE_TIME_SHIFT 7
2750
2751 #define M_P2P_BSS_BLK_SZ 12
2752 #define M_P2P_BSS_BLK(b) ((0x1d * 2) + (M_P2P_BSS_BLK_SZ * (b) * 2))
2753 #define M_P2P_BSS(b, p) (M_P2P_BSS_BLK(b) + (p) * 2)
2754 #define M_P2P_BSS_BCN_INT(b) (M_P2P_BSS_BLK(b) + (0 * 2)) /* beacon interval */
2755 #define M_P2P_BSS_DTIM_PRD(b) (M_P2P_BSS_BLK(b) + (1 * 2)) /* DTIM period */
2756 #define M_P2P_BSS_ST(b) (M_P2P_BSS_BLK(b) + (2 * 2)) /* current state */
2757 #define M_P2P_BSS_N_PRE_TBTT(b) (M_P2P_BSS_BLK(b) + (3 * 2)) /* next pretbtt time */
2758 #define M_P2P_BSS_CTW(b) (M_P2P_BSS_BLK(b) + (4 * 2)) /* CTWindow duration */
2759 #define M_P2P_BSS_N_CTW_END(b) (M_P2P_BSS_BLK(b) + (5 * 2)) /* next CTWindow end */
2760 #define M_P2P_BSS_NOA_CNT(b) (M_P2P_BSS_BLK(b) + (6 * 2)) /* NoA count */
2761 #define M_P2P_BSS_N_NOA(b) (M_P2P_BSS_BLK(b) + (7 * 2)) /* next absence time */
2762 #define M_P2P_BSS_NOA_DUR(b) (M_P2P_BSS_BLK(b) + (8 * 2)) /* absence period */
2763 #define M_P2P_BSS_NOA_TD(b) (M_P2P_BSS_BLK(b) + (9 * 2)) /* presence period (int - dur) */
2764 #define M_P2P_BSS_NOA_OFS(b) (M_P2P_BSS_BLK(b) + (10 * 2)) /* last 7 bits of interval in us */
2765 #define M_P2P_BSS_DTIM_CNT(b) (M_P2P_BSS_BLK(b) + (11 * 2)) /* DTIM count */
2766
2767 /* M_P2P_BSS_ST word positions. */
2768 #define M_P2P_BSS_ST_CTW (1 << 0) /* BSS is in CTWindow */
2769 #define M_P2P_BSS_ST_SUPR (1 << 1) /* BSS is suppressing frames */
2770 #define M_P2P_BSS_ST_ABS (1 << 2) /* BSS is in absence period */
2771 #define M_P2P_BSS_ST_WAKE (1 << 3)
2772 #define M_P2P_BSS_ST_AP (1 << 4) /* BSS is Infra-BSS AP */
2773 #define M_P2P_BSS_ST_STA (1 << 5) /* BSS is Infra-BSS STA */
2774 #define M_P2P_BSS_ST_GO (1 << 6) /* BSS is P2P Group Owner */
2775 #define M_P2P_BSS_ST_GC (1 << 7) /* BSS is P2P Client */
2776
2777 /* WiFi P2P TSF block positions */
2778 #define M_P2P_TSF_BLK_SZ 4
2779 #define M_P2P_TSF_BLK(b) ((0x4d * 2) + (M_P2P_TSF_BLK_SZ * (b) * 2))
2780 #define M_P2P_TSF(b, w) (M_P2P_TSF_BLK(b) + (w) * 2)
2781
2782 /* GO operating channel */
2783 #define M_P2P_GO_CHANNEL ((0x5d * 2))
2784 #define M_P2P_GO_IND_BMP ((0x5e * 2))
2785
2786 /* M_P2P_GO_IND_BMP now has multiple fields:
2787 7:0 - GO_IND_BMP
2788 10:8 - BSS Index
2789 15:11 - Reserved
2790 */
2791 #define M_P2P_GO_IND_BMP_MASK (0xFF)
2792 #define M_P2P_BSS_INDEX_MASK (0x7)
2793 #define M_P2P_BSS_INDEX_SHIFT_BITS (8)
2794
2795 /* per BSS PreTBTT */
2796 #define M_P2P_BSS_PRE_TBTT(b) ((0x5f * 2) + ((b) * 2)) /* in us */
2797 #endif /* WLP2P_UCODE */
2798
2799 #define ADDR_STAMON_NBIT (1 << 10) /* STA monitor bit in AMT_INFO_BLK entity */
2800
2801 #ifdef WLP2P_UCODE
2802 /* Reserve bottom of RCMTA for P2P Addresses */
2803 #define WSEC_MAX_RCMTA_KEYS (54 - M_ADDR_BMP_BLK_SZ)
2804 #else
2805 #define WSEC_MAX_RCMTA_KEYS 54
2806 #endif
2807
2808 /* PKTENG Rx Stats Block */
2809 #define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
2810
2811 /* LUT for Phy/Radio Registers for Idle TSSI measurement */
2812 #define M_TSSI_MSMT_BLK_PTR (M_PSM_SOFT_REGS + (53 * 2))
2813 #define M_LCNPHY_TSSICAL_EN (0 * 2)
2814 #define M_PHY_REG_LUT_CNT (1 * 2)
2815 #define M_RADIO_REG_LUT_CNT (2 * 2)
2816 #define M_LUT_PHY_REG_RESTORE_BLK (3 * 2) /* 26 locations, 13 regs */
2817 #define M_LUT_PHY_REG_SETUP_BLK (29 * 2) /* 26 locations, 13 regs */
2818 #define M_LUT_RADIO_REG_RESTORE_BLK (55 * 2) /* 30 locations, 15 regs */
2819 #define M_LUT_RADIO_REG_SETUP_BLK (85 * 2) /* 30 locations, 15 regs */
2820 #define M_LCNPHY_TSSICAL_DELAY (115 * 2)
2821 #define M_LCNPHY_TSSICAL_TIME (116 * 2)
2822
2823 /* Txcore Mask related parameters 5 locations (BPHY, OFDM, 1-streams ~ 3-Streams */
2824 /* precorerev 40 one */
2825 #define D11_PRE40_M_COREMASK_BLK 0x374 /* (1BA * 2) */
2826 #define M_COREMASK_BLK 0x2ea
2827
2828 #define M_COREMASK_BPHY ((M_COREMASK_BLK + 0) * 2)
2829 #define M_COREMASK_OFDM ((M_COREMASK_BLK + 1) * 2)
2830 #define M_COREMASK_MCS ((M_COREMASK_BLK + 2) * 2)
2831 #define M_COREMASK_BFM ((M_COREMASK_BLK + 4) * 2)
2832 #define M_COREMASK_BTRESP ((M_COREMASK_BLK + 5) * 2)
2833 #define TXCOREMASK 0x0F
2834 #define SPATIAL_SHIFT 8
2835 #define MAX_COREMASK_BLK 4
2836
2837
2838
2839 /* ucode debug status codes */
2840 #define DBGST_INACTIVE 0 /* not valid really */
2841 #define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
2842 #define DBGST_ACTIVE 2 /* "normal" state */
2843 #define DBGST_SUSPENDED 3 /* suspended */
2844 #define DBGST_ASLEEP 4 /* asleep (PS mode) */
2845
2846 /* Radio ID */
2847 #define M_RADIOID_L_OFFSET 0x43
2848 #define M_RADIOID_H_OFFSET 0x44
2849
2850 /* Scratch Reg defs */
2851 typedef enum
2852 {
2853 S_RSV0 = 0,
2854 S_RSV1,
2855 S_RSV2,
2856
2857 /* scratch registers for Dot11-constants */
2858 S_DOT11_CWMIN, /* CW-minimum 0x03 */
2859 S_DOT11_CWMAX, /* CW-maximum 0x04 */
2860 S_DOT11_CWCUR, /* CW-current 0x05 */
2861 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
2862 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
2863 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
2864
2865 /* Tx-side scratch registers */
2866 S_SEQ_NUM, /* hardware sequence number reg 0x09 */
2867 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
2868 S_FRMRETX_CNT, /* frame retx count 0x0B */
2869 S_SSRC, /* Station short retry count 0x0C */
2870 S_SLRC, /* Station long retry count 0x0D */
2871 S_EXP_RSP, /* Expected response frame 0x0E */
2872 S_OLD_BREM, /* Remaining backoff ctr 0x0F */
2873 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
2874 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
2875 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
2876
2877 /* Rx-side scratch registers */
2878 S_RXTST, /* Type and subtype in Rxframe 0x13 */
2879
2880 /* Global state register */
2881 S_STREG, /* state storage actual bit maps below 0x14 */
2882
2883 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
2884 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
2885 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
2886 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
2887
2888 S_KEYINDX, /* 0x19 */
2889 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
2890
2891 /* Receive TSF time stored in SCR */
2892 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
2893 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
2894 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
2895 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
2896 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
2897 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
2898
2899 /* Scratch pad regs used in microcode as temp storage */
2900 S_TMP0, /* stmp0 0x21 */
2901 S_TMP1, /* stmp1 0x22 */
2902 S_TMP2, /* stmp2 0x23 */
2903 S_TMP3, /* stmp3 0x24 */
2904 S_TMP4, /* stmp4 0x25 */
2905 S_TMP5, /* stmp5 0x26 */
2906 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
2907 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
2908 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
2909 S_RXTP, /* rx frame type 0x2A */
2910 S_STREG2, /* extra state storage 0x2B */
2911 S_STREG3, /* even more extra state storage 0x2C */
2912 S_STREG4, /* ... 0x2D */
2913 S_STREG5, /* remember to initialize it to zero 0x2E */
2914
2915 S_NITRO_TXT, /* NITRO: time of MP_ACK or Rsp frm trans 0x2F */
2916 S_NITRO_RXAID, /* NITRO: received child AID (at Parent) 0x30 */
2917
2918 S_ADJPWR_IDX,
2919 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
2920 S_REVID4, /* 0x33 */
2921 S_INDX, /* 0x34 */
2922 S_ADDR0, /* 0x35 */
2923 S_ADDR1, /* 0x36 */
2924 S_ADDR2, /* 0x37 */
2925 S_ADDR3, /* 0x38 */
2926 S_ADDR4, /* 0x39 */
2927 S_ADDR5, /* 0x3A */
2928 S_TMP6, /* 0x3B */
2929 S_KEYINDX_BU, /* Backup for Key index 0x3C */
2930 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
2931 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
2932 S_STREG6, /* 0x3F */
2933 } ePsmScratchPadRegDefinitions;
2934
2935 #define S_BEACON_INDX S_OLD_BREM
2936 #define S_PRS_INDX S_OLD_CWWIN
2937 #define S_BTCX_BT_DUR S_REVID4
2938 #define S_PHYTYPE S_SSRC
2939 #define S_PHYVER S_SLRC
2940
2941 /* IHR offsets */
2942 #define PHY_CTRL 0x49
2943
2944 #define TSF_TMR_TSF_L 0x119
2945 #define TSF_TMR_TSF_ML 0x11A
2946 #define TSF_TMR_TSF_MU 0x11B
2947 #define TSF_TMR_TSF_H 0x11C
2948
2949 #define TSF_GPT_0_STAT 0x123
2950 #define TSF_GPT_1_STAT 0x124
2951 #define TSF_GPT_0_CTR_L 0x125
2952 #define TSF_GPT_1_CTR_L 0x126
2953 #define TSF_GPT_0_CTR_H 0x127
2954 #define TSF_GPT_1_CTR_H 0x128
2955 #define TSF_GPT_0_VAL_L 0x129
2956 #define TSF_GPT_1_VAL_L 0x12A
2957 #define TSF_GPT_0_VAL_H 0x12B
2958 #define TSF_GPT_1_VAL_H 0x12C
2959
2960 /* GPT_2 is corerev >= 3 */
2961 #define TSF_GPT_2_STAT 0x133
2962 #define TSF_GPT_2_CTR_L 0x134
2963 #define TSF_GPT_2_CTR_H 0x135
2964 #define TSF_GPT_2_VAL_L 0x136
2965 #define TSF_GPT_2_VAL_H 0x137
2966
2967 /* Slow timer registers */
2968 #define SLOW_CTRL 0x150
2969 #define SLOW_TIMER_L 0x151
2970 #define SLOW_TIMER_H 0x152
2971 #define SLOW_FRAC 0x153
2972 #define FAST_PWRUP_DLY 0x154
2973
2974 /* IHR PHY_CTRL STAT values */
2975 #define PHY_CTRL_MC (1 << 1)
2976 #define PHY_CTRL_RESTORESTART (1 << 14)
2977
2978 /* PSO mode */
2979 #define PSO_CTRL 0x290
2980 #define PSO_RXWORD_WMK 0x291
2981 #define PSO_RXCNT_WMK 0x292
2982
2983 /* IHR TSF_GPT STAT values */
2984 #define TSF_GPT_PERIODIC (1 << 12)
2985 #define TSF_GPT_ADJTSF (1 << 13)
2986 #define TSF_GPT_USETSF (1 << 14)
2987 #define TSF_GPT_ENABLE (1 << 15)
2988
2989 /* IHR SLOW_CTRL values */
2990 #define SLOW_CTRL_PDE (1 << 0)
2991 #define SLOW_CTRL_FD (1 << 8)
2992
2993 /* PSO CTRL values */
2994 #define PSO_FRM_SUPPRESS (1 << 8)
2995 #define PSO_MODE (1 << 0)
2996
2997 /* ucode mac statistic counters in shared memory */
2998 typedef struct macstat {
2999 uint16 txallfrm; /* 0x80 */
3000 uint16 txrtsfrm; /* 0x82 */
3001 uint16 txctsfrm; /* 0x84 */
3002 uint16 txackfrm; /* 0x86 */
3003 uint16 txdnlfrm; /* 0x88 */
3004 uint16 txbcnfrm; /* 0x8a */
3005 uint16 txfunfl[6]; /* 0x8c - 0x96 */
3006 uint16 txfbw; /* 0x98 */
3007 uint16 PAD; /* 0x9a */
3008 uint16 txtplunfl; /* 0x9c */
3009 uint16 txphyerr; /* 0x9e */
3010 uint16 pktengrxducast; /* 0xa0 */
3011 uint16 pktengrxdmcast; /* 0xa2 */
3012 uint16 rxfrmtoolong; /* 0xa4 */
3013 uint16 rxfrmtooshrt; /* 0xa6 */
3014 uint16 rxinvmachdr; /* 0xa8 */
3015 uint16 rxbadfcs; /* 0xaa */
3016 uint16 rxbadplcp; /* 0xac */
3017 uint16 rxcrsglitch; /* 0xae */
3018 uint16 rxstrt; /* 0xb0 */
3019 uint16 rxdfrmucastmbss; /* 0xb2 */
3020 uint16 rxmfrmucastmbss; /* 0xb4 */
3021 uint16 rxcfrmucast; /* 0xb6 */
3022 uint16 rxrtsucast; /* 0xb8 */
3023 uint16 rxctsucast; /* 0xba */
3024 uint16 rxackucast; /* 0xbc */
3025 uint16 rxdfrmocast; /* 0xbe */
3026 uint16 rxmfrmocast; /* 0xc0 */
3027 uint16 rxcfrmocast; /* 0xc2 */
3028 uint16 rxrtsocast; /* 0xc4 */
3029 uint16 rxctsocast; /* 0xc6 */
3030 uint16 rxdfrmmcast; /* 0xc8 */
3031 uint16 rxmfrmmcast; /* 0xca */
3032 uint16 rxcfrmmcast; /* 0xcc */
3033 uint16 rxbeaconmbss; /* 0xce */
3034 uint16 rxdfrmucastobss; /* 0xd0 */
3035 uint16 rxbeaconobss; /* 0xd2 */
3036 uint16 rxrsptmout; /* 0xd4 */
3037 uint16 bcntxcancl; /* 0xd6 */
3038 uint16 PAD;
3039 uint16 rxf0ovfl; /* 0xda */
3040 uint16 rxf1ovfl; /* 0xdc */
3041 uint16 rxf2ovfl; /* 0xde */
3042 uint16 txsfovfl; /* 0xe0 */
3043 uint16 pmqovfl; /* 0xe2 */
3044 uint16 rxcgprqfrm; /* 0xe4 */
3045 uint16 rxcgprsqovfl; /* 0xe6 */
3046 uint16 txcgprsfail; /* 0xe8 */
3047 uint16 txcgprssuc; /* 0xea */
3048 uint16 prs_timeout; /* 0xec */
3049 uint16 rxnack;
3050 uint16 frmscons;
3051 uint16 txnack;
3052 uint16 rxback;
3053 uint16 txback; /* 0xf6 # tx bursts */
3054 uint16 bphy_rxcrsglitch; /* bphy rx crs glitch */
3055 uint16 rxdrop20s; /* 0xfa */
3056 uint16 rxtoolate;
3057 uint16 bphy_badplcp; /* bphy bad plcp */
3058 } macstat_t;
3059
3060 /* ucode mac statistic counters in shared memory, base addr defined in M_UCODE_MACSTAT1 */
3061 typedef struct macstat1 {
3062 uint16 txndpa; /* + 0 */
3063 uint16 txndp; /* + 1*2 */
3064 uint16 txsf; /* + 2*2 */
3065 uint16 txcwrts; /* + 3*2 */
3066 uint16 txcwcts; /* + 4*2 */
3067 uint16 txbfm; /* + 5*2 */
3068 uint16 rxndpaucast; /* + 6*2 */
3069 uint16 bferptrdy; /* + 7*2 */
3070 uint16 rxsfucast; /* + 8*2 */
3071 uint16 rxcwrtsucast; /* + 9*2 */
3072 uint16 rxcwctsucast; /* +10*2 */
3073 uint16 rtggrt; /* +11*2 */
3074 uint16 rtgack; /* +12*2 */
3075 uint16 btc_rfact_l; /* +13*2 */
3076 uint16 btc_rfact_h; /* +14*2 */
3077 uint16 btc_txconf_l; /* +15*2 : cnt */
3078 uint16 btc_txconf_h; /* +16*2 : cnt */
3079 uint16 btc_txconf_durl; /* +17*2 : dur */
3080 uint16 btc_txconf_durh; /* +18*2 : dur */
3081 uint16 rxsecrssi0; /* +19*2 : high bin */
3082 uint16 rxsecrssi1; /* +20*2 : med bin */
3083 uint16 rxsecrssi2; /* +21*2 : low bin */
3084 uint16 rxpri_durl; /* +22*2 : dur */
3085 uint16 rxpri_durh; /* +23*2 : dur */
3086 uint16 rxsec20_durl; /* +24*2 : dur */
3087 uint16 rxsec20_durh; /* +25*2 : dur */
3088 uint16 rxsec40_durl; /* +26*2 : dur */
3089 uint16 rxsec40_durh; /* +27*2 : dur */
3090 } macstat1_t;
3091
3092 /* dot11 core-specific control flags */
3093 #define SICF_PCLKE 0x0004 /* PHY clock enable */
3094 #define SICF_PRST 0x0008 /* PHY reset */
3095 #define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
3096 #define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */
3097 /* NOTE: the following bw bits only apply when the core is attached
3098 * to a NPHY (and corerev >= 11 which it will always be for NPHYs).
3099 */
3100 #define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
3101 #define SICF_BW80 0x00c0 /* 80MHz BW */
3102 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
3103 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
3104 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
3105 #define SICF_DAC 0x0300 /* Highspeed DAC mode control field */
3106 #define SICF_GMODE 0x2000 /* gmode enable */
3107
3108 /* dot11 core-specific status flags */
3109 #define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */
3110 #define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */
3111 #define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */
3112 #define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */
3113
3114
3115 /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
3116
3117 #define BPHY_REG_OFT_BASE 0x0
3118 /* offsets for indirect access to bphy registers */
3119 #define BPHY_BB_CONFIG 0x01
3120 #define BPHY_ADCBIAS 0x02
3121 #define BPHY_ANACORE 0x03
3122 #define BPHY_PHYCRSTH 0x06
3123 #define BPHY_TEST 0x0a
3124 #define BPHY_PA_TX_TO 0x10
3125 #define BPHY_SYNTH_DC_TO 0x11
3126 #define BPHY_PA_TX_TIME_UP 0x12
3127 #define BPHY_RX_FLTR_TIME_UP 0x13
3128 #define BPHY_TX_POWER_OVERRIDE 0x14
3129 #define BPHY_RF_OVERRIDE 0x15
3130 #define BPHY_RF_TR_LOOKUP1 0x16
3131 #define BPHY_RF_TR_LOOKUP2 0x17
3132 #define BPHY_COEFFS 0x18
3133 #define BPHY_PLL_OUT 0x19
3134 #define BPHY_REFRESH_MAIN 0x1a
3135 #define BPHY_REFRESH_TO0 0x1b
3136 #define BPHY_REFRESH_TO1 0x1c
3137 #define BPHY_RSSI_TRESH 0x20
3138 #define BPHY_IQ_TRESH_HH 0x21
3139 #define BPHY_IQ_TRESH_H 0x22
3140 #define BPHY_IQ_TRESH_L 0x23
3141 #define BPHY_IQ_TRESH_LL 0x24
3142 #define BPHY_GAIN 0x25
3143 #define BPHY_LNA_GAIN_RANGE 0x26
3144 #define BPHY_JSSI 0x27
3145 #define BPHY_TSSI_CTL 0x28
3146 #define BPHY_TSSI 0x29
3147 #define BPHY_TR_LOSS_CTL 0x2a
3148 #define BPHY_LO_LEAKAGE 0x2b
3149 #define BPHY_LO_RSSI_ACC 0x2c
3150 #define BPHY_LO_IQMAG_ACC 0x2d
3151 #define BPHY_TX_DC_OFF1 0x2e
3152 #define BPHY_TX_DC_OFF2 0x2f
3153 #define BPHY_PEAK_CNT_THRESH 0x30
3154 #define BPHY_FREQ_OFFSET 0x31
3155 #define BPHY_DIVERSITY_CTL 0x32
3156 #define BPHY_PEAK_ENERGY_LO 0x33
3157 #define BPHY_PEAK_ENERGY_HI 0x34
3158 #define BPHY_SYNC_CTL 0x35
3159 #define BPHY_TX_PWR_CTRL 0x36
3160 #define BPHY_TX_EST_PWR 0x37
3161 #define BPHY_STEP 0x38
3162 #define BPHY_WARMUP 0x39
3163 #define BPHY_LMS_CFF_READ 0x3a
3164 #define BPHY_LMS_COEFF_I 0x3b
3165 #define BPHY_LMS_COEFF_Q 0x3c
3166 #define BPHY_SIG_POW 0x3d
3167 #define BPHY_RFDC_CANCEL_CTL 0x3e
3168 #define BPHY_HDR_TYPE 0x40
3169 #define BPHY_SFD_TO 0x41
3170 #define BPHY_SFD_CTL 0x42
3171 #define BPHY_DEBUG 0x43
3172 #define BPHY_RX_DELAY_COMP 0x44
3173 #define BPHY_CRS_DROP_TO 0x45
3174 #define BPHY_SHORT_SFD_NZEROS 0x46
3175 #define BPHY_DSSS_COEFF1 0x48
3176 #define BPHY_DSSS_COEFF2 0x49
3177 #define BPHY_CCK_COEFF1 0x4a
3178 #define BPHY_CCK_COEFF2 0x4b
3179 #define BPHY_TR_CORR 0x4c
3180 #define BPHY_ANGLE_SCALE 0x4d
3181 #define BPHY_TX_PWR_BASE_IDX 0x4e
3182 #define BPHY_OPTIONAL_MODES2 0x4f
3183 #define BPHY_CCK_LMS_STEP 0x50
3184 #define BPHY_BYPASS 0x51
3185 #define BPHY_CCK_DELAY_LONG 0x52
3186 #define BPHY_CCK_DELAY_SHORT 0x53
3187 #define BPHY_PPROC_CHAN_DELAY 0x54
3188 #define BPHY_DDFS_ENABLE 0x58
3189 #define BPHY_PHASE_SCALE 0x59
3190 #define BPHY_FREQ_CONTROL 0x5a
3191 #define BPHY_LNA_GAIN_RANGE_10 0x5b
3192 #define BPHY_LNA_GAIN_RANGE_32 0x5c
3193 #define BPHY_OPTIONAL_MODES 0x5d
3194 #define BPHY_RX_STATUS2 0x5e
3195 #define BPHY_RX_STATUS3 0x5f
3196 #define BPHY_DAC_CONTROL 0x60
3197 #define BPHY_ANA11G_FILT_CTRL 0x62
3198 #define BPHY_REFRESH_CTRL 0x64
3199 #define BPHY_RF_OVERRIDE2 0x65
3200 #define BPHY_SPUR_CANCEL_CTRL 0x66
3201 #define BPHY_FINE_DIGIGAIN_CTRL 0x67
3202 #define BPHY_RSSI_LUT 0x88
3203 #define BPHY_RSSI_LUT_END 0xa7
3204 #define BPHY_TSSI_LUT 0xa8
3205 #define BPHY_TSSI_LUT_END 0xc7
3206 #define BPHY_TSSI2PWR_LUT 0x380
3207 #define BPHY_TSSI2PWR_LUT_END 0x39f
3208 #define BPHY_LOCOMP_LUT 0x3a0
3209 #define BPHY_LOCOMP_LUT_END 0x3bf
3210 #define BPHY_TXGAIN_LUT 0x3c0
3211 #define BPHY_TXGAIN_LUT_END 0x3ff
3212
3213 /* Bits in BB_CONFIG: */
3214 #define PHY_BBC_ANT_MASK 0x0180
3215 #define PHY_BBC_ANT_SHIFT 7
3216 #define BB_DARWIN 0x1000
3217 #define BBCFG_RESETCCA 0x4000
3218 #define BBCFG_RESETRX 0x8000
3219
3220 /* Bits in phytest(0x0a): */
3221 #define TST_DDFS 0x2000
3222 #define TST_TXFILT1 0x0800
3223 #define TST_UNSCRAM 0x0400
3224 #define TST_CARR_SUPP 0x0200
3225 #define TST_DC_COMP_LOOP 0x0100
3226 #define TST_LOOPBACK 0x0080
3227 #define TST_TXFILT0 0x0040
3228 #define TST_TXTEST_ENABLE 0x0020
3229 #define TST_TXTEST_RATE 0x0018
3230 #define TST_TXTEST_PHASE 0x0007
3231
3232 /* phytest txTestRate values */
3233 #define TST_TXTEST_RATE_1MBPS 0
3234 #define TST_TXTEST_RATE_2MBPS 1
3235 #define TST_TXTEST_RATE_5_5MBPS 2
3236 #define TST_TXTEST_RATE_11MBPS 3
3237 #define TST_TXTEST_RATE_SHIFT 3
3238
3239 /*
3240 * MBSS shared memory address definitions; see MultiBSSUcode Twiki page
3241 * Local terminology:
3242 * addr is byte offset used by SW.
3243 * offset is word offset used by uCode.
3244 */
3245 #define SHM_MBSS_UCODE_BASE (0x320 * 2)
3246 #define SHM_MBSS_UCODE_AC_BASE (0x374 * 2)
3247
3248 #define SHM_MBSS_BASE_ADDR (wlc->shm_mbss_base)
3249 #define SHM_MBSS_WORD_OFFSET_TO_ADDR(n) (SHM_MBSS_BASE_ADDR + ((n) * 2))
3250
3251 #define SHM_MBSS_BSSID0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0)
3252 #define SHM_MBSS_BSSID1 SHM_MBSS_WORD_OFFSET_TO_ADDR(1)
3253 #define SHM_MBSS_BSSID2 SHM_MBSS_WORD_OFFSET_TO_ADDR(2)
3254 #define SHM_MBSS_BCN_COUNT SHM_MBSS_WORD_OFFSET_TO_ADDR(3)
3255 #define SHM_MBSS_PRQ_BASE SHM_MBSS_WORD_OFFSET_TO_ADDR(4)
3256 #define SHM_MBSS_BC_FID0 SHM_MBSS_WORD_OFFSET_TO_ADDR(5)
3257 #define SHM_MBSS_BC_FID1 SHM_MBSS_WORD_OFFSET_TO_ADDR(6)
3258 #define SHM_MBSS_BC_FID2 SHM_MBSS_WORD_OFFSET_TO_ADDR(7)
3259 #define SHM_MBSS_BC_FID3 SHM_MBSS_WORD_OFFSET_TO_ADDR(8)
3260 #define SHM_MBSS_PRE_TBTT SHM_MBSS_WORD_OFFSET_TO_ADDR(9)
3261
3262 /* SSID lengths are encoded, two at a time in 16-bits */
3263 #define SHM_MBSS_SSID_LEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(10)
3264 #define SHM_MBSS_SSID_LEN1 SHM_MBSS_WORD_OFFSET_TO_ADDR(11)
3265
3266 /* New for ucode template based mbss */
3267 #define SHM_MBSS_BSSID_NUM SHM_MBSS_WORD_OFFSET_TO_ADDR(12)
3268 #define SHM_MBSS_BC_BITMAP SHM_MBSS_WORD_OFFSET_TO_ADDR(13)
3269 #define SHM_MBSS_PRS_TPLPTR SHM_MBSS_WORD_OFFSET_TO_ADDR(14)
3270 #define SHM_MBSS_TIMPOS_INBCN SHM_MBSS_WORD_OFFSET_TO_ADDR(15)
3271
3272 /* Re-uses M_SSID */
3273 #define SHM_MBSS_BCNLEN0 M_SSID
3274 /* Re-uses part of extended SSID storage */
3275 #define SHM_MBSS_PRSLEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x10)
3276 #define SHM_MBSS_BCFID0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x20)
3277 #define SHM_MBSS_SSIDLEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x30)
3278 #define SHM_MBSS_LPRSLEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x38)
3279 #define SHM_MBSS_CLOSED_NET (0x80) /* indicates closed network */
3280
3281 /* set value for 16 mbss */
3282 #define SHM_MBSS_PRS_TPL0 (2 * 0x1034)
3283 #define SHM_MBSS_LPRS_TPL0 (2 * 0x2034)
3284
3285 /* SSID Search Engine entries */
3286 #define SHM_MBSS_SSIDSE_BASE_ADDR (0)
3287 #define SHM_MBSS_SSIDSE_BLKSZ (36)
3288 #define SHM_MBSS_SSIDLEN_BLKSZ (4)
3289 #define SHM_MBSS_SSID_BLKSZ (32)
3290
3291
3292 /* END New for ucode template based mbss */
3293
3294
3295 /* Uses uCode (HW) BSS config IDX */
3296 #define SHM_MBSS_SSID_ADDR(idx) \
3297 (((idx) == 0) ? M_SSID : SHM_MBSS_WORD_OFFSET_TO_ADDR(0x10 * (idx)))
3298
3299 /* Uses uCode (HW) BSS config IDX */
3300 #define SHM_MBSS_BC_FID_ADDR(ucidx) SHM_MBSS_WORD_OFFSET_TO_ADDR(5 + (ucidx))
3301 #define SHM_MBSS_BC_FID_ADDR16(ucidx) (SHM_MBSS_BCFID0 + (2 * ucidx))
3302
3303 /*
3304 * Definitions for PRQ fifo data as per MultiBSSUcode Twiki page
3305 */
3306
3307 #define SHM_MBSS_PRQ_ENTRY_BYTES 10 /* Size of each PRQ entry */
3308 #define SHM_MBSS_PRQ_ENTRY_COUNT 12 /* Number of PRQ entries */
3309 #define SHM_MBSS_PRQ_TOT_BYTES (SHM_MBSS_PRQ_ENTRY_BYTES * SHM_MBSS_PRQ_ENTRY_COUNT)
3310
3311 #define SHM_MBSS_PRQ_READ_PTR (0x5E * 2)
3312 #define SHM_MBSS_PRQ_WRITE_PTR (0x5F * 2)
3313
3314 typedef struct shm_mbss_prq_entry_s shm_mbss_prq_entry_t;
3315 BWL_PRE_PACKED_STRUCT struct shm_mbss_prq_entry_s {
3316 struct ether_addr ta;
3317 uint8 prq_info[2];
3318 uint16 time_stamp; /* 7:0 timestamp, 8 HT STA Indication, 15:9 Reserved */
3319 } BWL_POST_PACKED_STRUCT;
3320
3321 typedef enum shm_mbss_prq_ft_e {
3322 SHM_MBSS_PRQ_FT_CCK,
3323 SHM_MBSS_PRQ_FT_OFDM,
3324 SHM_MBSS_PRQ_FT_MIMO,
3325 SHM_MBSS_PRQ_FT_RESERVED
3326 } shm_mbss_prq_ft_t;
3327
3328 #define SHM_MBSS_PRQ_FT_COUNT SHM_MBSS_PRQ_FT_RESERVED
3329 #define SHM_MBSS_PRQ_ENT_FRAMETYPE(entry) ((entry)->prq_info[0] & 0x3)
3330 #define SHM_MBSS_PRQ_ENT_UPBAND(entry) ((((entry)->prq_info[0] >> 2) & 0x1) != 0)
3331
3332 /* What was the index matched? */
3333 #define SHM_MBSS_PRQ_ENT_UC_BSS_IDX(entry) (((entry)->prq_info[0] >> 2) & 0x3)
3334 #define SHM_MBSS_PRQ_ENT_PLCP0(entry) ((entry)->prq_info[1])
3335
3336 /* Was this directed to a specific SSID or BSSID? If bit clear, quantity known */
3337 #define SHM_MBSS_PRQ_ENT_DIR_SSID(entry) \
3338 ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 1)
3339 #define SHM_MBSS_PRQ_ENT_DIR_BSSID(entry) \
3340 ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 2)
3341
3342 /* Was the probe request from a ht STA or a legacy STA */
3343 #define SHM_MBSS_PRQ_ENT_HTSTA(entry) ((ltoh16((entry)->time_stamp) >> 8) & 0x1)
3344 #define SHM_MBSS_PRQ_ENT_TIMESTAMP(entry) (ltoh16((entry)->time_stamp) & 0xFF)
3345
3346 typedef struct d11ac_tso_s d11ac_tso_t;
3347
3348 BWL_PRE_PACKED_STRUCT struct d11ac_tso_s {
3349 uint8 flag[3];
3350 uint8 sfh_hdr_offset;
3351 uint16 tso_mss; /* tso segment size */
3352 uint16 msdu_siz; /* msdu size */
3353 uint32 tso_payload_siz; /* total byte cnt in tcp payload */
3354 uint16 ip_hdr_offset; /* relative to the start of txd header */
3355 uint16 tcp_hdr_offset; /* relative to start of txd header */
3356 } BWL_POST_PACKED_STRUCT;
3357
3358 #define TOE_F0_HDRSIZ_NORMAL (1 << 0)
3359 #define TOE_F0_PASSTHROUGH (1 << 1)
3360 #define TOE_F0_TCPSEG_EN (1 << 3)
3361 #define TOE_F0_IPV4 (1 << 4)
3362 #define TOE_F0_IPV6 (1 << 5)
3363 #define TOE_F0_TCP (1 << 6)
3364 #define TOE_F0_UDP (1 << 7)
3365
3366 #define TOE_F1_IPV4_CSUM_EN (1 << 0)
3367 #define TOE_F1_TCPUDP_CSUM_EN (1 << 1)
3368 #define TOE_F1_PSEUDO_CSUM_EN (1 << 2)
3369
3370 #define TOE_F2_TXD_HEAD_SHORT (1 << 0)
3371 #define TOE_F2_EPOCH (1 << 1)
3372 #define TOE_F2_AMSDU_AGGR_EN (1 << 4)
3373 #define TOE_F2_AMSDU_CSUM_EN (1 << 5)
3374 #define TOE_F2_AMSDU_FS_MID (1 << 6)
3375 #define TOE_F2_AMSDU_FS_LAST (1 << 7)
3376
3377 /* This marks the end of a packed structure section. */
3378 #include <packed_section_end.h>
3379
3380 #define SHM_BYT_CNT 0x2 /* IHR location */
3381 #define MAX_BYT_CNT 0x600 /* Maximum frame len */
3382
3383
3384 #define M_HOST_WOWLBM (0x06a * 2) /* Events to be set by driver */
3385 #define M_WAKEEVENT_IND (0x06b * 2) /* Event indication by ucode */
3386 #define M_WOWL_NOBCN (0x06c * 2) /* loss of bcn value */
3387
3388 #define M_TXPSP_CNT (0x7b * 2)
3389 #define M_PHYERR (0x7f * 2)
3390
3391 /* Beacon Aggregation Related definitions */
3392 #define SHM_BCN_AGG_MAX_BUFF_SIZE (0x27*2) /* Read/Write */
3393 #define SHM_BCN_AGG_CUR_BUFF_SIZE (0x48*2) /* Read only */
3394 #define SHM_BCN_AGG_STA_AID (0x62*2) /* Read/Write */
3395
3396 /* WOWL Template Regions */
3397 #define WOWL_NS_CHKSUM (0x57 * 2)
3398 #define WOWL_PSP_TPL_BASE (0x334 * 2)
3399 #define WOWL_GTK_MSG2 (0x434 * 2)
3400 #define WOWL_NS_OFFLOAD (0x634 * 2)
3401 #define T_KEEPALIVE_0 (0x6b4 * 2)
3402 #define T_KEEPALIVE_1 ((0x6b4 + 0x40) * 2)
3403 #define WOWL_ARP_OFFLOAD (0x734 * 2)
3404 #define WOWL_TX_FIFO_TXRAM_BASE (0x774 * 2)
3405
3406 /* template regions for 11ac */
3407 #define D11AC_WOWL_PSP_TPL_BASE (0x4c0 * 2)
3408 #define D11AC_WOWL_GTK_MSG2 (0x5c0 * 2) /* for core rev >= 42 */
3409 #define WOWL_NS_OFFLOAD_GE42 (0x7c0 * 2)
3410 #define T_KEEPALIVE_0_GE42 (0x840 * 2)
3411 #define T_KEEPALIVE_1_GE42 ((0x840 + 0x40) * 2)
3412 #define WOWL_ARP_OFFLOAD_GE42 (0x8c0 * 2)
3413 #define D11AC_WOWL_TX_FIFO_TXRAM_BASE (0x900 * 2) /* GTKM2 for core rev >= 42 */
3414
3415 /* Event definitions */
3416 #define WOWL_MAGIC (1 << 0) /* Wakeup on Magic packet */
3417 #define WOWL_NET (1 << 1) /* Wakeup on Netpattern */
3418 #define WOWL_DIS (1 << 2) /* Wakeup on loss-of-link due to Disassoc/Deauth */
3419 #define WOWL_RETR (1 << 3) /* Wakeup on retrograde TSF */
3420 #define WOWL_BCN (1 << 4) /* Wakeup on loss of beacon */
3421 #define WOWL_TST (1 << 5) /* Wakeup after test */
3422 #define WOWL_M1 (1 << 6) /* Wakeup after PTK refresh */
3423 #define WOWL_EAPID (1 << 7) /* Wakeup after receipt of EAP-Identity Req */
3424 #define WOWL_PME_GPIO (1 << 8) /* Wakeind via PME(0) or GPIO(1) */
3425 #define WOWL_NEEDTKIP1 (1 << 9) /* need tkip phase 1 key to be updated by the driver */
3426 #define WOWL_GTK_FAILURE (1 << 10) /* enable wakeup if GTK fails */
3427 #define WOWL_EXTMAGPAT (1 << 11) /* support extended magic packets */
3428 #define WOWL_ARPOFFLOAD (1 << 12) /* support ARP/NS offloading */
3429 #define WOWL_WPA2 (1 << 13) /* read protocol version for EAPOL frames */
3430 #define WOWL_KEYROT (1 << 14) /* If the bit is set, use key rotaton */
3431 #define WOWL_BCAST (1 << 15) /* If the bit is set, frm received was bcast frame */
3432
3433 #define MAXBCNLOSS (1 << 13) - 1 /* max 12-bit value for bcn loss */
3434
3435 /* Shared memory for magic pattern */
3436 /* for core rev < 40 */
3437 #define M_RXFRM_SRA0 (0x172 * 2) /* word 0 of the station's shifted MAC address */
3438 #define M_RXFRM_SRA1 (0x173 * 2) /* word 1 of the station's shifted MAC address */
3439 #define M_RXFRM_SRA2 (0x174 * 2) /* word 2 of the station's shifted MAC address */
3440 #define M_RXFRM_RA0 (0x175 * 2) /* word 0 of the station's MAC address */
3441 #define M_RXFRM_RA1 (0x176 * 2) /* word 1 of the station's MAC address */
3442 #define M_RXFRM_RA2 (0x177 * 2) /* word 2 of the station's MAC address */
3443 /* for core rev >= 42 */
3444 #define D11AC_M_RXFRM_SRA0 (0x254 * 2) /* word 0 of the station's shifted MAC address */
3445 #define D11AC_M_RXFRM_SRA1 (0x255 * 2) /* word 1 of the station's shifted MAC address */
3446 #define D11AC_M_RXFRM_SRA2 (0x256 * 2) /* word 2 of the station's shifted MAC address */
3447 #define D11AC_M_RXFRM_RA0 (0x257 * 2) /* word 0 of the station's MAC address */
3448 #define D11AC_M_RXFRM_RA1 (0x258 * 2) /* word 1 of the station's MAC address */
3449 #define D11AC_M_RXFRM_RA2 (0x259 * 2) /* word 2 of the station's MAC address */
3450
3451 /* Shared memory for net-pattern */
3452 #define M_NETPAT_NUM (0x3e * 2) /* #of netpatterns */
3453 #define D11AC_M_NETPAT_NUM (0x1af * 2) /* #of netpatterns for corerev >= 42 */
3454 #define M_NETPAT_BLK_PTR (0x3f * 2) /* address for location of pattern 1 */
3455
3456 /* UCODE shm view:
3457 * typedef struct {
3458 * uint16 offset; // byte offset
3459 * uint16 patternsize; // the length of value[.] in bytes
3460 * uchar bitmask[MAXPATTERNSIZE/8]; // 16 bytes, the effect length is (patternsize+7)/8
3461 * uchar value[MAXPATTERNSIZE]; // 128 bytes, the effect length is patternsize.
3462 * } netpattern_t;
3463 */
3464 #define NETPATTERNSIZE (148) /* 128 value + 16 mask + 4 offset + 4 patternsize */
3465 #define MAXPATTERNSIZE 128
3466 #define MAXMASKSIZE MAXPATTERNSIZE/8
3467
3468 /* Power-save related */
3469 #define M_AID_NBIT (0x068 * 2) /* The station's AID bit position in AP's TIM bitmap */
3470 /* The station's AID bit position in AP's TIM bitmap for core rev >=42 */
3471 #define D11AC_M_AID_NBIT (0x062 * 2)
3472 #define M_PSP_PCTLWD (0x02a * 2) /* PHYCTL word for the PS-Poll frame */
3473 #define M_PSP_PCT1LWD (0x058 * 2) /* PHYCTL_1 word for the PS-Poll frame */
3474
3475 /* Security Algorithm defines */
3476 #define TSCPN_BLK_SIZE 6 * 4 /* 6 bytes * 4 ACs */
3477 #define M_WOWL_SECKINDXALGO_BLK (0x0f4 * 2) /* Key index mapping */
3478 #define D11AC_M_WOWL_SECKINDXALGO_BLK (0x1b6 * 2) /* Key index mapping for corerev >= 42 */
3479 #define M_WOWL_TKIP_TSC_TTAK (0x0fa * 2) /* TTAK & MSB(32, TSC/PN) */
3480 /* TTAK & MSB(32, TSC/PN) for corerev >= 42 */
3481 #define D11AC_M_WOWL_TKIP_TSC_TTAK (0x18c * 2)
3482 #define M_WOWL_TSCPN_BLK (0x11e * 2) /* 0-5 per AC */
3483 #define D11AC_M_WOWL_TSCPN_BLK (0x200 * 2) /* 0-5 per AC for corerev >= 42 */
3484 #define M_WOWL_SECRXKEYS_PTR (0x02b * 2)
3485 #define M_WOWL_TKMICKEYS_PTR (0x059 * 2)
3486
3487 #define M_WOWL_SECSUITE (0x069 * 2) /* Security being used */
3488
3489 #define M_WOWL_GPIOSEL (0x058 * 2) /* GPIO Sel for 11AC Chips */
3490
3491 /* test mode -- wakeup the system after 'x' seconds */
3492 #define M_WOWL_TEST_CYCLE (0x06d * 2) /* Time to wakeup in seconds */
3493
3494 #define M_WOWL_WAKEUP_FRM (0x468 *2) /* Frame that woke us up */
3495
3496 /* Broadcast Key rotation related */
3497 #define M_GROUP_KEY_IDX (0x0af * 2) /* Last rotated key index */
3498 #define D11AC_M_GROUP_KEY_IDX (0x03f * 2) /* Last rotated key index for core rev >= 42 */
3499
3500 #define M_KEYRC_LAST (0x178 * 2) /* Last good key replay counter */
3501 /* Last good key replay counter for core rev >= 42 */
3502 #define D11AC_M_KEYRC_LAST (0x382 * 2)
3503
3504 /* for sync up b/w ARM and host */
3505 #define M_REPLCNT_BLK (0x3d4*2)
3506 #define M_SEQNUM_TID (M_REPLCNT_BLK + 0)
3507 #define M_REPCNT_TID (M_REPLCNT_BLK + 0x1*2)
3508 #define M_KCK (0x15a * 2) /* KCK */
3509 #define D11AC_M_KCK (0x23c * 2) /* KCK for core rev >= 42 */
3510
3511 #define M_KEK (0x16a * 2) /* KEK for WEP/TKIP */
3512 #define D11AC_M_KEK (0x24c * 2) /* KEK for WEP/TKIP for core rev >= 42 */
3513
3514 #define M_AESTABLES_PTR (0x06e * 2) /* Pointer to AES tables (see below) */
3515
3516 /* wowl Offload related addresses and offsets */
3517 #define M_WOWL_OFFLOAD_CTX (0x17c * 2) /* Tx descriptor for offloaded templates */
3518 /* Tx descriptor for offloaded templates for core rev >= 42 */
3519 #define D11AC_M_WOWL_OFFLOAD_CTX (0x386 * 2)
3520
3521 #define M_WOWL_OFFLOADCFG_PTR (0x66 * 2) /* ptr to wowl offload cfg block */
3522 #define D11AC_M_WOWL_OFFLOADCFG_PTR (0x4f * 2) /* ptr to wowl cfg block for cr>=42 */
3523 #define M_ARPRESP_BYTESZ_OFFSET 0 /* 2 bytes; ARP resp pkt size */
3524 #define M_NA_BYTESZ_0_OFFSET 2 /* 2 bytes ; NA pkt size */
3525 #define M_NA_BYTESZ_1_OFFSET 4 /* 2 bytes ; NA pkt size */
3526 #define M_KEEPALIVE_BYTESZ_0_OFFSET 6 /* 2 bytes; size of first keepalive */
3527 #define M_KEEPALIVE_BYTESZ_1_OFFSET 8 /* 2 bytes; size of second keepalive */
3528 #define M_NPAT_ARPIDX_OFFSET 10 /* 2 bytes; net pattern index of ARP */
3529 #define M_NPAT_NS0IDX_OFFSET 12 /* 2 bytes; net pattern index of NS 0 */
3530 #define M_NPAT_NS1IDX_OFFSET 14 /* 2 bytes; net pattern index of NS 1 */
3531 #define M_EXTWAKEPATTERN_0_OFFSET 16 /* 6 bytes; ext magic pattern */
3532 #define M_EXTWAKEPATTERN_U0_OFFSET 22 /* 8 bytes; unaligned ext magic pattern */
3533 #define M_KEEPALIVE_INTVL_0_OFFSET 30 /* 2 bytes; in no of beacon intervals */
3534 #define M_KEEPALIVE_INTVL_1_OFFSET 32 /* 2 bytes; in no of beacon intervals */
3535
3536
3537 #define EXPANDED_KEY_RNDS 10
3538 #define EXPANDED_KEY_LEN 176 /* the expanded key from KEK (4*11*4, 16-byte state, 11 rounds) */
3539
3540 /* Txcore Mask related parameters 5 locations (BPHY, OFDM, 1-streams ~ 3-Streams) for WOWL
3541 * The base address is different than normal ucode(offset is the same)
3542 * Refer to above M_COREMASK_BLK definition
3543 */
3544 /* corerev >= 26 and <= 29 */
3545 #define M_COREMASK_BLK_WOWL_L30 (0x298 * 2)
3546 #define M_COREMASK_BPHY_WOWL_L30 (M_COREMASK_BLK_WOWL_L30 + (0 * 2))
3547 #define M_COREMASK_OFDM_WOWL_L30 (M_COREMASK_BLK_WOWL_L30 + (1 * 2))
3548 #define M_COREMASK_MCS_WOWL_L30 (M_COREMASK_BLK_WOWL_L30 + (2 * 2))
3549 /* corerev > 29 && corerev < 40 */
3550 #define M_COREMASK_BLK_WOWL (0x7e8 *2)
3551 #define M_COREMASK_BPHY_WOWL (M_COREMASK_BLK_WOWL + (0 * 2))
3552 #define M_COREMASK_OFDM_WOWL (M_COREMASK_BLK_WOWL + (1 * 2))
3553 #define M_COREMASK_MCS_WOWL (M_COREMASK_BLK_WOWL + (2 * 2))
3554 /* corerev >= 42 */
3555 #define D11AC_M_COREMASK_BLK_WOWL (0x1b0*2)
3556 #define D11AC_M_COREMASK_BPHY_WOWL (D11AC_M_COREMASK_BLK_WOWL + (0 * 2))
3557 #define D11AC_M_COREMASK_OFDM_WOWL (D11AC_M_COREMASK_BLK_WOWL + (1 * 2))
3558 #define D11AC_M_COREMASK_MCS_WOWL (D11AC_M_COREMASK_BLK_WOWL + (2 * 2))
3559 #define D11AC_M_COREMASK_MCS_WOWL_1 (D11AC_M_COREMASK_BLK_WOWL + (3 * 2))
3560 #define D11AC_M_COREMASK_MCS_WOWL_2 (D11AC_M_COREMASK_BLK_WOWL + (4 * 2))
3561
3562 /* Organization of Template RAM is as follows
3563 * typedef struct {
3564 * uint8 AES_XTIME9DBE[1024];
3565 * uint8 AES_INVSBOX[256];
3566 * uint8 AES_KEYW[176];
3567 * } AES_TABLES_t;
3568 */
3569 /* See dot11_firmware/diag/wmac_tcl/wmac_762_wowl_gtk_aes: proc write_aes_tables,
3570 * for an example of writing those tables into the tx fifo buffer.
3571 */
3572
3573 typedef struct {
3574 uint16 MacTxControlLow; /* mac-tx-ctl-low word */
3575 uint16 MacTxControlHigh; /* mac-tx-ctl-high word */
3576 uint16 PhyTxControlWord; /* phy control word */
3577 uint16 PhyTxControlWord_1; /* extra phy control word for mimophy */
3578 union {
3579 uint16 XtraFrameTypes; /* frame type for RTS/FRAG fallback (used only for AES) */
3580 uint16 bssenc_pos; /* BssEnc includes key ID , for corerev >= 42 */
3581 } u1;
3582 uint8 plcp[6]; /* plcp of template */
3583
3584 /* For detailed definition of the above field,
3585 * please see the general description of the tx descriptor
3586 * at http://hwnbu-twiki.broadcom.com/bin/view/Mwgroup/TxDescriptor.
3587 */
3588
3589 uint16 mac_frmtype; /* MAC frame type for GTK MSG2, can be
3590 * dot11_data frame (0x2) or dot11_QoS_Data frame (0x22).
3591 */
3592 uint16 frm_bytesize; /* number of bytes in the template, it includes:
3593 * PLCP, MAC header, IV/EIV, the data payload
3594 * (eth-hdr and EAPOL-Key), TKIP MIC
3595 */
3596 uint16 payload_wordoffset; /* the word offset of the data payload */
3597
3598 uint16 seqnum; /* Sequence number for this frame */
3599 uint8 seciv[18]; /* 10-byte TTAK used for TKIP, 8-byte IV/EIV.
3600 * See <SecurityInitVector> in the general tx descriptor.
3601 */
3602 } wowl_templ_ctxt_t;
3603
3604 #define WOWL_TEMPL_CTXT_LEN 42 /* For making sure that no PADs are needed */
3605 #define WOWL_TEMPL_CTXT_FRMTYPE_DATA 0x2
3606 #define WOWL_TEMPL_CTXT_FRMTYPE_QOS 0x22
3607
3608 /* constant tables required for AES key unwrapping for key rotation */
3609 extern uint16 aes_invsbox[128];
3610 extern uint16 aes_xtime9dbe[512];
3611
3612 /* Common to ucode/hw agg : WLAMPDU_MAC not defined yet here */
3613 #if defined(WLAMPDU_UCODE) || defined(WLAMPDU_HW) || defined(WLAMPDU_AQM)
3614 #define M_TXMPDU_CNT (0x74 * 2) /* # of total MPDUs in AMPDUs tx'd */
3615 #define M_TXAMPDU_CNT (0x7d * 2) /* # of total AMPDUs tx'd */
3616 #define M_RXBA_CNT (0xaa * 2) /* # of rx'ed block acks */
3617 #endif /* defined(WLAMPDU_UCODE) || defined(WLAMPDU_HW) */
3618
3619 #ifdef WLAMPDU_UCODE
3620 /* ucode assisted AMPDU aggregation */
3621 /* ucode allocates a big block starting with 4 side channels, followed by 4 descriptor blocks */
3622 #define M_TXFS_PTR (M_PSM_SOFT_REGS + (0x69 * 2)) /* pointer to txfs block */
3623 #define TOT_TXFS_WSIZE 50 /* totally 50 entries */
3624 #define C_TXFSD_WOFFSET TOT_TXFS_WSIZE /* offset of M_TXFS_INTF_BLK in M_TXFS_BLK */
3625
3626 #define C_TXFSD_SIZE 10 /* Each descriptor is 10 bytes */
3627 #define C_TXFSD_STRT_POS(base, q) (base + (q * C_TXFSD_SIZE) + 0) /* start */
3628 #define C_TXFSD_END_POS(base, q) (base + (q * C_TXFSD_SIZE) + 2) /* end */
3629 #define C_TXFSD_WPTR_POS(base, q) (base + (q * C_TXFSD_SIZE) + 4) /* driver updates */
3630 #define C_TXFSD_RPTR_POS(base, q) (base + (q * C_TXFSD_SIZE) + 6) /* ucode updates */
3631 #define C_TXFSD_RNUM_POS(base, q) (base + (q * C_TXFSD_SIZE) + 8) /* For ucode debugging */
3632
3633 #define MPDU_LEN_SHIFT 0
3634 #define MPDU_LEN_MASK (0xfff << MPDU_LEN_SHIFT) /* Bits 0 - 11 */
3635 #define MPDU_EPOCH_SHIFT 14
3636 #define MPDU_EPOCH_MASK (0x1 << MPDU_EPOCH_SHIFT) /* Bit 14 */
3637 #define MPDU_DEBUG_SHIFT 15
3638 #define MPDU_DEBUG_MASK (0x1 << MPDU_DEBUG_SHIFT) /* Bit 15 */
3639 #endif /* WLAMPDU_UCODE */
3640
3641 #if defined(WLAMPDU_HW) || defined(WLAMPDU_AQM)
3642 #define AGGFIFO_CAP 64
3643 #define MPDU_LEN_SHIFT 0
3644 #define MPDU_LEN_MASK (0xfff << MPDU_LEN_SHIFT) /* Bits 0 - 11 */
3645 #define MPDU_EPOCH_HW_SHIFT 12
3646 #define MPDU_EPOCH_HW_MASK (0x1 << MPDU_EPOCH_HW_SHIFT) /* Bit 12 */
3647 #define MPDU_RSVD_SHIFT 13
3648 #define MPDU_RSVD_MASK (0x7 << MPDU_RSVD_SHIFT) /* Bit 13-15 */
3649 #define MPDU_FIFOSEL_SHIFT 16
3650 #define MPDU_FIFOSEL_MASK (0x3 << MPDU_FIFOSEL_SHIFT) /* Bit 16-17 */
3651
3652 /* # of bins for mpdu density histogram : this ony exists for 4331hw or aqm agg */
3653 #define C_MPDUDEN_NBINS 64
3654
3655 #define C_HWAGG_STATS_MPDU_WSZ (C_MPDUDEN_NBINS+2) /* comes first */
3656 #define C_HWAGG_STATS_TXMCS_WSZ 32
3657 #define C_HWAGG_STATS_WSZ (C_HWAGG_STATS_MPDU_WSZ + C_HWAGG_STATS_TXMCS_WSZ)
3658 #define C_HWAGG_RDEMP_WOFF C_MPDUDEN_NBINS
3659 #define C_HWAGG_NAMPDU_WOFF (C_MPDUDEN_NBINS + 1)
3660 #define C_MBURST_WOFF C_HWAGG_STATS_WSZ
3661 #define C_MBURST_NBINS 8
3662
3663 #define M_HWAGG_STATS_PTR (0x69 * 2) /* corerev < 40 hwagg */
3664 #define M_AMP_STATS_PTR (0x3d * 2) /* corerev >= 40 aqmagg */
3665 #define C_AGGSTOP_NBINS 8
3666 #define C_AMP_STATS_SIZE (C_MPDUDEN_NBINS + C_AGGSTOP_NBINS + C_MBURST_NBINS)
3667 #endif /* WLAMPDU_HW */
3668
3669 #define MAX_MPDU_SPACE (D11_TXH_LEN + 1538)
3670
3671 #define M_LCNPHY_BLK_PTR (0x3d * 2)
3672 #define M_LCNPHY_PABIAS_CCK_OFFSET 0
3673 #define M_LCNPHY_PABIAS_OFDM_OFFSET 1
3674
3675 #define M_EXTLNA_PWRSAVE (0x32 * 2) /* External LNA power control support */
3676 #define M_PHY_ANTDIV_REG_4314 (0xa94 * 2)
3677 #define M_PHY_ANTDIV_MASK_4314 (0xa95 * 2)
3678
3679 /* Bits in TXE_BMCCTL */
3680 #define BMCCTL_InitReq_SHIFT 0
3681 #define BMC_CTL_DONE (1 << BMCCTL_InitReq_SHIFT)
3682 #define BMCCTL_ResetStats_SHIFT 1
3683 #define BMCCTL_TxBufSize_SHIFT 2
3684 #define BMCCTL_Loopback_SHIFT 5
3685
3686 /* Bits in TXE_BMCDescrLen */
3687 #define BMCDescrLen_ShortLen_SHIFT 0
3688 #define BMCDescrLen_LongLen_SHIFT 8
3689
3690 /* Bits in TXE_BMCAllocCtl */
3691 #define BMCAllocCtl_AllocCount_SHIFT 0
3692 #define BMCAllocCtl_AllocThreshold_SHIFT 8
3693
3694 /* Bits in TXE_BMCCmd */
3695 #define BMCCmd_TIDSel_SHIFT 0
3696 #define BMCCmd_Enable_SHIFT 4
3697 #define BMCCmd_ReleasePreAlloc_SHIFT 5
3698 #define BMCCmd_ReleasePreAllocAll_SHIFT 6
3699 #define BMCCmd_UpdateBA_SHIFT 7
3700 #define BMCCmd_Consume_SHIFT 8
3701 #define BMCCmd_Aggregate_SHIFT 9
3702 #define BMCCmd_UpdateRetryCount_SHIFT 10
3703 #define BMCCmd_DisableTID_SHIFT 11
3704
3705 /* Bits in TXE_PsmMSDUAccess */
3706 #define PsmMSDUAccess_TIDSel_SHIFT 0
3707 #define PsmMSDUAccess_MSDUIdx_SHIFT 4
3708 #define PsmMSDUAccess_ReadBusy_SHIFT 14
3709 #define PsmMSDUAccess_WriteBusy_SHIFT 15
3710
3711 /* D11AC shm location changes */
3712 #define D11AC_T_NULL_TPL_BASE (0x16 * 2)
3713 #define D11AC_T_NULL_TPL_SIZE_BYTES (24)
3714 #define D11_T_BCN0_TPL_BASE T_BCN0_TPL_BASE
3715 #define D11AC_T_BCN0_TPL_BASE (0x100 * 2)
3716 #define D11_T_BCN1_TPL_BASE T_BCN1_TPL_BASE
3717 #define D11AC_T_BCN1_TPL_BASE (0x240 * 2)
3718
3719 #define D11_M_BCN_PCTLWD M_BCN_PCTLWD
3720 #define D11_M_BCN_PCT1WD M_BCN_PCTL1WD
3721
3722 /* To adjust BCN and PRS power */
3723 #define D11_M_LCNXN_BLK_PTR (M_PSM_SOFT_REGS +(71*2))
3724
3725 #define D11AC_BCN_TXPCTL0 (0x66 * 2)
3726 #define D11AC_BCN_TXPCTL1 (0x67 * 2)
3727 #define D11AC_BCN_TXPCTL2 (0x68 * 2)
3728
3729 #define D11_T_PRS_TPL_BASE T_PRS_TPL_BASE
3730 #define D11AC_T_PRS_TPL_BASE (0x380 * 2)
3731
3732 #define D11_M_RT_PRS_PLCP_POS M_RT_PRS_PLCP_POS
3733 #define D11_M_RT_PRS_DUR_POS M_RT_PRS_DUR_POS
3734 #define D11AC_M_RT_PRS_PLCP_POS 8
3735 #define D11AC_M_RT_PRS_DUR_POS 12
3736
3737 /* Field definitions for M_REV40_RT_TXPWROFF_POS */
3738 #define M_REV40_RT_HTTXPWR_OFFSET_MASK 0x01f8 /* bit 8:3 */
3739 #define M_REV40_RT_HTTXPWR_OFFSET_SHIFT 3
3740
3741 /* shm location for TXBF */
3742 #define M_BFI_BLK_PTR (0x58 * 2)
3743 #define M_BFI_BLK_SIZE 16
3744 #define M_BFI_COMM_OFFSET 112 /* start of info shared by all links */
3745 #define M_BFI_REFRESH_THR_OFFSET (M_BFI_COMM_OFFSET + 0)
3746 #define M_BFI_NDPA_TXLMT_OFFSET (M_BFI_COMM_OFFSET + 1)
3747 #define M_BFI_BFI_NRXC_OFFSET (M_BFI_COMM_OFFSET + 2)
3748 #define M_BFI_BFEADDR_OFFSET (M_BFI_COMM_OFFSET + 3)
3749 #define M_BFI_HTNDP2S_PHYCTL_OFFSET (M_BFI_COMM_OFFSET + 4)
3750 #define M_BFI_HTNDP2S_PLCP_OFFSET (M_BFI_COMM_OFFSET + 7)
3751 #define M_BFI_HTNDP3S_PHYCTL_OFFSET (M_BFI_COMM_OFFSET + 11)
3752 #define M_BFI_HTNDP3S_PLCP_OFFSET (M_BFI_COMM_OFFSET + 14)
3753
3754 #define M_BFI_VHTNDP2S_PHYCTL_OFFSET (M_BFI_COMM_OFFSET + 18)
3755 #define M_BFI_VHTNDP2S_PLCP_OFFSET (M_BFI_COMM_OFFSET + 21)
3756 #define M_BFI_VHTNDP3S_PHYCTL_OFFSET (M_BFI_COMM_OFFSET + 25)
3757 #define M_BFI_VHTNDP3S_PLCP_OFFSET (M_BFI_COMM_OFFSET + 28)
3758 #define M_BFI_MLBF_LUT (M_BFI_COMM_OFFSET + 32)
3759 #define M_BFI_BFERPT_BLK_OFFSET (M_BFI_COMM_OFFSET + 48)
3760 #define M_BFI_LAST (M_BFI_BFERPT_BLK_OFFSET + 34)
3761
3762 #define C_BFI_BFRIDX_POS 0
3763 #define C_BFI_NDPA_TST_POS 1
3764 #define C_BFI_NDPA_TXCNT_POS 2
3765 #define C_BFI_NDPA_SEQ_POS 3
3766 #define C_BFI_NDPA_TYPE_POS 4
3767 #define C_BFI_BFRCTL_POS 5
3768 #define C_BFI_BFR_CONFIG0_POS 6
3769 #define C_BFI_BFE_CONFIG0_POS 7
3770 #define C_BFI_BFE_MIMOCTL_POS 8
3771 #define C_BFI_BFE_BSSID0_POS 9
3772 #define C_BFI_BFE_BSSID1_POS 10
3773 #define C_BFI_BFE_BSSID2_POS 11
3774 #define C_BFI_BFMSTAT_POS 12
3775
3776 #define C_BFI_BFRCTL_POS_NSTS_SHIFT 0 /* 0: 2 stream; 1: 3 streams */
3777 #define C_BFI_BFRCTL_POS_NDP_TYPE_SHIFT 1 /* 0 HT NDP; 1 VHT NDP */
3778 #define C_BFI_BFRCTL_POS_MLBF_SHIFT 2 /* 1 enable MLBF */
3779
3780 /* dynamic rflo ucode WAR defines */
3781 #define UCODE_WAR_EN 1
3782 #define UCODE_WAR_DIS 0
3783 #define M_4324_RXTX_WAR_PTR 0x6c
3784 #define M_CHIP_CHECK 0
3785 #define M_TX_MODE_0xb0 1
3786 #define M_TX_MODE_0x14d 2
3787 #define M_TX_MODE_0xb1 3
3788 #define M_TX_MODE_0x14e 4
3789 #define M_TX_MODE_0xb4 5
3790 #define M_TX_MODE_0x151 6
3791 #define M_RX_MODE_0xb0 7
3792 #define M_RX_MODE_0x14d 8
3793 #define M_RX_MODE_0xb1 9
3794 #define M_RX_MODE_0x14e 10
3795 #define M_RX_MODE_0xb4 11
3796 #define M_RX_MODE_0x151 12
3797
3798 #define M_TXFL_BMAP (0x3f*2)
3799
3800 /* TIMBC offset value */
3801 #define M_TIMBC_OFFSET (M_PSM_SOFT_REGS + (0x65 * 2))
3802 #define M_TIMBC_OFFSET_PRE40 (M_PSM_SOFT_REGS + (0x3f * 2))
3803
3804 /* new interface block added for corerev >= 40 */
3805 /* elna bypas based on w1 OR RSSI */
3806 #define M_PHYREG_WRSSI (M_PSM_SOFT_REGS_EXT + 0)
3807 #define M_WRSSI_THR (M_PSM_SOFT_REGS_EXT + 0x2)
3808 #define M_HIRSSI_FLAG (M_PSM_SOFT_REGS_EXT + 0x4)
3809 #define M_HIRSSI_THR (M_PSM_SOFT_REGS_EXT + 0x6)
3810 #define M_RSVD_NOW (M_PSM_SOFT_REGS_EXT + 0x8) /* currently used for prs in driver */
3811 #define M_SECRSSI0_MIN (M_PSM_SOFT_REGS_EXT + 0xa) /* rx secondary rssi hi thresh */
3812 #define M_SECRSSI1_MIN (M_PSM_SOFT_REGS_EXT + 0xc) /* rx secondary rssi med thresh */
3813 #define M_RSPBW20_RSSI (M_PSM_SOFT_REGS_EXT + 0xe) /* rssi thresh for rspbw20 */
3814
3815 /* RFLDO ON setting */
3816 #define M_RFLDO_ON_L (0x17e * 2)
3817 #define M_RFLDO_ON_H (0x17f * 2)
3818
3819 #endif /* _D11_H */
Tomato firmware and modifications.