release/src-rt/cfe/cfe/arch/mips/board/p5064/include/i82371sb.h

   1 /*
   2  * i82371sb.h: Intel PCI to ISA bridge
   3  */
   4
   5 #define I82371_IDETIM           0x40
   6 #define I82371_IDETIM_IDEENA    0x8000
   7
   8 #define I82371_IORT_XBCS        0x4c
   9 #define  I82371_IORT_16BIT(x)    0x04+(((x)&3)<<0)
  10 #define  I82371_IORT_8BIT(x)     0x40+(((x)&7)<<3)
  11 #define  I82371_IORT_DMAAC       0x80
  12
  13 #define I82371_XBCS             0x4e
  14 #define  I82371_XBCS_RTCEN       0x0001
  15 #define  I82371_XBCS_KBDEN       0x0002
  16 #define  I82371_XBCS_BIOSWP      0x0004
  17 #define  I82371_XBCS_MOUSE       0x0010
  18 #define  I82371_XBCS_CPERR       0x0020
  19 #define  I82371_XBCS_LBIOS       0x0040
  20 #define  I82371_XBCS_XBIOS       0x0080
  21 #define  I82371_XBCS_APIC        0x0100
  22
  23 #define I82371_PIRQRCA          0x60
  24 #define I82371_PIRQRCB          0x61
  25 #define I82371_PIRQRCC          0x62
  26 #define I82371_PIRQRCD          0x63
  27 #define  I82371_PIRQRC(d)       (0x80 | (d & 0xf))
  28
  29 #define I82371_TOM              0x69
  30 #define  I82371_TOM_FWD_89       0x02
  31 #define  I82371_TOM_FWD_AB       0x04
  32 #define  I82371_TOM_FWD_LBIOS    0x08
  33 #define  I82371_TOM_TOM(mb)      (((mb)-1) << 4)
  34
  35 #define I82371_MSTAT            0x6a
  36 #define  I82371_MSTAT_ISADIV_3   0x0001
  37 #define  I82371_MSTAT_ISADIV_4   0x0000
  38 #define  I82371_MSTAT_USBE       0x0010
  39 #define  I82371_MSTAT_ESMIME     0x0040
  40 #define  I82371_MSTAT_NBRE       0x0080
  41 #define  I82371_MSTAT_SEDT       0x8000
  42
  43 #define I82371_MBIRQ0           0x70
  44
  45 #define I82371_MBDMA0           0x76
  46 #define I82371_MBDMA1           0x77
  47 #define  I82371_MBDMA_CHNL(x)   ((x) & 7)
  48 #define  I82371_MBDMA_FAST       0x80
  49
  50 #define I82371_PCSC             0x78
  51 #define  I82371_PCSC_AMASK       0xfffc
  52 #define  I82371_PCSC_SIZE_4      0x0000
  53 #define  I82371_PCSC_SIZE_8      0x0001
  54 #define  I82371_PCSC_DISABLED    0x0002
  55 #define  I82371_PCSC_SIZE_16     0x0003
  56
  57 #define I82371_APICBASE         0x80
  58
  59 #define I82371_DLC              0x82
  60 #define  I82371_DLC_DT           0x01 /* delayed transaction enb */
  61 #define  I82371_DLC_PR           0x02 /* passive release enb */
  62 #define  I82371_DLC_USBPR        0x04 /* USB passive release enb */
  63 #define  I82371_DLC_DTTE         0x08 /* SERR on delayed timeout */
  64
  65 #define I82371_SMICNTL          0xa0
  66 #define I82371_SMIEN            0xa2
  67
  68 #define I82371_SEE              0xa4
  69
  70 #define I82371_FTMR             0xa8
  71 #define I82371_SMIREQ           0xaa
  72
  73 #define I82371_CTLTMR           0xac
  74 #define I82371_CTHTMR           0xae