2 * HND SiliconBackplane Gigabit Ethernet core software interface
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: hndgige.c,v 1.11 2008-03-28 19:31:55 Exp $
32 * Setup the gige core.
33 * Resetting the core will lose all settings.
36 hndgige_init(si_t
*sih
, uint32 unit
, bool *rgmii
)
38 volatile pci_config_regs
*pci
;
39 sbgige_pcishim_t
*ocp
;
52 idx
= si_coreidx(sih
);
54 /* point to the gige core registers */
55 regs
= si_setcore(sih
, GIGETH_CORE_ID
, unit
);
60 pci
= &((sbgige_t
*)regs
)->pcicfg
;
61 ocp
= &((sbgige_t
*)regs
)->pcishim
;
62 sb
= &((sbgige_t
*)regs
)->sbconfig
;
64 /* Enable the core clock and memory access */
65 if (!si_iscoreup(sih
))
66 si_core_reset(sih
, 0, 0);
69 * Setup the 64K memory-mapped region base address through BAR0.
70 * Leave the other BAR values alone.
72 base
= si_addrspace(sih
, 1);
73 W_REG(osh
, &pci
->base
[0], base
);
74 W_REG(osh
, &pci
->base
[1], 0);
77 * Enable the PCI memory access anyway. Any PCI config commands
78 * issued before the core is enabled will go to the emulation
79 * only and will not go to the real PCI config registers.
81 OR_REG(osh
, &pci
->command
, 2);
84 * Enable the posted write flush scheme as follows:
86 * - Enable flush on any core register read
87 * - Enable timeout on the flush
88 * - Disable the interrupt mask when flushing
90 * This differs from the default setting only in that interrupts are
91 * not masked. Since posted writes are not flushed on interrupt, the
92 * driver must explicitly request a flush in its interrupt handling
93 * by reading a core register.
95 W_REG(osh
, &ocp
->FlushStatusControl
, 0x68);
98 * Determine whether the GbE is in GMII or RGMII mode. This is
99 * indicated in bit 16 of the SBTMStateHigh register, which is
100 * part of the core-specific flags field.
102 * For GMII, bypass the Rx/Tx DLLs, i.e. add no delay to RXC/GTXC
103 * within the core. For RGMII, do not bypass the DLLs, resulting
104 * in added delay for RXC/GTXC. The SBTMStateLow register contains
105 * the controls for doing this in the core-specific flags field:
107 * bit 24 - Enable DLL controls
108 * bit 20 - Bypass Rx DLL
109 * bit 19 - Bypass Tx DLL
111 statelow
= R_REG(osh
, &sb
->sbtmstatelow
); /* DLL controls */
112 statehigh
= R_REG(osh
, &sb
->sbtmstatehigh
); /* GMII/RGMII mode */
113 if ((statehigh
& (1 << 16)) != 0) /* RGMII */
115 statelow
&= ~(1 << 20); /* no Rx bypass (delay) */
116 statelow
&= ~(1 << 19); /* no Tx bypass (delay) */
121 statelow
|= (1 << 20); /* Rx bypass (no delay) */
122 statelow
|= (1 << 19); /* Tx bypass (no delay) */
125 statelow
|= (1 << 24); /* enable DLL controls */
126 W_REG(osh
, &sb
->sbtmstatelow
, statelow
);
128 si_setcoreidx(sih
, idx
);