release/src-rt/linux/linux-2.6/arch/mips/brcm-boards/bcm947xx/time.c

   1 /*
   2  * Copyright (C) 2008, Broadcom Corporation
   3  * All Rights Reserved.
   4  *
   5  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   6  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   7  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
   8  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
   9  *
  10  * $Id: time.c,v 1.9 2009/07/17 06:23:12 Exp $
  11  */
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/interrupt.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/io.h>
  20 #include <asm/time.h>
  21
  22 #include <typedefs.h>
  23 #include <osl.h>
  24 #include <bcmutils.h>
  25 #include <bcmnvram.h>
  26 #include <hndsoc.h>
  27 #include <sbchipc.h>
  28 #include <siutils.h>
  29 #include <hndmips.h>
  30 #include <mipsinc.h>
  31 #include <hndcpu.h>
  32 #include <bcmdevs.h>
  33
  34 /* Global SB handle */
  35 extern si_t *bcm947xx_sih;
  36 extern spinlock_t bcm947xx_sih_lock;
  37
  38 /* Convenience */
  39 #define sih bcm947xx_sih
  40 #define sih_lock bcm947xx_sih_lock
  41
  42 #define WATCHDOG_MIN    3000    /* milliseconds */
  43 extern int panic_timeout;
  44 extern int panic_on_oops;
  45 static int watchdog = 0;
  46 extern int bcm947xx_cpu_clk;
  47
  48 #ifndef CONFIG_HWSIM
  49 static u8 *mcr = NULL;
  50 #endif /* CONFIG_HWSIM */
  51
  52 void __init
  53 bcm947xx_time_init(void)
  54 {
  55         unsigned int hz;
  56         char cn[8];
  57
  58         /*
  59          * Use deterministic values for initial counter interrupt
  60          * so that calibrate delay avoids encountering a counter wrap.
  61          */
  62         write_c0_count(0);
  63         write_c0_compare(0xffff);
  64
  65         /* 5354 could run both on 200 & 240 Mhz -- use nvram setting */
  66         if (sih->chip == BCM5354_CHIP_ID && nvram_match("clkfreq", "200"))
  67                 hz = 200000000;
  68         else
  69         if (!(hz = si_cpu_clock(sih)))
  70                 hz = 100000000;
  71
  72         bcm_chipname(sih->chip, cn, 8);
  73         printk("CPU: BCM%s rev %d pkg %d at %d MHz\n", cn, sih->chiprev, sih->chippkg,
  74                (hz + 500000) / 1000000);
  75         bcm947xx_cpu_clk = (hz + 500000) / 1000000;
  76
  77         /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
  78         if (sih->chip == BCM5354_CHIP_ID &&
  79                 strncmp(nvram_safe_get("hardware_version"), "WL520G", 6) == 0)
  80                 mips_hpt_frequency = 100000000; // Fix WL520GUGC clock
  81         else
  82                 mips_hpt_frequency = hz / 2;
  83
  84         /* Set watchdog interval in ms */
  85         watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
  86
  87         /* Ensure at least WATCHDOG_MIN */
  88         if ((watchdog > 0) && (watchdog < WATCHDOG_MIN))
  89                 watchdog = WATCHDOG_MIN;
  90
  91         /* Set panic timeout in seconds */
  92         panic_timeout = watchdog / 1000;
  93         panic_on_oops = watchdog / 1000;
  94 }
  95
  96 #ifdef CONFIG_HND_BMIPS3300_PROF
  97 extern bool hndprofiling;
  98 #ifdef CONFIG_MIPS64
  99 typedef u_int64_t sbprof_pc;
 100 #else
 101 typedef u_int32_t sbprof_pc;
 102 #endif
 103 extern void sbprof_cpu_intr(sbprof_pc restartpc);
 104 #endif  /* CONFIG_HND_BMIPS3300_PROF */
 105
 106 static irqreturn_t
 107 bcm947xx_timer_interrupt(int irq, void *dev_id)
 108 {
 109 #ifdef CONFIG_HND_BMIPS3300_PROF
 110         /*
 111          * Are there any ExcCode or other mean(s) to determine what has caused
 112          * the timer interrupt? For now simply stop the normal timer proc if
 113          * count register is less than compare register.
 114          */
 115         if (hndprofiling) {
 116                 sbprof_cpu_intr(read_c0_epc() +
 117                                 ((read_c0_cause() >> (CAUSEB_BD - 2)) & 4));
 118                 if (read_c0_count() < read_c0_compare())
 119                         return (IRQ_HANDLED);
 120         }
 121 #endif  /* CONFIG_HND_BMIPS3300_PROF */
 122
 123         /* Generic MIPS timer code */
 124         timer_interrupt(irq, dev_id);
 125
 126         /* Set the watchdog timer to reset after the specified number of ms */
 127         if (watchdog > 0) {
 128                 if (((si_t *)sih)->chip == BCM5354_CHIP_ID)
 129                         si_watchdog(sih, WATCHDOG_CLOCK_5354 / 1000 * watchdog);
 130                 else
 131                         si_watchdog_ms(sih, watchdog);
 132         }
 133
 134 #ifdef  CONFIG_HWSIM
 135         (*((int *)0xa0000f1c))++;
 136 #else
 137         /* Blink one of the LEDs in the external UART */
 138         if (mcr && !(jiffies % (HZ/2)))
 139                 writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
 140 #endif
 141
 142         return (IRQ_HANDLED);
 143 }
 144
 145 static struct irqaction bcm947xx_timer_irqaction = {
 146         bcm947xx_timer_interrupt,
 147         IRQF_DISABLED,
 148         { { 0 } },
 149         "timer",
 150         NULL,
 151         NULL,
 152         0,
 153         NULL
 154 };
 155
 156 void __init
 157 plat_timer_setup(struct irqaction *irq)
 158 {
 159         /* Enable the timer interrupt */
 160         setup_irq(7, &bcm947xx_timer_irqaction);
 161 }
 162
 163 #define CFE_UPDATE 1            // added by Chen-I for mac/regulation update
 164
 165 #ifdef CFE_UPDATE
 166 void bcm947xx_watchdog_disable(void)
 167 {
 168         watchdog=0;
 169         si_watchdog(sih, 0);
 170 }
 171 #endif
 172