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1 /* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Wafer ID bit definitions File: sb1250_wid.h
5 *
6 * Some preproduction BCM1250 samples use the wafer ID (WID) bits
7 * in the system_revision register in the SCD to determine which
8 * portions of the L1 and L2 caches are usable.
9 *
10 * This file describes the WID register layout.
11 *
12 * Author: Mitch Lichtenberg (mpl@broadcom.com)
13 *
14 *********************************************************************
15 *
16 * Copyright 2000,2001,2002,2003
17 * Broadcom Corporation. All rights reserved.
18 *
19 * This software is furnished under license and may be used and
20 * copied only in accordance with the following terms and
21 * conditions. Subject to these conditions, you may download,
22 * copy, install, use, modify and distribute modified or unmodified
23 * copies of this software in source and/or binary form. No title
24 * or ownership is transferred hereby.
25 *
26 * 1) Any source code used, modified or distributed must reproduce
27 * and retain this copyright notice and list of conditions
28 * as they appear in the source file.
29 *
30 * 2) No right is granted to use any trade name, trademark, or
31 * logo of Broadcom Corporation. The "Broadcom Corporation"
32 * name may not be used to endorse or promote products derived
33 * from this software without the prior written permission of
34 * Broadcom Corporation.
35 *
36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
48 * THE POSSIBILITY OF SUCH DAMAGE.
49 ********************************************************************* */
52 #ifndef _SB1250_WID_H
53 #define _SB1250_WID_H
57 /*
58 * To make things easier to work with, we'll assume that the
59 * WID bits have been shifted from their normal home
60 * in scd_system_revision[63:32] to bits [31..0].
61 *
62 * That is, we've already shifted right by S_SYS_WID
63 */
65 #define S_WID_BIN 0
66 #define M_WID_BIN _SB_MAKEMASK(3,S_WID_BIN)
67 #define V_WID_BIN(x) _SB_MAKEVALUE(x,S_WID_BIN)
68 #define G_WID_BIN(x) _SB_GETVALUE(x,S_WID_BIN,M_WID_BIN)
70 /* CPUs L1I L1D L2 */
80 /*
81 * '1' bits in this mask represent bins with only one CPU
82 */
84 #define M_WID_BIN_1CPU (_SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
85 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
88 /*
89 * '1' bits in this mask represent bins with a good L2
90 */
92 #define M_WID_BIN_F2 (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
93 _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_F2) | \
94 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2))
96 /*
97 * '1' bits in this mask represent bins with 1/2 L2
98 */
100 #define M_WID_BIN_H2 (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_1D_H2) | \
101 _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
102 _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_H2) | \
103 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2) )
105 /*
106 * '1' bits in this mask represent bins with 1/4 L2
107 */
109 #define M_WID_BIN_Q2 (_SB_MAKEMASK1(K_WID_BIN_2CPU_1I_1D_Q2))
111 /*
112 * '1' bits in this mask represent bins with 3/4 L1
113 */
115 #define M_WID_BIN_3ID (_SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_F2) | \
116 _SB_MAKEMASK1(K_WID_BIN_2CPU_3I_3D_H2))
118 /*
119 * '1' bits in this mask represent bins with a full L1I
120 */
122 #define M_WID_BIN_FI (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_1D_H2) | \
123 _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
124 _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
125 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
126 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
128 /*
129 * '1' bits in this mask represent bins with a full L1D
130 */
132 #define M_WID_BIN_FD (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
133 _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
134 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
135 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
137 /*
138 * '1' bits in this mask represent bins with a full L1 (both I and D)
139 */
141 #define M_WID_BIN_FID (_SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_F2) | \
142 _SB_MAKEMASK1(K_WID_BIN_2CPU_FI_FD_H2) | \
143 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_F2) | \
144 _SB_MAKEMASK1(K_WID_BIN_1CPU_FI_FD_H2))
146 #define S_WID_L2QTR 3
147 #define M_WID_L2QTR _SB_MAKEMASK(2,S_WID_L2QTR)
148 #define V_WID_L2QTR(x) _SB_MAKEVALUE(x,S_WID_L2QTR)
149 #define G_WID_L2QTR(x) _SB_GETVALUE(x,S_WID_L2QTR,M_WID_L2QTR)
151 #define M_WID_L2HALF _SB_MAKEMASK1(4)
153 #define S_WID_CPU0_L1I 5
154 #define M_WID_CPU0_L1I _SB_MAKEMASK(2,S_WID_CPU0_L1I)
155 #define V_WID_CPU0_L1I(x) _SB_MAKEVALUE(x,S_WID_CPU0_L1I)
156 #define G_WID_CPU0_L1I(x) _SB_GETVALUE(x,S_WID_CPU0_L1I,M_WID_CPU0_L1I)
158 #define S_WID_CPU0_L1D 7
159 #define M_WID_CPU0_L1D _SB_MAKEMASK(2,S_WID_CPU0_L1D)
160 #define V_WID_CPU0_L1D(x) _SB_MAKEVALUE(x,S_WID_CPU0_L1D)
161 #define G_WID_CPU0_L1D(x) _SB_GETVALUE(x,S_WID_CPU0_L1D,M_WID_CPU0_L1D)
163 #define S_WID_CPU1_L1I 9
164 #define M_WID_CPU1_L1I _SB_MAKEMASK(2,S_WID_CPU1_L1I)
165 #define V_WID_CPU1_L1I(x) _SB_MAKEVALUE(x,S_WID_CPU1_L1I)
166 #define G_WID_CPU1_L1I(x) _SB_GETVALUE(x,S_WID_CPU1_L1I,M_WID_CPU1_L1I)
168 #define S_WID_CPU1_L1D 11
169 #define M_WID_CPU1_L1D _SB_MAKEMASK(2,S_WID_CPU1_L1D)
170 #define V_WID_CPU1_L1D(x) _SB_MAKEVALUE(x,S_WID_CPU1_L1D)
171 #define G_WID_CPU1_L1D(x) _SB_GETVALUE(x,S_WID_CPU1_L1D,M_WID_CPU1_L1D)
173 /*
174 * The macros below assume that the CPU bits have been shifted into the
175 * low-order 4 bits.
176 */
178 #define S_WID_CPUX_L1I 0
179 #define M_WID_CPUX_L1I _SB_MAKEMASK(2,S_WID_CPUX_L1I)
180 #define V_WID_CPUX_L1I(x) _SB_MAKEVALUE(x,S_WID_CPUX_L1I)
181 #define G_WID_CPUX_L1I(x) _SB_GETVALUE(x,S_WID_CPUX_L1I,M_WID_CPUX_L1I)
183 #define S_WID_CPUX_L1D 2
184 #define M_WID_CPUX_L1D _SB_MAKEMASK(2,S_WID_CPUX_L1D)
185 #define V_WID_CPUX_L1D(x) _SB_MAKEVALUE(x,S_WID_CPUX_L1D)
186 #define G_WID_CPUX_L1D(x) _SB_GETVALUE(x,S_WID_CPUX_L1D,M_WID_CPUX_L1D)
188 #define S_WID_CPU0 5
189 #define S_WID_CPU1 9
191 #define S_WID_WAFERID 13
192 #define M_WID_WAFERID _SB_MAKEMASK(5,S_WID_WAFERID)
193 #define V_WID_WAFERID(x) _SB_MAKEVALUE(x,S_WID_WAFERID)
194 #define G_WID_WAFERID(x) _SB_GETVALUE(x,S_WID_WAFERID,M_WID_WAFERID)
196 #define S_WID_LOTID 18
197 #define M_WID_LOTID _SB_MAKEMASK(14,S_WID_LOTID)
198 #define V_WID_LOTID(x) _SB_MAKEVALUE(x,S_WID_LOTID)
199 #define G_WID_LOTID(x) _SB_GETVALUE(x,S_WID_LOTID,M_WID_LOTID)
201 /*
202 * Now, to make things even more confusing, the fuses on the chip
203 * don't exactly correspond to the bits in the register. The mask
204 * below represents bits that need to be swapped with the ones to
205 * their left. So, if bit 10 is set, swap bits 10 and 11
206 */
208 #define M_WID_SWAPBITS (_SB_MAKEMASK1(2) | _SB_MAKEMASK1(4) | _SB_MAKEMASK1(10) | \
209 _SB_MAKEMASK1(20) | _SB_MAKEMASK1(18) | _SB_MAKEMASK1(26) )
211 #ifdef __ASSEMBLER__
212 #define WID_UNCONVOLUTE(wid,t1,t2,t3) \
213 li t1,M_WID_SWAPBITS ; \
214 and t1,t1,wid ; \
215 sll t1,t1,1 ; \
216 li t2,(M_WID_SWAPBITS << 1); \
217 and t2,t2,wid ; \
218 srl t2,t2,1 ; \
219 li t3, ~((M_WID_SWAPBITS | (M_WID_SWAPBITS << 1))) ; \
220 and wid,wid,t3 ; \
221 or wid,wid,t1 ; \
222 or wid,wid,t2
223 #else
224 #define WID_UNCONVOLUTE(wid) \
225 (((wid) & ~((M_WID_SWAPBITS | (M_WID_SWAPBITS << 1)))) | \
226 (((wid) & M_WID_SWAPBITS) << 1) | \
227 (((wid) & (M_WID_SWAPBITS<<1)) >> 1))
228 #endif
232 #endif