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Migrate UI cleanup phase 4 from MIPS into ARM
[tomato.git] / release / src-rt-6.x.4708 / include / sbchipc.h
blob81ae68d734d1a96647c91e44cd08f39e8c3b2189
1 /*
2 * SiliconBackplane Chipcommon core hardware definitions.
3 *
4 * The chipcommon core provides chip identification, SB control,
5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
6 * GPIO interface, extbus, and support for serial and parallel flashes.
7 *
8 * $Id: sbchipc.h 419467 2013-08-21 09:19:48Z $
9 *
10 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
11 *
12 * Permission to use, copy, modify, and/or distribute this software for any
13 * purpose with or without fee is hereby granted, provided that the above
14 * copyright notice and this permission notice appear in all copies.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 */
24
25 #ifndef _SBCHIPC_H
26 #define _SBCHIPC_H
27
28 #ifndef _LANGUAGE_ASSEMBLY
29
30 /* cpp contortions to concatenate w/arg prescan */
31 #ifndef PAD
32 #define _PADLINE(line) pad ## line
33 #define _XSTR(line) _PADLINE(line)
34 #define PAD _XSTR(__LINE__)
35 #endif /* PAD */
36
37 typedef struct eci_prerev35 {
38 uint32 eci_output;
39 uint32 eci_control;
40 uint32 eci_inputlo;
41 uint32 eci_inputmi;
42 uint32 eci_inputhi;
43 uint32 eci_inputintpolaritylo;
44 uint32 eci_inputintpolaritymi;
45 uint32 eci_inputintpolarityhi;
46 uint32 eci_intmasklo;
47 uint32 eci_intmaskmi;
48 uint32 eci_intmaskhi;
49 uint32 eci_eventlo;
50 uint32 eci_eventmi;
51 uint32 eci_eventhi;
52 uint32 eci_eventmasklo;
53 uint32 eci_eventmaskmi;
54 uint32 eci_eventmaskhi;
55 uint32 PAD[3];
56 } eci_prerev35_t;
57
58 typedef struct eci_rev35 {
59 uint32 eci_outputlo;
60 uint32 eci_outputhi;
61 uint32 eci_controllo;
62 uint32 eci_controlhi;
63 uint32 eci_inputlo;
64 uint32 eci_inputhi;
65 uint32 eci_inputintpolaritylo;
66 uint32 eci_inputintpolarityhi;
67 uint32 eci_intmasklo;
68 uint32 eci_intmaskhi;
69 uint32 eci_eventlo;
70 uint32 eci_eventhi;
71 uint32 eci_eventmasklo;
72 uint32 eci_eventmaskhi;
73 uint32 eci_auxtx;
74 uint32 eci_auxrx;
75 uint32 eci_datatag;
76 uint32 eci_uartescvalue;
77 uint32 eci_autobaudctr;
78 uint32 eci_uartfifolevel;
79 } eci_rev35_t;
80
81 typedef struct flash_config {
82 uint32 PAD[19];
83 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */
84 uint32 flashstrconfig;
85 } flash_config_t;
86
87 typedef volatile struct {
88 uint32 chipid; /* 0x0 */
89 uint32 capabilities;
90 uint32 corecontrol; /* corerev >= 1 */
91 uint32 bist;
92
93 /* OTP */
94 uint32 otpstatus; /* 0x10, corerev >= 10 */
95 uint32 otpcontrol;
96 uint32 otpprog;
97 uint32 otplayout; /* corerev >= 23 */
98
99 /* Interrupt control */
100 uint32 intstatus; /* 0x20 */
101 uint32 intmask;
102
103 /* Chip specific regs */
104 uint32 chipcontrol; /* 0x28, rev >= 11 */
105 uint32 chipstatus; /* 0x2c, rev >= 11 */
106
107 /* Jtag Master */
108 uint32 jtagcmd; /* 0x30, rev >= 10 */
109 uint32 jtagir;
110 uint32 jtagdr;
111 uint32 jtagctrl;
112
113 /* serial flash interface registers */
114 uint32 flashcontrol; /* 0x40 */
115 uint32 flashaddress;
116 uint32 flashdata;
117 uint32 otplayoutextension; /* rev >= 35 */
118
119 /* Silicon backplane configuration broadcast control */
120 uint32 broadcastaddress; /* 0x50 */
121 uint32 broadcastdata;
122
123 /* gpio - cleared only by power-on-reset */
124 uint32 gpiopullup; /* 0x58, corerev >= 20 */
125 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
126 uint32 gpioin; /* 0x60 */
127 uint32 gpioout; /* 0x64 */
128 uint32 gpioouten; /* 0x68 */
129 uint32 gpiocontrol; /* 0x6C */
130 uint32 gpiointpolarity; /* 0x70 */
131 uint32 gpiointmask; /* 0x74 */
132
133 /* GPIO events corerev >= 11 */
134 uint32 gpioevent;
135 uint32 gpioeventintmask;
136
137 /* Watchdog timer */
138 uint32 watchdog; /* 0x80 */
139
140 /* GPIO events corerev >= 11 */
141 uint32 gpioeventintpolarity;
142
143 /* GPIO based LED powersave registers corerev >= 16 */
144 uint32 gpiotimerval; /* 0x88 */
145 uint32 gpiotimeroutmask;
146
147 /* clock control */
148 uint32 clockcontrol_n; /* 0x90 */
149 uint32 clockcontrol_sb; /* aka m0 */
150 uint32 clockcontrol_pci; /* aka m1 */
151 uint32 clockcontrol_m2; /* mii/uart/mipsref */
152 uint32 clockcontrol_m3; /* cpu */
153 uint32 clkdiv; /* corerev >= 3 */
154 uint32 gpiodebugsel; /* corerev >= 28 */
155 uint32 capabilities_ext; /* 0xac */
156
157 /* pll delay registers (corerev >= 4) */
158 uint32 pll_on_delay; /* 0xb0 */
159 uint32 fref_sel_delay;
160 uint32 slow_clk_ctl; /* 5 < corerev < 10 */
161 uint32 PAD;
162
163 /* Instaclock registers (corerev >= 10) */
164 uint32 system_clk_ctl; /* 0xc0 */
165 uint32 clkstatestretch;
166 uint32 PAD[2];
167
168 /* Indirect backplane access (corerev >= 22) */
169 uint32 bp_addrlow; /* 0xd0 */
170 uint32 bp_addrhigh;
171 uint32 bp_data;
172 uint32 PAD;
173 uint32 bp_indaccess;
174 /* SPI registers, corerev >= 37 */
175 uint32 gsioctrl;
176 uint32 gsioaddress;
177 uint32 gsiodata;
178
179 /* More clock dividers (corerev >= 32) */
180 uint32 clkdiv2;
181 /* FAB ID (corerev >= 40) */
182 uint32 otpcontrol1;
183 uint32 fabid; /* 0xf8 */
184
185 /* In AI chips, pointer to erom */
186 uint32 eromptr; /* 0xfc */
187
188 /* ExtBus control registers (corerev >= 3) */
189 uint32 pcmcia_config; /* 0x100 */
190 uint32 pcmcia_memwait;
191 uint32 pcmcia_attrwait;
192 uint32 pcmcia_iowait;
193 uint32 ide_config;
194 uint32 ide_memwait;
195 uint32 ide_attrwait;
196 uint32 ide_iowait;
197 uint32 prog_config;
198 uint32 prog_waitcount;
199 uint32 flash_config;
200 uint32 flash_waitcount;
201 uint32 SECI_config; /* 0x130 SECI configuration */
202 uint32 SECI_status;
203 uint32 SECI_statusmask;
204 uint32 SECI_rxnibchanged;
205
206 union { /* 0x140 */
207 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
208 struct eci_prerev35 lt35;
209 struct eci_rev35 ge35;
210 /* Other interfaces */
211 struct flash_config flashconf;
212 uint32 PAD[20];
213 } eci;
214
215 /* SROM interface (corerev >= 32) */
216 uint32 sromcontrol; /* 0x190 */
217 uint32 sromaddress;
218 uint32 sromdata;
219 uint32 PAD[1]; /* 0x19C */
220 /* NAND flash registers for BCM4706 (corerev = 31) */
221 uint32 nflashctrl; /* 0x1a0 */
222 uint32 nflashconf;
223 uint32 nflashcoladdr;
224 uint32 nflashrowaddr;
225 uint32 nflashdata;
226 uint32 nflashwaitcnt0; /* 0x1b4 */
227 uint32 PAD[2];
228
229 uint32 seci_uart_data; /* 0x1C0 */
230 uint32 seci_uart_bauddiv;
231 uint32 seci_uart_fcr;
232 uint32 seci_uart_lcr;
233 uint32 seci_uart_mcr;
234 uint32 seci_uart_lsr;
235 uint32 seci_uart_msr;
236 uint32 seci_uart_baudadj;
237 /* Clock control and hardware workarounds (corerev >= 20) */
238 uint32 clk_ctl_st; /* 0x1e0 */
239 uint32 hw_war;
240 uint32 PAD[70];
241
242 /* UARTs */
243 uint8 uart0data; /* 0x300 */
244 uint8 uart0imr;
245 uint8 uart0fcr;
246 uint8 uart0lcr;
247 uint8 uart0mcr;
248 uint8 uart0lsr;
249 uint8 uart0msr;
250 uint8 uart0scratch;
251 uint8 PAD[248]; /* corerev >= 1 */
252
253 uint8 uart1data; /* 0x400 */
254 uint8 uart1imr;
255 uint8 uart1fcr;
256 uint8 uart1lcr;
257 uint8 uart1mcr;
258 uint8 uart1lsr;
259 uint8 uart1msr;
260 uint8 uart1scratch;
261 uint32 PAD[126];
262
263 /* PMU registers (corerev >= 20) */
264 /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP.
265 * The CPU must read them twice, compare, and retry if different.
266 */
267 uint32 pmucontrol; /* 0x600 */
268 uint32 pmucapabilities;
269 uint32 pmustatus;
270 uint32 res_state;
271 uint32 res_pending;
272 uint32 pmutimer;
273 uint32 min_res_mask;
274 uint32 max_res_mask;
275 uint32 res_table_sel;
276 uint32 res_dep_mask;
277 uint32 res_updn_timer;
278 uint32 res_timer;
279 uint32 clkstretch;
280 uint32 pmuwatchdog;
281 uint32 gpiosel; /* 0x638, rev >= 1 */
282 uint32 gpioenable; /* 0x63c, rev >= 1 */
283 uint32 res_req_timer_sel;
284 uint32 res_req_timer;
285 uint32 res_req_mask;
286 uint32 PAD;
287 uint32 chipcontrol_addr; /* 0x650 */
288 uint32 chipcontrol_data; /* 0x654 */
289 uint32 regcontrol_addr;
290 uint32 regcontrol_data;
291 uint32 pllcontrol_addr;
292 uint32 pllcontrol_data;
293 uint32 pmustrapopt; /* 0x668, corerev >= 28 */
294 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
295 uint32 PAD[100];
296 uint16 sromotp[512]; /* 0x800 */
297 #ifdef NFLASH_SUPPORT
298 /* Nand flash MLC controller registers (corerev >= 38) */
299 uint32 nand_revision; /* 0xC00 */
300 uint32 nand_cmd_start;
301 uint32 nand_cmd_addr_x;
302 uint32 nand_cmd_addr;
303 uint32 nand_cmd_end_addr;
304 uint32 nand_cs_nand_select;
305 uint32 nand_cs_nand_xor;
306 uint32 PAD;
307 uint32 nand_spare_rd0;
308 uint32 nand_spare_rd4;
309 uint32 nand_spare_rd8;
310 uint32 nand_spare_rd12;
311 uint32 nand_spare_wr0;
312 uint32 nand_spare_wr4;
313 uint32 nand_spare_wr8;
314 uint32 nand_spare_wr12;
315 uint32 nand_acc_control;
316 uint32 PAD;
317 uint32 nand_config;
318 uint32 PAD;
319 uint32 nand_timing_1;
320 uint32 nand_timing_2;
321 uint32 nand_semaphore;
322 uint32 PAD;
323 uint32 nand_devid;
324 uint32 nand_devid_x;
325 uint32 nand_block_lock_status;
326 uint32 nand_intfc_status;
327 uint32 nand_ecc_corr_addr_x;
328 uint32 nand_ecc_corr_addr;
329 uint32 nand_ecc_unc_addr_x;
330 uint32 nand_ecc_unc_addr;
331 uint32 nand_read_error_count;
332 uint32 nand_corr_stat_threshold;
333 uint32 PAD[2];
334 uint32 nand_read_addr_x;
335 uint32 nand_read_addr;
336 uint32 nand_page_program_addr_x;
337 uint32 nand_page_program_addr;
338 uint32 nand_copy_back_addr_x;
339 uint32 nand_copy_back_addr;
340 uint32 nand_block_erase_addr_x;
341 uint32 nand_block_erase_addr;
342 uint32 nand_inv_read_addr_x;
343 uint32 nand_inv_read_addr;
344 uint32 PAD[2];
345 uint32 nand_blk_wr_protect;
346 uint32 PAD[3];
347 uint32 nand_acc_control_cs1;
348 uint32 nand_config_cs1;
349 uint32 nand_timing_1_cs1;
350 uint32 nand_timing_2_cs1;
351 uint32 PAD[20];
352 uint32 nand_spare_rd16;
353 uint32 nand_spare_rd20;
354 uint32 nand_spare_rd24;
355 uint32 nand_spare_rd28;
356 uint32 nand_cache_addr;
357 uint32 nand_cache_data;
358 uint32 nand_ctrl_config;
359 uint32 nand_ctrl_status;
360 #endif /* NFLASH_SUPPORT */
361 uint32 gci_corecaps0; /* GCI starting at 0xC00 */
362 uint32 gci_corecaps1;
363 uint32 gci_corecaps2;
364 uint32 gci_corectrl;
365 uint32 gci_corestat; /* 0xC10 */
366 uint32 gci_intstat; /* 0xC14 */
367 uint32 gci_intmask; /* 0xC18 */
368 uint32 gci_wakemask; /* 0xC1C */
369 uint32 gci_levelintstat; /* 0xC20 */
370 uint32 gci_eventintstat; /* 0xC24 */
371 uint32 PAD[6];
372 uint32 gci_indirect_addr; /* 0xC40 */
373 uint32 gci_gpioctl; /* 0xC44 */
374 uint32 PAD;
375 uint32 gci_gpiomask; /* 0xC4C */
376 uint32 PAD;
377 uint32 gci_miscctl; /* 0xC54 */
378 uint32 PAD[2];
379 uint32 gci_input[32]; /* C60 */
380 uint32 gci_event[32]; /* CE0 */
381 uint32 gci_output[4]; /* D60 */
382 uint32 gci_control_0; /* 0xD70 */
383 uint32 gci_control_1; /* 0xD74 */
384 uint32 gci_level_polreg; /* 0xD78 */
385 uint32 gci_levelintmask; /* 0xD7C */
386 uint32 gci_eventintmask; /* 0xD80 */
387 uint32 PAD[3];
388 uint32 gci_inbandlevelintmask; /* 0xD90 */
389 uint32 gci_inbandeventintmask; /* 0xD94 */
390 uint32 PAD[2];
391 uint32 gci_seciauxtx; /* 0xDA0 */
392 uint32 gci_seciauxrx; /* 0xDA4 */
393 uint32 gci_secitx_datatag; /* 0xDA8 */
394 uint32 gci_secirx_datatag; /* 0xDAC */
395 uint32 gci_secitx_datamask; /* 0xDB0 */
396 uint32 gci_seciusef0tx_reg; /* 0xDB4 */
397 uint32 gci_secif0tx_offset; /* 0xDB8 */
398 uint32 gci_secif0rx_offset; /* 0xDBC */
399 uint32 gci_secif1tx_offset; /* 0xDC0 */
400 uint32 PAD[3];
401 uint32 gci_uartescval; /* DD0 */
402 uint32 PAD[3];
403 uint32 gci_secibauddiv; /* DE0 */
404 uint32 gci_secifcr; /* DE4 */
405 uint32 gci_secilcr; /* DE8 */
406 uint32 gci_secimcr; /* DEC */
407 uint32 PAD[2];
408 uint32 gci_baudadj; /* DF8 */
409 uint32 PAD;
410 uint32 gci_chipctrl; /* 0xE00 */
411 uint32 gci_chipsts; /* 0xE04 */
412 } chipcregs_t;
413
414 #endif /* _LANGUAGE_ASSEMBLY */
415
416 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
417 /* Selective swapped defines for those registers we need in
418 * big-endian code.
419 */
420 #define CC_CHIPID 4
421 #define CC_CAPABILITIES 0
422 #define CC_CHIPST 0x28
423 #define CC_EROMPTR 0xf8
424
425 #else /* !IL_BIGENDIAN || !BCMHND74K */
426
427 #define CC_CHIPID 0
428 #define CC_CAPABILITIES 4
429 #define CC_CHIPST 0x2c
430 #define CC_EROMPTR 0xfc
431
432 #endif /* IL_BIGENDIAN && BCMHND74K */
433
434 #define CC_OTPST 0x10
435 #define CC_JTAGCMD 0x30
436 #define CC_JTAGIR 0x34
437 #define CC_JTAGDR 0x38
438 #define CC_JTAGCTRL 0x3c
439 #define CC_GPIOPU 0x58
440 #define CC_GPIOPD 0x5c
441 #define CC_GPIOIN 0x60
442 #define CC_GPIOOUT 0x64
443 #define CC_GPIOOUTEN 0x68
444 #define CC_GPIOCTRL 0x6c
445 #define CC_GPIOPOL 0x70
446 #define CC_GPIOINTM 0x74
447 #define CC_WATCHDOG 0x80
448 #define CC_CLKC_N 0x90
449 #define CC_CLKC_M0 0x94
450 #define CC_CLKC_M1 0x98
451 #define CC_CLKC_M2 0x9c
452 #define CC_CLKC_M3 0xa0
453 #define CC_CLKDIV 0xa4
454 #define CC_SYS_CLK_CTL 0xc0
455 #define CC_CLK_CTL_ST SI_CLK_CTL_ST
456 #define PMU_CTL 0x600
457 #define PMU_CAP 0x604
458 #define PMU_ST 0x608
459 #define PMU_RES_STATE 0x60c
460 #define PMU_TIMER 0x614
461 #define PMU_MIN_RES_MASK 0x618
462 #define PMU_MAX_RES_MASK 0x61c
463 #define CC_CHIPCTL_ADDR 0x650
464 #define CC_CHIPCTL_DATA 0x654
465 #define PMU_REG_CONTROL_ADDR 0x658
466 #define PMU_REG_CONTROL_DATA 0x65C
467 #define PMU_PLL_CONTROL_ADDR 0x660
468 #define PMU_PLL_CONTROL_DATA 0x664
469 #define CC_SROM_CTRL 0x190
470 #define CC_SROM_OTP 0x800 /* SROM/OTP address space */
471 #define CC_GCI_INDIRECT_ADDR_REG 0xC40
472 #define CC_GCI_CHIP_CTRL_REG 0xE00
473 #define CC_GCI_CC_OFFSET_2 2
474 #define CC_GCI_CC_OFFSET_5 5
475
476 #define CHIPCTRLREG0 0x0
477 #define CHIPCTRLREG1 0x1
478 #define CHIPCTRLREG2 0x2
479 #define CHIPCTRLREG3 0x3
480 #define CHIPCTRLREG4 0x4
481 #define CHIPCTRLREG5 0x5
482 #define CHIPCTRLREG6 0x6
483 #define REGCTRLREG4 0x4
484 #define REGCTRLREG5 0x5
485 #define REGCTRLREG6 0x6
486 #define MINRESMASKREG 0x618
487 #define MAXRESMASKREG 0x61c
488 #define CHIPCTRLADDR 0x650
489 #define CHIPCTRLDATA 0x654
490 #define RSRCTABLEADDR 0x620
491 #define RSRCUPDWNTIME 0x628
492 #define PMUREG_RESREQ_MASK 0x68c
493 #define EXT_LPO_AVAIL 0x100
494 #define LPO_SEL 0x0
495 #define CC_EXT_LPO_PU 0x200000
496 #define GC_EXT_LPO_PU 0x2
497 #define CC_INT_LPO_PU 0x100000
498 #define GC_INT_LPO_PU 0x1
499 #define EXT_LPO_SEL 0x8
500 #define INT_LPO_SEL 0x4
501 #define ENABLE_FINE_CBUCK_CTRL (1 << 30)
502 #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000
503 #define REGCTRL5_PWM_AUTO_CTRL_SHIFT 17
504 #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000
505 #define REGCTRL6_PWM_AUTO_CTRL_SHIFT 16
506
507 #ifdef NFLASH_SUPPORT
508 /* NAND flash support */
509 #define CC_NAND_REVISION 0xC00
510 #define CC_NAND_CMD_START 0xC04
511 #define CC_NAND_CMD_ADDR 0xC0C
512 #define CC_NAND_SPARE_RD_0 0xC20
513 #define CC_NAND_SPARE_RD_4 0xC24
514 #define CC_NAND_SPARE_RD_8 0xC28
515 #define CC_NAND_SPARE_RD_C 0xC2C
516 #define CC_NAND_CONFIG 0xC48
517 #define CC_NAND_DEVID 0xC60
518 #define CC_NAND_DEVID_EXT 0xC64
519 #define CC_NAND_INTFC_STATUS 0xC6C
520 #endif /* NFLASH_SUPPORT */
521
522 /* chipid */
523 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */
524 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
525 #define CID_REV_SHIFT 16 /* Chip Revision shift */
526 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */
527 #define CID_PKG_SHIFT 20 /* Package Option shift */
528 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
529 #define CID_CC_SHIFT 24
530 #define CID_TYPE_MASK 0xf0000000 /* Chip Type */
531 #define CID_TYPE_SHIFT 28
532
533 /* capabilities */
534 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
535 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
536 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
537 #define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
538 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
539 #define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
540 #define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
541 #define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
542 #define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
543 #define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
544 #define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
545 #define CC_CAP_PWR_CTL 0x00040000 /* Power control */
546 #define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
547 #define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
548 #define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
549 #define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
550 #define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
551 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
552 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
553 #define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
554 #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
555 #define CC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */
556
557 #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
558 #define CC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */
559
560 /* capabilities extension */
561 #define CC_CAP_EXT_SECI_PRESENT 0x00000001 /* SECI present */
562 #define CC_CAP_EXT_GCI_PRESENT 0x00000004 /* GCI present */
563
564 #define GCI_WL_CHN_INFO_MASK (0xFF00)
565 #define GCI_WL_BANDWIDTH_OFFSET 41
566 #define GCI_WL_BANDWIDTH_MASK (0x7)
567
568 /* PLL type */
569 #define PLL_NONE 0x00000000
570 #define PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */
571 #define PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */
572 #define PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */
573 #define PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */
574 #define PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */
575 #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
576 #define PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */
577
578 /* ILP clock */
579 #define ILP_CLOCK 32000
580
581 /* ALP clock on pre-PMU chips */
582 #define ALP_CLOCK 20000000
583
584 #ifdef CFG_SIM
585 #define NS_ALP_CLOCK 84922
586 #define NS_SLOW_ALP_CLOCK 84922
587 #define NS_CPU_CLOCK 534500
588 #define NS_SLOW_CPU_CLOCK 534500
589 #define NS_SI_CLOCK 271750
590 #define NS_SLOW_SI_CLOCK 271750
591 #define NS_FAST_MEM_CLOCK 271750
592 #define NS_MEM_CLOCK 271750
593 #define NS_SLOW_MEM_CLOCK 271750
594 #else
595 #define NS_ALP_CLOCK 125000000
596 #define NS_SLOW_ALP_CLOCK 100000000
597 #define NS_CPU_CLOCK 1000000000
598 #define NS_SLOW_CPU_CLOCK 800000000
599 #define NS_SI_CLOCK 250000000
600 #define NS_SLOW_SI_CLOCK 200000000
601 #define NS_FAST_MEM_CLOCK 800000000
602 #define NS_MEM_CLOCK 533000000
603 #define NS_SLOW_MEM_CLOCK 400000000
604 #endif /* CFG_SIM */
605
606 /* HT clock */
607 #define HT_CLOCK 80000000
608
609 /* corecontrol */
610 #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
611 #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
612 #define CC_ASYNCGPIO 0x00000004 /* 1=generate GPIO interrupt without backplane clock */
613 #define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
614
615 /* 4321 chipcontrol */
616 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
617 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
618 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */
619
620 /* Fields in the otpstatus register in rev >= 21 */
621 #define OTPS_OL_MASK 0x000000ff
622 #define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
623 #define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
624 #define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
625 #define OTPS_OL_GU 0x00000008 /* general use region is locked */
626 #define OTPS_GUP_MASK 0x00000f00
627 #define OTPS_GUP_SHIFT 8
628 #define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
629 #define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
630 #define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
631 #define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
632 #define OTPS_READY 0x00001000
633 #define OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */
634 #define OTPS_RV_MASK 0x0fff0000
635 #define OTPS_PROGOK 0x40000000
636
637 /* Fields in the otpcontrol register in rev >= 21 */
638 #define OTPC_PROGSEL 0x00000001
639 #define OTPC_PCOUNT_MASK 0x0000000e
640 #define OTPC_PCOUNT_SHIFT 1
641 #define OTPC_VSEL_MASK 0x000000f0
642 #define OTPC_VSEL_SHIFT 4
643 #define OTPC_TMM_MASK 0x00000700
644 #define OTPC_TMM_SHIFT 8
645 #define OTPC_ODM 0x00000800
646 #define OTPC_PROGEN 0x80000000
647
648 /* Fields in the 40nm otpcontrol register in rev >= 40 */
649 #define OTPC_40NM_PROGSEL_SHIFT 0
650 #define OTPC_40NM_PCOUNT_SHIFT 1
651 #define OTPC_40NM_PCOUNT_WR 0xA
652 #define OTPC_40NM_PCOUNT_V1X 0xB
653 #define OTPC_40NM_REGCSEL_SHIFT 5
654 #define OTPC_40NM_REGCSEL_DEF 0x4
655 #define OTPC_40NM_PROGIN_SHIFT 8
656 #define OTPC_40NM_R2X_SHIFT 10
657 #define OTPC_40NM_ODM_SHIFT 11
658 #define OTPC_40NM_DF_SHIFT 15
659 #define OTPC_40NM_VSEL_SHIFT 16
660 #define OTPC_40NM_VSEL_WR 0xA
661 #define OTPC_40NM_VSEL_V1X 0xA
662 #define OTPC_40NM_VSEL_R1X 0x5
663 #define OTPC_40NM_COFAIL_SHIFT 30
664
665 #define OTPC1_CPCSEL_SHIFT 0
666 #define OTPC1_CPCSEL_DEF 6
667 #define OTPC1_TM_SHIFT 8
668 #define OTPC1_TM_WR 0x84
669 #define OTPC1_TM_V1X 0x84
670 #define OTPC1_TM_R1X 0x4
671
672 /* Fields in otpprog in rev >= 21 and HND OTP */
673 #define OTPP_COL_MASK 0x000000ff
674 #define OTPP_COL_SHIFT 0
675 #define OTPP_ROW_MASK 0x0000ff00
676 #define OTPP_ROW_SHIFT 8
677 #define OTPP_OC_MASK 0x0f000000
678 #define OTPP_OC_SHIFT 24
679 #define OTPP_READERR 0x10000000
680 #define OTPP_VALUE_MASK 0x20000000
681 #define OTPP_VALUE_SHIFT 29
682 #define OTPP_START_BUSY 0x80000000
683 #define OTPP_READ 0x40000000 /* HND OTP */
684
685 /* Fields in otplayout register */
686 #define OTPL_HWRGN_OFF_MASK 0x00000FFF
687 #define OTPL_HWRGN_OFF_SHIFT 0
688 #define OTPL_WRAP_REVID_MASK 0x00F80000
689 #define OTPL_WRAP_REVID_SHIFT 19
690 #define OTPL_WRAP_TYPE_MASK 0x00070000
691 #define OTPL_WRAP_TYPE_SHIFT 16
692 #define OTPL_WRAP_TYPE_65NM 0
693 #define OTPL_WRAP_TYPE_40NM 1
694 #define OTPL_ROW_SIZE_MASK 0x70000000
695 #define OTPL_ROW_SIZE_SHIFT 28
696
697 /* otplayout reg corerev >= 36 */
698 #define OTP_CISFORMAT_NEW 0x80000000
699
700 /* Opcodes for OTPP_OC field */
701 #define OTPPOC_READ 0
702 #define OTPPOC_BIT_PROG 1
703 #define OTPPOC_VERIFY 3
704 #define OTPPOC_INIT 4
705 #define OTPPOC_SET 5
706 #define OTPPOC_RESET 6
707 #define OTPPOC_OCST 7
708 #define OTPPOC_ROW_LOCK 8
709 #define OTPPOC_PRESCN_TEST 9
710
711 /* Opcodes for OTPP_OC field (40NM) */
712 #define OTPPOC_READ_40NM 0
713 #define OTPPOC_PROG_ENABLE_40NM 1
714 #define OTPPOC_PROG_DISABLE_40NM 2
715 #define OTPPOC_VERIFY_40NM 3
716 #define OTPPOC_WORD_VERIFY_1_40NM 4
717 #define OTPPOC_ROW_LOCK_40NM 5
718 #define OTPPOC_STBY_40NM 6
719 #define OTPPOC_WAKEUP_40NM 7
720 #define OTPPOC_WORD_VERIFY_0_40NM 8
721 #define OTPPOC_PRESCN_TEST_40NM 9
722 #define OTPPOC_BIT_PROG_40NM 10
723 #define OTPPOC_WORDPROG_40NM 11
724 #define OTPPOC_BURNIN_40NM 12
725 #define OTPPOC_AUTORELOAD_40NM 13
726 #define OTPPOC_OVST_READ_40NM 14
727 #define OTPPOC_OVST_PROG_40NM 15
728
729 /* Fields in otplayoutextension */
730 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF
731 #define OTPLAYOUTEXT_AUTOLOAD_PRESENT_MASK 0x00001000
732 #define OTPLAYOUTEXT_AUTOLOAD_PRESENT_SHIFT 12
733 #define OTPLAYOUTEXT_NUM_AUTOLOAD_MASK 0x0003E000
734 #define OTPLAYOUTEXT_NUM_AUTOLOAD_SHIFT 13
735 #define OTPLAYOUTEXT_AUTOLOAD_OFF_MASK 0x0FF00000
736 #define OTPLAYOUTEXT_AUTOLOAD_OFF_SHIFT 20
737
738
739 /* Jtagm characteristics that appeared at a given corerev */
740 #define JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */
741 #define JTAGM_CREV_IRP 22 /* Able to do pause-ir */
742 #define JTAGM_CREV_RTI 28 /* Able to do return-to-idle */
743
744 /* jtagcmd */
745 #define JCMD_START 0x80000000
746 #define JCMD_BUSY 0x80000000
747 #define JCMD_STATE_MASK 0x60000000
748 #define JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */
749 #define JCMD_STATE_PIR 0x20000000 /* Pause IR */
750 #define JCMD_STATE_PDR 0x40000000 /* Pause DR */
751 #define JCMD_STATE_RTI 0x60000000 /* Run-test-idle */
752 #define JCMD0_ACC_MASK 0x0000f000
753 #define JCMD0_ACC_IRDR 0x00000000
754 #define JCMD0_ACC_DR 0x00001000
755 #define JCMD0_ACC_IR 0x00002000
756 #define JCMD0_ACC_RESET 0x00003000
757 #define JCMD0_ACC_IRPDR 0x00004000
758 #define JCMD0_ACC_PDR 0x00005000
759 #define JCMD0_IRW_MASK 0x00000f00
760 #define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
761 #define JCMD_ACC_IRDR 0x00000000
762 #define JCMD_ACC_DR 0x00010000
763 #define JCMD_ACC_IR 0x00020000
764 #define JCMD_ACC_RESET 0x00030000
765 #define JCMD_ACC_IRPDR 0x00040000
766 #define JCMD_ACC_PDR 0x00050000
767 #define JCMD_ACC_PIR 0x00060000
768 #define JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */
769 #define JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */
770 #define JCMD_IRW_MASK 0x00001f00
771 #define JCMD_IRW_SHIFT 8
772 #define JCMD_DRW_MASK 0x0000003f
773
774 /* jtagctrl */
775 #define JCTRL_FORCE_CLK 4 /* Force clock */
776 #define JCTRL_EXT_EN 2 /* Enable external targets */
777 #define JCTRL_EN 1 /* Enable Jtag master */
778
779 /* Fields in clkdiv */
780 #define CLKD_SFLASH 0x0f000000
781 #define CLKD_SFLASH_SHIFT 24
782 #define CLKD_OTP 0x000f0000
783 #define CLKD_OTP_SHIFT 16
784 #define CLKD_JTAG 0x00000f00
785 #define CLKD_JTAG_SHIFT 8
786 #define CLKD_UART 0x000000ff
787
788 #define CLKD2_SROM 0x00000003
789
790 /* intstatus/intmask */
791 #define CI_GPIO 0x00000001 /* gpio intr */
792 #define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
793 #define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
794 #define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
795 #define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
796 #define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
797 #define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
798 #define CI_SGWI 0x00000080 /* SeciGciWakeup intr (corerev >= 43) */
799 #define CI_SPM 0x00000100 /* spm intr (corerev >= 44) */
800 #define CI_WDRESET 0x80000000 /* watchdog reset occurred */
801
802 /* slow_clk_ctl */
803 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
804 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
805 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
806 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
807 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
808 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
809 * 0: LPO is enabled
810 */
811 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
812 * 0: power logic control
813 */
814 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
815 * PLL clock disable requests from core
816 */
817 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
818 * disable crystal when appropriate
819 */
820 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
821 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
822 #define SCC_CD_SHIFT 16
823
824 /* system_clk_ctl */
825 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
826 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
827 #define SYCC_FP 0x00000004 /* ForcePLLOn */
828 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
829 #define SYCC_HR 0x00000010 /* Force HT */
830 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
831 #define SYCC_CD_SHIFT 16
832
833 /* Indirect backplane access */
834 #define BPIA_BYTEEN 0x0000000f
835 #define BPIA_SZ1 0x00000001
836 #define BPIA_SZ2 0x00000003
837 #define BPIA_SZ4 0x00000007
838 #define BPIA_SZ8 0x0000000f
839 #define BPIA_WRITE 0x00000100
840 #define BPIA_START 0x00000200
841 #define BPIA_BUSY 0x00000200
842 #define BPIA_ERROR 0x00000400
843
844 /* pcmcia/prog/flash_config */
845 #define CF_EN 0x00000001 /* enable */
846 #define CF_EM_MASK 0x0000000e /* mode */
847 #define CF_EM_SHIFT 1
848 #define CF_EM_FLASH 0 /* flash/asynchronous mode */
849 #define CF_EM_SYNC 2 /* synchronous mode */
850 #define CF_EM_PCMCIA 4 /* pcmcia mode */
851 #define CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */
852 #define CF_BS 0x00000020 /* byteswap */
853 #define CF_CD_MASK 0x000000c0 /* clock divider */
854 #define CF_CD_SHIFT 6
855 #define CF_CD_DIV2 0x00000000 /* backplane/2 */
856 #define CF_CD_DIV3 0x00000040 /* backplane/3 */
857 #define CF_CD_DIV4 0x00000080 /* backplane/4 */
858 #define CF_CE 0x00000100 /* clock enable */
859 #define CF_SB 0x00000200 /* size/bytestrobe (synch only) */
860
861 /* pcmcia_memwait */
862 #define PM_W0_MASK 0x0000003f /* waitcount0 */
863 #define PM_W1_MASK 0x00001f00 /* waitcount1 */
864 #define PM_W1_SHIFT 8
865 #define PM_W2_MASK 0x001f0000 /* waitcount2 */
866 #define PM_W2_SHIFT 16
867 #define PM_W3_MASK 0x1f000000 /* waitcount3 */
868 #define PM_W3_SHIFT 24
869
870 /* pcmcia_attrwait */
871 #define PA_W0_MASK 0x0000003f /* waitcount0 */
872 #define PA_W1_MASK 0x00001f00 /* waitcount1 */
873 #define PA_W1_SHIFT 8
874 #define PA_W2_MASK 0x001f0000 /* waitcount2 */
875 #define PA_W2_SHIFT 16
876 #define PA_W3_MASK 0x1f000000 /* waitcount3 */
877 #define PA_W3_SHIFT 24
878
879 /* pcmcia_iowait */
880 #define PI_W0_MASK 0x0000003f /* waitcount0 */
881 #define PI_W1_MASK 0x00001f00 /* waitcount1 */
882 #define PI_W1_SHIFT 8
883 #define PI_W2_MASK 0x001f0000 /* waitcount2 */
884 #define PI_W2_SHIFT 16
885 #define PI_W3_MASK 0x1f000000 /* waitcount3 */
886 #define PI_W3_SHIFT 24
887
888 /* prog_waitcount */
889 #define PW_W0_MASK 0x0000001f /* waitcount0 */
890 #define PW_W1_MASK 0x00001f00 /* waitcount1 */
891 #define PW_W1_SHIFT 8
892 #define PW_W2_MASK 0x001f0000 /* waitcount2 */
893 #define PW_W2_SHIFT 16
894 #define PW_W3_MASK 0x1f000000 /* waitcount3 */
895 #define PW_W3_SHIFT 24
896
897 #define PW_W0 0x0000000c
898 #define PW_W1 0x00000a00
899 #define PW_W2 0x00020000
900 #define PW_W3 0x01000000
901
902 /* flash_waitcount */
903 #define FW_W0_MASK 0x0000003f /* waitcount0 */
904 #define FW_W1_MASK 0x00001f00 /* waitcount1 */
905 #define FW_W1_SHIFT 8
906 #define FW_W2_MASK 0x001f0000 /* waitcount2 */
907 #define FW_W2_SHIFT 16
908 #define FW_W3_MASK 0x1f000000 /* waitcount3 */
909 #define FW_W3_SHIFT 24
910
911 /* When Srom support present, fields in sromcontrol */
912 #define SRC_START 0x80000000
913 #define SRC_BUSY 0x80000000
914 #define SRC_OPCODE 0x60000000
915 #define SRC_OP_READ 0x00000000
916 #define SRC_OP_WRITE 0x20000000
917 #define SRC_OP_WRDIS 0x40000000
918 #define SRC_OP_WREN 0x60000000
919 #define SRC_OTPSEL 0x00000010
920 #define SRC_LOCK 0x00000008
921 #define SRC_SIZE_MASK 0x00000006
922 #define SRC_SIZE_1K 0x00000000
923 #define SRC_SIZE_4K 0x00000002
924 #define SRC_SIZE_16K 0x00000004
925 #define SRC_SIZE_SHIFT 1
926 #define SRC_PRESENT 0x00000001
927
928 /* Fields in pmucontrol */
929 #define PCTL_ILP_DIV_MASK 0xffff0000
930 #define PCTL_ILP_DIV_SHIFT 16
931 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
932 #define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
933 #define PCTL_HT_REQ_EN 0x00000100
934 #define PCTL_ALP_REQ_EN 0x00000080
935 #define PCTL_XTALFREQ_MASK 0x0000007c
936 #define PCTL_XTALFREQ_SHIFT 2
937 #define PCTL_ILP_DIV_EN 0x00000002
938 #define PCTL_LPO_SEL 0x00000001
939
940 /* Fields in clkstretch */
941 #define CSTRETCH_HT 0xffff0000
942 #define CSTRETCH_ALP 0x0000ffff
943
944 /* gpiotimerval */
945 #define GPIO_ONTIME_SHIFT 16
946
947 /* clockcontrol_n */
948 #define CN_N1_MASK 0x3f /* n1 control */
949 #define CN_N2_MASK 0x3f00 /* n2 control */
950 #define CN_N2_SHIFT 8
951 #define CN_PLLC_MASK 0xf0000 /* pll control */
952 #define CN_PLLC_SHIFT 16
953
954 /* clockcontrol_sb/pci/uart */
955 #define CC_M1_MASK 0x3f /* m1 control */
956 #define CC_M2_MASK 0x3f00 /* m2 control */
957 #define CC_M2_SHIFT 8
958 #define CC_M3_MASK 0x3f0000 /* m3 control */
959 #define CC_M3_SHIFT 16
960 #define CC_MC_MASK 0x1f000000 /* mux control */
961 #define CC_MC_SHIFT 24
962
963 /* N3M Clock control magic field values */
964 #define CC_F6_2 0x02 /* A factor of 2 in */
965 #define CC_F6_3 0x03 /* 6-bit fields like */
966 #define CC_F6_4 0x05 /* N1, M1 or M3 */
967 #define CC_F6_5 0x09
968 #define CC_F6_6 0x11
969 #define CC_F6_7 0x21
970
971 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
972
973 #define CC_MC_BYPASS 0x08
974 #define CC_MC_M1 0x04
975 #define CC_MC_M1M2 0x02
976 #define CC_MC_M1M2M3 0x01
977 #define CC_MC_M1M3 0x11
978
979 /* Type 2 Clock control magic field values */
980 #define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
981 #define CC_T2M2_BIAS 3 /* m2 bias */
982
983 #define CC_T2MC_M1BYP 1
984 #define CC_T2MC_M2BYP 2
985 #define CC_T2MC_M3BYP 4
986
987 /* Type 6 Clock control magic field values */
988 #define CC_T6_MMASK 1 /* bits of interest in m */
989 #define CC_T6_M0 120000000 /* sb clock for m = 0 */
990 #define CC_T6_M1 100000000 /* sb clock for m = 1 */
991 #define SB2MIPS_T6(sb) (2 * (sb))
992
993 /* Common clock base */
994 #define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
995 #define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */
996
997 /* Clock control values for 200MHz in 5350 */
998 #define CLKC_5350_N 0x0311
999 #define CLKC_5350_M 0x04020009
1000
1001 /* Flash types in the chipcommon capabilities register */
1002 #define FLASH_NONE 0x000 /* No flash */
1003 #define SFLASH_ST 0x100 /* ST serial flash */
1004 #define SFLASH_AT 0x200 /* Atmel serial flash */
1005 #define NFLASH 0x300
1006 #define PFLASH 0x700 /* Parallel flash */
1007 #define QSPIFLASH_ST 0x800
1008 #define QSPIFLASH_AT 0x900
1009
1010 /* Bits in the ExtBus config registers */
1011 #define CC_CFG_EN 0x0001 /* Enable */
1012 #define CC_CFG_EM_MASK 0x000e /* Extif Mode */
1013 #define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
1014 #define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
1015 #define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
1016 #define CC_CFG_EM_IDE 0x0006 /* IDE */
1017 #define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
1018 #define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
1019 #define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
1020 #define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
1021 #define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
1022
1023 /* ExtBus address space */
1024 #define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
1025 #define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
1026 #define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
1027 #define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
1028 #define CC_EB_IDE 0x1a800000 /* IDE memory base */
1029 #define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
1030 #define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
1031 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
1032 #define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
1033
1034
1035 /* Start/busy bit in flashcontrol */
1036 #define SFLASH_OPCODE 0x000000ff
1037 #define SFLASH_ACTION 0x00000700
1038 #define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
1039 #define SFLASH_START 0x80000000
1040 #define SFLASH_BUSY SFLASH_START
1041
1042 /* flashcontrol action codes */
1043 #define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
1044 #define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
1045 #define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */
1046 #define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */
1047 #define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */
1048 #define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */
1049 #define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */
1050
1051 /* flashcontrol action+opcodes for ST flashes */
1052 #define SFLASH_ST_WREN 0x0006 /* Write Enable */
1053 #define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
1054 #define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
1055 #define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
1056 #define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
1057 #define SFLASH_ST_PP 0x0302 /* Page Program */
1058 #define SFLASH_ST_SE 0x02d8 /* Sector Erase */
1059 #define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
1060 #define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
1061 #define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
1062 #define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
1063 #define SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */
1064
1065 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */
1066 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */
1067
1068 /* Status register bits for ST flashes */
1069 #define SFLASH_ST_WIP 0x01 /* Write In Progress */
1070 #define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
1071 #define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
1072 #define SFLASH_ST_BP_SHIFT 2
1073 #define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
1074
1075 /* flashcontrol action+opcodes for Atmel flashes */
1076 #define SFLASH_AT_READ 0x07e8
1077 #define SFLASH_AT_PAGE_READ 0x07d2
1078 #define SFLASH_AT_BUF1_READ
1079 #define SFLASH_AT_BUF2_READ
1080 #define SFLASH_AT_STATUS 0x01d7
1081 #define SFLASH_AT_BUF1_WRITE 0x0384
1082 #define SFLASH_AT_BUF2_WRITE 0x0387
1083 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
1084 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
1085 #define SFLASH_AT_BUF1_PROGRAM 0x0288
1086 #define SFLASH_AT_BUF2_PROGRAM 0x0289
1087 #define SFLASH_AT_PAGE_ERASE 0x0281
1088 #define SFLASH_AT_BLOCK_ERASE 0x0250
1089 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
1090 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
1091 #define SFLASH_AT_BUF1_LOAD 0x0253
1092 #define SFLASH_AT_BUF2_LOAD 0x0255
1093 #define SFLASH_AT_BUF1_COMPARE 0x0260
1094 #define SFLASH_AT_BUF2_COMPARE 0x0261
1095 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
1096 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
1097
1098 /* Status register bits for Atmel flashes */
1099 #define SFLASH_AT_READY 0x80
1100 #define SFLASH_AT_MISMATCH 0x40
1101 #define SFLASH_AT_ID_MASK 0x38
1102 #define SFLASH_AT_ID_SHIFT 3
1103
1104 /* SPI register bits, corerev >= 37 */
1105 #define GSIO_START 0x80000000
1106 #define GSIO_BUSY GSIO_START
1107
1108 /*
1109 * These are the UART port assignments, expressed as offsets from the base
1110 * register. These assignments should hold for any serial port based on
1111 * a 8250, 16450, or 16550(A).
1112 */
1113
1114 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1115 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
1116 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
1117 #define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
1118 #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
1119 #define UART_IIR 2 /* In: Interrupt Identity Register */
1120 #define UART_FCR 2 /* Out: FIFO Control Register */
1121 #define UART_LCR 3 /* Out: Line Control Register */
1122 #define UART_MCR 4 /* Out: Modem Control Register */
1123 #define UART_LSR 5 /* In: Line Status Register */
1124 #define UART_MSR 6 /* In: Modem Status Register */
1125 #define UART_SCR 7 /* I/O: Scratch Register */
1126 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1127 #define UART_LCR_WLEN8 0x03 /* Word length: 8 bits */
1128 #define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
1129 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1130 #define UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */
1131 #define UART_LSR_TDHR 0x40 /* Data-hold-register empty */
1132 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1133 #define UART_LSR_BREAK 0x10 /* Break interrupt */
1134 #define UART_LSR_FRAMING 0x08 /* Framing error */
1135 #define UART_LSR_PARITY 0x04 /* Parity error */
1136 #define UART_LSR_OVERRUN 0x02 /* Overrun error */
1137 #define UART_LSR_RXRDY 0x01 /* Receiver ready */
1138 #define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
1139
1140 /* Interrupt Identity Register (IIR) bits */
1141 #define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
1142 #define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
1143 #define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
1144 #define UART_IIR_NOINT 0x1 /* No interrupt pending */
1145 #define UART_IIR_THRE 0x2 /* THR empty */
1146 #define UART_IIR_RCVD_DATA 0x4 /* Received data available */
1147 #define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
1148 #define UART_IIR_CHAR_TIME 0xc /* Character time */
1149
1150 /* Interrupt Enable Register (IER) bits */
1151 #define UART_IER_EDSSI 8 /* enable modem status interrupt */
1152 #define UART_IER_ELSI 4 /* enable receiver line status interrupt */
1153 #define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
1154 #define UART_IER_ERBFI 1 /* enable data available interrupt */
1155
1156 /* pmustatus */
1157 #define PST_EXTLPOAVAIL 0x0100
1158 #define PST_WDRESET 0x0080
1159 #define PST_INTPEND 0x0040
1160 #define PST_SBCLKST 0x0030
1161 #define PST_SBCLKST_ILP 0x0010
1162 #define PST_SBCLKST_ALP 0x0020
1163 #define PST_SBCLKST_HT 0x0030
1164 #define PST_ALPAVAIL 0x0008
1165 #define PST_HTAVAIL 0x0004
1166 #define PST_RESINIT 0x0003
1167
1168 /* pmucapabilities */
1169 #define PCAP_REV_MASK 0x000000ff
1170 #define PCAP_RC_MASK 0x00001f00
1171 #define PCAP_RC_SHIFT 8
1172 #define PCAP_TC_MASK 0x0001e000
1173 #define PCAP_TC_SHIFT 13
1174 #define PCAP_PC_MASK 0x001e0000
1175 #define PCAP_PC_SHIFT 17
1176 #define PCAP_VC_MASK 0x01e00000
1177 #define PCAP_VC_SHIFT 21
1178 #define PCAP_CC_MASK 0x1e000000
1179 #define PCAP_CC_SHIFT 25
1180 #define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
1181 #define PCAP5_PC_SHIFT 17
1182 #define PCAP5_VC_MASK 0x07c00000
1183 #define PCAP5_VC_SHIFT 22
1184 #define PCAP5_CC_MASK 0xf8000000
1185 #define PCAP5_CC_SHIFT 27
1186
1187 /* PMU Resource Request Timer registers */
1188 /* This is based on PmuRev0 */
1189 #define PRRT_TIME_MASK 0x03ff
1190 #define PRRT_INTEN 0x0400
1191 #define PRRT_REQ_ACTIVE 0x0800
1192 #define PRRT_ALP_REQ 0x1000
1193 #define PRRT_HT_REQ 0x2000
1194 #define PRRT_HQ_REQ 0x4000
1195
1196 /* PMU resource bit position */
1197 #define PMURES_BIT(bit) (1 << (bit))
1198
1199 /* PMU resource number limit */
1200 #define PMURES_MAX_RESNUM 30
1201
1202 /* PMU chip control0 register */
1203 #define PMU_CHIPCTL0 0
1204
1205 /* clock req types */
1206 #define PMU_CC1_CLKREQ_TYPE_SHIFT 19
1207 #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT)
1208
1209 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0
1210 #define CLKREQ_TYPE_CONFIG_PUSHPULL 1
1211
1212 /* PMU chip control1 register */
1213 #define PMU_CHIPCTL1 1
1214 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000
1215 #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010
1216
1217 #define PMU_CC1_IF_TYPE_MASK 0x00000030
1218 #define PMU_CC1_IF_TYPE_RMII 0x00000000
1219 #define PMU_CC1_IF_TYPE_MII 0x00000010
1220 #define PMU_CC1_IF_TYPE_RGMII 0x00000020
1221
1222 #define PMU_CC1_SW_TYPE_MASK 0x000000c0
1223 #define PMU_CC1_SW_TYPE_EPHY 0x00000000
1224 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
1225 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
1226 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0
1227
1228 /* PMU chip control2 register */
1229 #define PMU_CHIPCTL2 2
1230 #define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1 << 18)
1231 #define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1 << 19)
1232 #define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1 << 20)
1233 #define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1 << 21)
1234
1235 /* PMU chip control3 register */
1236 #define PMU_CHIPCTL3 3
1237 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19
1238 #define PMU_CC3_ENABLE_RF_SHIFT 22
1239 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23
1240
1241 /* PMU chip control5 register */
1242 #define PMU_CHIPCTL5 5
1243
1244 /* PMU chip control6 register */
1245 #define PMU_CHIPCTL6 6
1246 #define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4)
1247 #define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6)
1248
1249 /* PMU corerev and chip specific PLL controls.
1250 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
1251 * to differentiate different PLLs controlled by the same PMU rev.
1252 */
1253 /* pllcontrol registers */
1254 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
1255 #define PMU0_PLL0_PLLCTL0 0
1256 #define PMU0_PLL0_PC0_PDIV_MASK 1
1257 #define PMU0_PLL0_PC0_PDIV_FREQ 25000
1258 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
1259 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
1260 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8
1261
1262 /* PC0_DIV_ARM for PLLOUT_ARM */
1263 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
1264 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
1265 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
1266 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
1267 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
1268 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
1269 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
1270 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
1271
1272 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
1273 #define PMU0_PLL0_PLLCTL1 1
1274 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
1275 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
1276 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
1277 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
1278 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040
1279
1280 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
1281 #define PMU0_PLL0_PLLCTL2 2
1282 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
1283 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
1284
1285 /* pllcontrol registers */
1286 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
1287 #define PMU1_PLL0_PLLCTL0 0
1288 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
1289 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20
1290 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
1291 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24
1292
1293 /* m<x>div */
1294 #define PMU1_PLL0_PLLCTL1 1
1295 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
1296 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0
1297 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
1298 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8
1299 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
1300 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16
1301 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
1302 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24
1303 #define PMU1_PLL0_PC1_M4DIV_BY_9 9
1304 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12
1305 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24
1306
1307 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
1308 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1309 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1310
1311 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
1312 #define PMU1_PLL0_PLLCTL2 2
1313 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
1314 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0
1315 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc
1316 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12
1317 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24
1318 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
1319 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8
1320 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12
1321 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24
1322 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
1323 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
1324 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1
1325 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */
1326 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
1327 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
1328
1329 /* ndiv_frac */
1330 #define PMU1_PLL0_PLLCTL3 3
1331 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
1332 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
1333
1334 /* pll_ctrl */
1335 #define PMU1_PLL0_PLLCTL4 4
1336
1337 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
1338 #define PMU1_PLL0_PLLCTL5 5
1339 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
1340 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
1341
1342 /* PMU rev 2 control words */
1343 #define PMU2_PHY_PLL_PLLCTL 4
1344 #define PMU2_SI_PLL_PLLCTL 10
1345
1346 /* PMU rev 2 */
1347 /* pllcontrol registers */
1348 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
1349 #define PMU2_PLL_PLLCTL0 0
1350 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
1351 #define PMU2_PLL_PC0_P1DIV_SHIFT 20
1352 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
1353 #define PMU2_PLL_PC0_P2DIV_SHIFT 24
1354
1355 /* m<x>div */
1356 #define PMU2_PLL_PLLCTL1 1
1357 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
1358 #define PMU2_PLL_PC1_M1DIV_SHIFT 0
1359 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
1360 #define PMU2_PLL_PC1_M2DIV_SHIFT 8
1361 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
1362 #define PMU2_PLL_PC1_M3DIV_SHIFT 16
1363 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
1364 #define PMU2_PLL_PC1_M4DIV_SHIFT 24
1365
1366 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
1367 #define PMU2_PLL_PLLCTL2 2
1368 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
1369 #define PMU2_PLL_PC2_M5DIV_SHIFT 0
1370 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
1371 #define PMU2_PLL_PC2_M6DIV_SHIFT 8
1372 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
1373 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17
1374 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
1375 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20
1376
1377 /* ndiv_frac */
1378 #define PMU2_PLL_PLLCTL3 3
1379 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
1380 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
1381
1382 /* pll_ctrl */
1383 #define PMU2_PLL_PLLCTL4 4
1384
1385 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
1386 #define PMU2_PLL_PLLCTL5 5
1387 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
1388 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
1389 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
1390 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
1391 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
1392 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
1393 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
1394 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
1395 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
1396 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
1397 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
1398 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
1399
1400 /* PMU rev 5 (& 6) */
1401 #define PMU5_PLL_P1P2_OFF 0
1402 #define PMU5_PLL_P1_MASK 0x0f000000
1403 #define PMU5_PLL_P1_SHIFT 24
1404 #define PMU5_PLL_P2_MASK 0x00f00000
1405 #define PMU5_PLL_P2_SHIFT 20
1406 #define PMU5_PLL_M14_OFF 1
1407 #define PMU5_PLL_MDIV_MASK 0x000000ff
1408 #define PMU5_PLL_MDIV_WIDTH 8
1409 #define PMU5_PLL_NM5_OFF 2
1410 #define PMU5_PLL_NDIV_MASK 0xfff00000
1411 #define PMU5_PLL_NDIV_SHIFT 20
1412 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
1413 #define PMU5_PLL_NDIV_MODE_SHIFT 17
1414 #define PMU5_PLL_FMAB_OFF 3
1415 #define PMU5_PLL_MRAT_MASK 0xf0000000
1416 #define PMU5_PLL_MRAT_SHIFT 28
1417 #define PMU5_PLL_ABRAT_MASK 0x08000000
1418 #define PMU5_PLL_ABRAT_SHIFT 27
1419 #define PMU5_PLL_FDIV_MASK 0x07ffffff
1420 #define PMU5_PLL_PLLCTL_OFF 4
1421 #define PMU5_PLL_PCHI_OFF 5
1422 #define PMU5_PLL_PCHI_MASK 0x0000003f
1423
1424 /* pmu XtalFreqRatio */
1425 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
1426 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
1427 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
1428
1429 /* Divider allocation in 4716/47162/5356/5357 */
1430 #define PMU5_MAINPLL_CPU 1
1431 #define PMU5_MAINPLL_MEM 2
1432 #define PMU5_MAINPLL_SI 3
1433
1434 /* 4706 PMU */
1435 #define PMU4706_MAINPLL_PLL0 0
1436 #define PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
1437 #define PMU6_4706_PROC_P2DIV_MASK 0x000f0000
1438 #define PMU6_4706_PROC_P2DIV_SHIFT 16
1439 #define PMU6_4706_PROC_P1DIV_MASK 0x0000f000
1440 #define PMU6_4706_PROC_P1DIV_SHIFT 12
1441 #define PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
1442 #define PMU6_4706_PROC_NDIV_INT_SHIFT 3
1443 #define PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1444 #define PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1445
1446 #define PMU7_PLL_PLLCTL7 7
1447 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000
1448 #define PMU7_PLL_CTL7_M4DIV_SHIFT 24
1449 #define PMU7_PLL_CTL7_M4DIV_BY_6 6
1450 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc
1451 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18
1452 #define PMU7_PLL_PLLCTL8 8
1453 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff
1454 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0
1455 #define PMU7_PLL_CTL8_M5DIV_BY_8 8
1456 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc
1457 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18
1458 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00
1459 #define PMU7_PLL_CTL8_M6DIV_SHIFT 8
1460 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc
1461 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18
1462 #define PMU7_PLL_PLLCTL11 11
1463 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00
1464 #define PMU7_PLL_PLLCTL11_VAL 0x22222200
1465
1466 /* PMU rev 15 */
1467 #define PMU15_PLL_PLLCTL0 0
1468 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1469 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0
1470 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1471 #define PMU15_PLL_PC0_FREQTGT_SHIFT 2
1472 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1473 #define PMU15_PLL_PC0_PRESCALE_SHIFT 22
1474 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1475 #define PMU15_PLL_PC0_KPCTRL_SHIFT 24
1476 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1477 #define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1478 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1479 #define PMU15_PLL_PC0_FDCMODE_SHIFT 30
1480 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1481 #define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1482
1483 #define PMU15_PLL_PLLCTL1 1
1484 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060
1485 #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5
1486 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040
1487 #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6
1488 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80
1489 #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7
1490 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000
1491 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17
1492 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000
1493 #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26
1494 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000
1495 #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28
1496 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000
1497 #define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30
1498
1499 #define PMU15_PLL_PLLCTL2 2
1500 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001
1501 #define PMU15_PLL_PC2_CTEN_SHIFT 0
1502
1503 #define PMU15_PLL_PLLCTL3 3
1504 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001
1505 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0
1506 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000
1507 #define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25
1508 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01
1509 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0
1510 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02
1511 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1
1512 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04
1513 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2
1514 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18
1515 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3
1516 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60
1517 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5
1518 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0
1519 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1
1520 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2
1521 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3
1522
1523 #define PMU15_PLL_PLLCTL4 4
1524 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007
1525 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0
1526 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038
1527 #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3
1528 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0
1529 #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6
1530 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00
1531 #define PMU15_PLL_PC4_DBGMODE_SHIFT 9
1532 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000
1533 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12
1534 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000
1535 #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13
1536 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000
1537 #define PMU15_PLL_PC4_DINPOL_SHIFT 20
1538 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000
1539 #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21
1540 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000
1541 #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22
1542 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000
1543 #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23
1544 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000
1545 #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24
1546 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000
1547 #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25
1548 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000
1549 #define PMU15_PLL_PC4_TEST_EN_SHIFT 26
1550
1551 #define PMU15_PLL_PLLCTL5 5
1552 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF
1553 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0
1554 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000
1555 #define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20
1556 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000
1557 #define PMU15_PLL_PC5_PRESCALE_SHIFT 27
1558
1559 #define PMU15_PLL_PLLCTL6 6
1560 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF
1561 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0
1562 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000
1563 #define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20
1564 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000
1565 #define PMU15_PLL_PC6_PRESCALE_SHIFT 27
1566
1567 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1
1568 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5
1569 #define PMU15_ARM_96MHZ 96000000 /* 96 Mhz */
1570 #define PMU15_ARM_98MHZ 98400000 /* 98.4 Mhz */
1571 #define PMU15_ARM_97MHZ 97000000 /* 97 Mhz */
1572
1573
1574 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070
1575 #define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4
1576
1577 #define PMU17_PLLCTL2_NDIV_MODE_INT 0
1578 #define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1
1579 #define PMU17_PLLCTL2_NDIV_MODE_MASH111 2
1580 #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3
1581
1582 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0
1583 #define PMU17_PLLCTL0_BBPLL_DRST 3
1584 #define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8
1585
1586 /* PLL usage in 4335 */
1587 #define PMU4335_PLL0_PC2_P1DIV_MASK 0x000f0000
1588 #define PMU4335_PLL0_PC2_P1DIV_SHIFT 16
1589 #define PMU4335_PLL0_PC2_NDIV_INT_MASK 0xff800000
1590 #define PMU4335_PLL0_PC2_NDIV_INT_SHIFT 23
1591 #define PMU4335_PLL0_PC1_MDIV2_MASK 0x0000ff00
1592 #define PMU4335_PLL0_PC1_MDIV2_SHIFT 8
1593
1594 /* PLL usage in 4716/47162 */
1595 #define PMU4716_MAINPLL_PLL0 12
1596
1597 /* PLL usage in 5356/5357 */
1598 #define PMU5356_MAINPLL_PLL0 0
1599 #define PMU5357_MAINPLL_PLL0 0
1600
1601 /* 4716/47162 resources */
1602 #define RES4716_PROC_PLL_ON 0x00000040
1603 #define RES4716_PROC_HT_AVAIL 0x00000080
1604
1605 /* 4716/4717/4718 Chip specific ChipControl register bits */
1606 #define CCTRL_471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared w/ pflash */
1607
1608 /* 5357 Chip specific ChipControl register bits */
1609 /* 2nd - 32-bit reg */
1610 #define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 /* I2S pins enable */
1611 #define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 /* I2C/SPI pins enable */
1612
1613 /* 5354 resources */
1614 #define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
1615 #define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
1616 #define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
1617 #define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
1618 #define RES5354_ILP_REQUEST 4 /* 0x00010 */
1619 #define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
1620 #define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
1621 #define RES5354_ROM_SWITCH 7 /* 0x00080 */
1622 #define RES5354_PA_REF_LDO 8 /* 0x00100 */
1623 #define RES5354_RADIO_LDO 9 /* 0x00200 */
1624 #define RES5354_AFE_LDO 10 /* 0x00400 */
1625 #define RES5354_PLL_LDO 11 /* 0x00800 */
1626 #define RES5354_BG_FILTBYP 12 /* 0x01000 */
1627 #define RES5354_TX_FILTBYP 13 /* 0x02000 */
1628 #define RES5354_RX_FILTBYP 14 /* 0x04000 */
1629 #define RES5354_XTAL_PU 15 /* 0x08000 */
1630 #define RES5354_XTAL_EN 16 /* 0x10000 */
1631 #define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
1632 #define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
1633 #define RES5354_BB_PLL_PU 19 /* 0x80000 */
1634
1635 /* 5357 Chip specific ChipControl register bits */
1636 #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
1637 #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
1638 #define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */
1639
1640 /* 43217 Chip specific ChipControl register bits */
1641 #define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */
1642 #define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */
1643
1644 /* 43228 Chip specific ChipControl register bits */
1645 #define CCTRL43228_EXTPA_C0 (1<<14) /* core1 extPA in ChipControl 1, bit 14 */
1646 #define CCTRL43228_EXTPA_C1 (1<<9) /* core0 extPA in ChipControl 1, bit 1 */
1647
1648 /* 4328 resources */
1649 #define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
1650 #define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
1651 #define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
1652 #define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
1653 #define RES4328_ILP_REQUEST 4 /* 0x00010 */
1654 #define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
1655 #define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
1656 #define RES4328_ROM_SWITCH 7 /* 0x00080 */
1657 #define RES4328_PA_REF_LDO 8 /* 0x00100 */
1658 #define RES4328_RADIO_LDO 9 /* 0x00200 */
1659 #define RES4328_AFE_LDO 10 /* 0x00400 */
1660 #define RES4328_PLL_LDO 11 /* 0x00800 */
1661 #define RES4328_BG_FILTBYP 12 /* 0x01000 */
1662 #define RES4328_TX_FILTBYP 13 /* 0x02000 */
1663 #define RES4328_RX_FILTBYP 14 /* 0x04000 */
1664 #define RES4328_XTAL_PU 15 /* 0x08000 */
1665 #define RES4328_XTAL_EN 16 /* 0x10000 */
1666 #define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
1667 #define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
1668 #define RES4328_BB_PLL_PU 19 /* 0x80000 */
1669
1670 /* 4325 A0/A1 resources */
1671 #define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
1672 #define RES4325_CBUCK_BURST 1 /* 0x00000002 */
1673 #define RES4325_CBUCK_PWM 2 /* 0x00000004 */
1674 #define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
1675 #define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
1676 #define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
1677 #define RES4325_ILP_REQUEST 6 /* 0x00000040 */
1678 #define RES4325_ABUCK_BURST 7 /* 0x00000080 */
1679 #define RES4325_ABUCK_PWM 8 /* 0x00000100 */
1680 #define RES4325_LNLDO1_PU 9 /* 0x00000200 */
1681 #define RES4325_OTP_PU 10 /* 0x00000400 */
1682 #define RES4325_LNLDO3_PU 11 /* 0x00000800 */
1683 #define RES4325_LNLDO4_PU 12 /* 0x00001000 */
1684 #define RES4325_XTAL_PU 13 /* 0x00002000 */
1685 #define RES4325_ALP_AVAIL 14 /* 0x00004000 */
1686 #define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
1687 #define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
1688 #define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1689 #define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1690 #define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
1691 #define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1692 #define RES4325_HT_AVAIL 21 /* 0x00200000 */
1693
1694 /* 4325 B0/C0 resources */
1695 #define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */
1696 #define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */
1697 #define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */
1698 #define RES4325B0_CLDO_PU 4 /* 0x00000010 */
1699
1700 /* 4325 C1 resources */
1701 #define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */
1702
1703 /* 4325 chip-specific ChipStatus register bits */
1704 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003
1705 #define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1706 #define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1707 #define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
1708 #define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
1709 #define CST4325_SDIO_USB_MODE_MASK 0x00000004
1710 #define CST4325_SDIO_USB_MODE_SHIFT 2
1711 #define CST4325_RCAL_VALID_MASK 0x00000008
1712 #define CST4325_RCAL_VALID_SHIFT 3
1713 #define CST4325_RCAL_VALUE_MASK 0x000001f0
1714 #define CST4325_RCAL_VALUE_SHIFT 4
1715 #define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
1716 #define CST4325_PMUTOP_2B_SHIFT 9
1717
1718 #define RES4329_RESERVED0 0 /* 0x00000001 */
1719 #define RES4329_CBUCK_LPOM 1 /* 0x00000002 */
1720 #define RES4329_CBUCK_BURST 2 /* 0x00000004 */
1721 #define RES4329_CBUCK_PWM 3 /* 0x00000008 */
1722 #define RES4329_CLDO_PU 4 /* 0x00000010 */
1723 #define RES4329_PALDO_PU 5 /* 0x00000020 */
1724 #define RES4329_ILP_REQUEST 6 /* 0x00000040 */
1725 #define RES4329_RESERVED7 7 /* 0x00000080 */
1726 #define RES4329_RESERVED8 8 /* 0x00000100 */
1727 #define RES4329_LNLDO1_PU 9 /* 0x00000200 */
1728 #define RES4329_OTP_PU 10 /* 0x00000400 */
1729 #define RES4329_RESERVED11 11 /* 0x00000800 */
1730 #define RES4329_LNLDO2_PU 12 /* 0x00001000 */
1731 #define RES4329_XTAL_PU 13 /* 0x00002000 */
1732 #define RES4329_ALP_AVAIL 14 /* 0x00004000 */
1733 #define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */
1734 #define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */
1735 #define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1736 #define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1737 #define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */
1738 #define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1739 #define RES4329_HT_AVAIL 21 /* 0x00200000 */
1740
1741 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
1742 #define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1743 #define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1744 #define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */
1745 #define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
1746 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
1747 #define CST4329_SPI_SDIO_MODE_SHIFT 2
1748
1749 /* 4312 chip-specific ChipStatus register bits */
1750 #define CST4312_SPROM_OTP_SEL_MASK 0x00000003
1751 #define CST4312_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1752 #define CST4312_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1753 #define CST4312_OTP_SEL 2 /* OTP is powered up, no SPROM */
1754 #define CST4312_OTP_BAD 3 /* OTP is broken, SPROM is present */
1755
1756 /* 4312 resources (all PMU chips with little memory constraint) */
1757 #define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
1758 #define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
1759 #define RES4312_PA_REF_LDO 2 /* 0x00000004 */
1760 #define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
1761 #define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
1762 #define RES4312_RADIO_LDO 5 /* 0x00000020 */
1763 #define RES4312_ILP_REQUEST 6 /* 0x00000040 */
1764 #define RES4312_BG_FILTBYP 7 /* 0x00000080 */
1765 #define RES4312_TX_FILTBYP 8 /* 0x00000100 */
1766 #define RES4312_RX_FILTBYP 9 /* 0x00000200 */
1767 #define RES4312_XTAL_PU 10 /* 0x00000400 */
1768 #define RES4312_ALP_AVAIL 11 /* 0x00000800 */
1769 #define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
1770 #define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
1771 #define RES4312_HT_AVAIL 14 /* 0x00004000 */
1772
1773 /* 4322 resources */
1774 #define RES4322_RF_LDO 0
1775 #define RES4322_ILP_REQUEST 1
1776 #define RES4322_XTAL_PU 2
1777 #define RES4322_ALP_AVAIL 3
1778 #define RES4322_SI_PLL_ON 4
1779 #define RES4322_HT_SI_AVAIL 5
1780 #define RES4322_PHY_PLL_ON 6
1781 #define RES4322_HT_PHY_AVAIL 7
1782 #define RES4322_OTP_PU 8
1783
1784 /* 4322 chip-specific ChipStatus register bits */
1785 #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020
1786 #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0
1787 #define CST4322_SPROM_OTP_SEL_SHIFT 6
1788 #define CST4322_NO_SPROM_OTP 0 /* no OTP, no SPROM */
1789 #define CST4322_SPROM_PRESENT 1 /* SPROM is present */
1790 #define CST4322_OTP_PRESENT 2 /* OTP is present */
1791 #define CST4322_PCI_OR_USB 0x00000100
1792 #define CST4322_BOOT_MASK 0x00000600
1793 #define CST4322_BOOT_SHIFT 9
1794 #define CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
1795 #define CST4322_BOOT_FROM_ROM 1 /* boot from ROM */
1796 #define CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */
1797 #define CST4322_BOOT_FROM_INVALID 3
1798 #define CST4322_ILP_DIV_EN 0x00000800
1799 #define CST4322_FLASH_TYPE_MASK 0x00001000
1800 #define CST4322_FLASH_TYPE_SHIFT 12
1801 #define CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */
1802 #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */
1803 #define CST4322_ARM_TAP_SEL 0x00002000
1804 #define CST4322_RES_INIT_MODE_MASK 0x0000c000
1805 #define CST4322_RES_INIT_MODE_SHIFT 14
1806 #define CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */
1807 #define CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */
1808 #define CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */
1809 #define CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */
1810 #define CST4322_PCIPLLCLK_GATING 0x00010000
1811 #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000
1812 #define CST4322_PCI_CARDBUS_MODE 0x00040000
1813
1814 /* 43224 chip-specific ChipControl register bits */
1815 #define CCTRL43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
1816 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
1817 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
1818
1819 /* 43236 resources */
1820 #define RES43236_REGULATOR 0
1821 #define RES43236_ILP_REQUEST 1
1822 #define RES43236_XTAL_PU 2
1823 #define RES43236_ALP_AVAIL 3
1824 #define RES43236_SI_PLL_ON 4
1825 #define RES43236_HT_SI_AVAIL 5
1826
1827 /* 43236 chip-specific ChipControl register bits */
1828 #define CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */
1829 #define CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
1830 #define CCTRL43236_EXT_LNA (1<<2) /* 0 disable */
1831 #define CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */
1832 #define CCTRL43236_GSIO (1<<4) /* 0 disable */
1833
1834 /* 43236 Chip specific ChipStatus register bits */
1835 #define CST43236_SFLASH_MASK 0x00000040
1836 #define CST43236_OTP_SEL_MASK 0x00000080
1837 #define CST43236_OTP_SEL_SHIFT 7
1838 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
1839 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
1840 #define CST43236_BOOT_MASK 0x00001800
1841 #define CST43236_BOOT_SHIFT 11
1842 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
1843 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
1844 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
1845 #define CST43236_BOOT_FROM_INVALID 3
1846
1847 /* 43237 resources */
1848 #define RES43237_REGULATOR 0
1849 #define RES43237_ILP_REQUEST 1
1850 #define RES43237_XTAL_PU 2
1851 #define RES43237_ALP_AVAIL 3
1852 #define RES43237_SI_PLL_ON 4
1853 #define RES43237_HT_SI_AVAIL 5
1854
1855 /* 43237 chip-specific ChipControl register bits */
1856 #define CCTRL43237_BT_COEXIST (1<<0) /* 0 disable */
1857 #define CCTRL43237_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
1858 #define CCTRL43237_EXT_LNA (1<<2) /* 0 disable */
1859 #define CCTRL43237_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */
1860 #define CCTRL43237_GSIO (1<<4) /* 0 disable */
1861
1862 /* 43237 Chip specific ChipStatus register bits */
1863 #define CST43237_SFLASH_MASK 0x00000040
1864 #define CST43237_OTP_SEL_MASK 0x00000080
1865 #define CST43237_OTP_SEL_SHIFT 7
1866 #define CST43237_HSIC_MASK 0x00000100 /* USB/HSIC */
1867 #define CST43237_BP_CLK 0x00000200 /* 120/96Mbps */
1868 #define CST43237_BOOT_MASK 0x00001800
1869 #define CST43237_BOOT_SHIFT 11
1870 #define CST43237_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
1871 #define CST43237_BOOT_FROM_ROM 1 /* boot from ROM */
1872 #define CST43237_BOOT_FROM_FLASH 2 /* boot from FLASH */
1873 #define CST43237_BOOT_FROM_INVALID 3
1874
1875 /* 43239 resources */
1876 #define RES43239_OTP_PU 9
1877 #define RES43239_MACPHY_CLKAVAIL 23
1878 #define RES43239_HT_AVAIL 24
1879
1880 /* 43239 Chip specific ChipStatus register bits */
1881 #define CST43239_SPROM_MASK 0x00000002
1882 #define CST43239_SFLASH_MASK 0x00000004
1883 #define CST43239_RES_INIT_MODE_SHIFT 7
1884 #define CST43239_RES_INIT_MODE_MASK 0x000001f0
1885 #define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15)) /* SDIO || gSPI */
1886 #define CST43239_CHIPMODE_USB20D(cs) (~(cs) & (1 << 15)) /* USB || USBDA */
1887 #define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0) /* SDIO */
1888 #define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) /* gSPI */
1889
1890 /* 4324 resources */
1891 /* 43242 use same PMU as 4324 */
1892 #define RES4324_LPLDO_PU 0
1893 #define RES4324_RESET_PULLDN_DIS 1
1894 #define RES4324_PMU_BG_PU 2
1895 #define RES4324_HSIC_LDO_PU 3
1896 #define RES4324_CBUCK_LPOM_PU 4
1897 #define RES4324_CBUCK_PFM_PU 5
1898 #define RES4324_CLDO_PU 6
1899 #define RES4324_LPLDO2_LVM 7
1900 #define RES4324_LNLDO1_PU 8
1901 #define RES4324_LNLDO2_PU 9
1902 #define RES4324_LDO3P3_PU 10
1903 #define RES4324_OTP_PU 11
1904 #define RES4324_XTAL_PU 12
1905 #define RES4324_BBPLL_PU 13
1906 #define RES4324_LQ_AVAIL 14
1907 #define RES4324_WL_CORE_READY 17
1908 #define RES4324_ILP_REQ 18
1909 #define RES4324_ALP_AVAIL 19
1910 #define RES4324_PALDO_PU 20
1911 #define RES4324_RADIO_PU 21
1912 #define RES4324_SR_CLK_STABLE 22
1913 #define RES4324_SR_SAVE_RESTORE 23
1914 #define RES4324_SR_PHY_PWRSW 24
1915 #define RES4324_SR_PHY_PIC 25
1916 #define RES4324_SR_SUBCORE_PWRSW 26
1917 #define RES4324_SR_SUBCORE_PIC 27
1918 #define RES4324_SR_MEM_PM0 28
1919 #define RES4324_HT_AVAIL 29
1920 #define RES4324_MACPHY_CLKAVAIL 30
1921
1922 /* 4324 Chip specific ChipStatus register bits */
1923 #define CST4324_SPROM_MASK 0x00000080
1924 #define CST4324_SFLASH_MASK 0x00400000
1925 #define CST4324_RES_INIT_MODE_SHIFT 10
1926 #define CST4324_RES_INIT_MODE_MASK 0x00000c00
1927 #define CST4324_CHIPMODE_MASK 0x7
1928 #define CST4324_CHIPMODE_SDIOD(cs) ((~(cs)) & (1 << 2)) /* SDIO || gSPI */
1929 #define CST4324_CHIPMODE_USB20D(cs) (((cs) & CST4324_CHIPMODE_MASK) == 0x6) /* USB || USBDA */
1930
1931 /* 43242 Chip specific ChipStatus register bits */
1932 #define CST43242_SFLASH_MASK 0x00000008
1933 #define CST43242_SR_HALT (1<<25)
1934 #define CST43242_SR_CHIP_STATUS_2 27 /* bit 27 */
1935
1936 /* 4331 resources */
1937 #define RES4331_REGULATOR 0
1938 #define RES4331_ILP_REQUEST 1
1939 #define RES4331_XTAL_PU 2
1940 #define RES4331_ALP_AVAIL 3
1941 #define RES4331_SI_PLL_ON 4
1942 #define RES4331_HT_SI_AVAIL 5
1943
1944 /* 4331 chip-specific ChipControl register bits */
1945 #define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */
1946 #define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
1947 #define CCTRL4331_EXT_LNA_G (1<<2) /* 0 disable */
1948 #define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */
1949 #define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */
1950 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */
1951 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */
1952 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */
1953 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */
1954 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */
1955 #define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */
1956 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */
1957 #define CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa disable, 1 ext pa enabled */
1958 #define CCTRL4331_EXT_LNA_A (1<<13) /* 0 disable */
1959 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */
1960 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */
1961 #define CCTRL4331_EXTPA_ANA_EN (1<<24) /* 0 ext pa disable, 1 ext pa enabled */
1962
1963 /* 4331 Chip specific ChipStatus register bits */
1964 #define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */
1965 #define CST4331_SPROM_OTP_SEL_MASK 0x00000006
1966 #define CST4331_SPROM_OTP_SEL_SHIFT 1
1967 #define CST4331_SPROM_PRESENT 0x00000002
1968 #define CST4331_OTP_PRESENT 0x00000004
1969 #define CST4331_LDO_RF 0x00000008
1970 #define CST4331_LDO_PAR 0x00000010
1971
1972 /* 4315 resource */
1973 #define RES4315_CBUCK_LPOM 1 /* 0x00000002 */
1974 #define RES4315_CBUCK_BURST 2 /* 0x00000004 */
1975 #define RES4315_CBUCK_PWM 3 /* 0x00000008 */
1976 #define RES4315_CLDO_PU 4 /* 0x00000010 */
1977 #define RES4315_PALDO_PU 5 /* 0x00000020 */
1978 #define RES4315_ILP_REQUEST 6 /* 0x00000040 */
1979 #define RES4315_LNLDO1_PU 9 /* 0x00000200 */
1980 #define RES4315_OTP_PU 10 /* 0x00000400 */
1981 #define RES4315_LNLDO2_PU 12 /* 0x00001000 */
1982 #define RES4315_XTAL_PU 13 /* 0x00002000 */
1983 #define RES4315_ALP_AVAIL 14 /* 0x00004000 */
1984 #define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */
1985 #define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */
1986 #define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */
1987 #define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */
1988 #define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */
1989 #define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */
1990 #define RES4315_HT_AVAIL 21 /* 0x00200000 */
1991
1992 /* 4315 chip-specific ChipStatus register bits */
1993 #define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /* gpio [7:6], SDIO CIS selection */
1994 #define CST4315_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
1995 #define CST4315_SPROM_SEL 0x00000001 /* use SPROM, OTP is powered up */
1996 #define CST4315_OTP_SEL 0x00000002 /* use OTP, OTP is powered up */
1997 #define CST4315_OTP_PWRDN 0x00000003 /* use SPROM, OTP is powered down */
1998 #define CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */
1999 #define CST4315_RCAL_VALID 0x00000008
2000 #define CST4315_RCAL_VALUE_MASK 0x000001f0
2001 #define CST4315_RCAL_VALUE_SHIFT 4
2002 #define CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */
2003 #define CST4315_CBUCK_MODE_MASK 0x00000c00
2004 #define CST4315_CBUCK_MODE_BURST 0x00000400
2005 #define CST4315_CBUCK_MODE_LPBURST 0x00000c00
2006
2007 /* 4319 resources */
2008 #define RES4319_CBUCK_LPOM 1 /* 0x00000002 */
2009 #define RES4319_CBUCK_BURST 2 /* 0x00000004 */
2010 #define RES4319_CBUCK_PWM 3 /* 0x00000008 */
2011 #define RES4319_CLDO_PU 4 /* 0x00000010 */
2012 #define RES4319_PALDO_PU 5 /* 0x00000020 */
2013 #define RES4319_ILP_REQUEST 6 /* 0x00000040 */
2014 #define RES4319_LNLDO1_PU 9 /* 0x00000200 */
2015 #define RES4319_OTP_PU 10 /* 0x00000400 */
2016 #define RES4319_LNLDO2_PU 12 /* 0x00001000 */
2017 #define RES4319_XTAL_PU 13 /* 0x00002000 */
2018 #define RES4319_ALP_AVAIL 14 /* 0x00004000 */
2019 #define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */
2020 #define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */
2021 #define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */
2022 #define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */
2023 #define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */
2024 #define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */
2025 #define RES4319_HT_AVAIL 21 /* 0x00200000 */
2026
2027 /* 4319 chip-specific ChipStatus register bits */
2028 #define CST4319_SPI_CPULESSUSB 0x00000001
2029 #define CST4319_SPI_CLK_POL 0x00000002
2030 #define CST4319_SPI_CLK_PH 0x00000008
2031 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */
2032 #define CST4319_SPROM_OTP_SEL_SHIFT 6
2033 #define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
2034 #define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */
2035 #define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */
2036 #define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */
2037 #define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */
2038 #define CST4319_REMAP_SEL_MASK 0x00000600
2039 #define CST4319_ILPDIV_EN 0x00000800
2040 #define CST4319_XTAL_PD_POL 0x00001000
2041 #define CST4319_LPO_SEL 0x00002000
2042 #define CST4319_RES_INIT_MODE 0x0000c000
2043 #define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */
2044 #define CST4319_CBUCK_MODE_MASK 0x00060000
2045 #define CST4319_CBUCK_MODE_BURST 0x00020000
2046 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
2047 #define CST4319_RCAL_VALID 0x01000000
2048 #define CST4319_RCAL_VALUE_MASK 0x3e000000
2049 #define CST4319_RCAL_VALUE_SHIFT 25
2050
2051 #define PMU1_PLL0_CHIPCTL0 0
2052 #define PMU1_PLL0_CHIPCTL1 1
2053 #define PMU1_PLL0_CHIPCTL2 2
2054 #define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
2055 #define CCTL_4319USB_XTAL_SEL_SHIFT 19
2056 #define CCTL_4319USB_48MHZ_PLL_SEL 1
2057 #define CCTL_4319USB_24MHZ_PLL_SEL 2
2058
2059 /* PMU resources for 4336 */
2060 #define RES4336_CBUCK_LPOM 0
2061 #define RES4336_CBUCK_BURST 1
2062 #define RES4336_CBUCK_LP_PWM 2
2063 #define RES4336_CBUCK_PWM 3
2064 #define RES4336_CLDO_PU 4
2065 #define RES4336_DIS_INT_RESET_PD 5
2066 #define RES4336_ILP_REQUEST 6
2067 #define RES4336_LNLDO_PU 7
2068 #define RES4336_LDO3P3_PU 8
2069 #define RES4336_OTP_PU 9
2070 #define RES4336_XTAL_PU 10
2071 #define RES4336_ALP_AVAIL 11
2072 #define RES4336_RADIO_PU 12
2073 #define RES4336_BG_PU 13
2074 #define RES4336_VREG1p4_PU_PU 14
2075 #define RES4336_AFE_PWRSW_PU 15
2076 #define RES4336_RX_PWRSW_PU 16
2077 #define RES4336_TX_PWRSW_PU 17
2078 #define RES4336_BB_PWRSW_PU 18
2079 #define RES4336_SYNTH_PWRSW_PU 19
2080 #define RES4336_MISC_PWRSW_PU 20
2081 #define RES4336_LOGEN_PWRSW_PU 21
2082 #define RES4336_BBPLL_PWRSW_PU 22
2083 #define RES4336_MACPHY_CLKAVAIL 23
2084 #define RES4336_HT_AVAIL 24
2085 #define RES4336_RSVD 25
2086
2087 /* 4336 chip-specific ChipStatus register bits */
2088 #define CST4336_SPI_MODE_MASK 0x00000001
2089 #define CST4336_SPROM_PRESENT 0x00000002
2090 #define CST4336_OTP_PRESENT 0x00000004
2091 #define CST4336_ARMREMAP_0 0x00000008
2092 #define CST4336_ILPDIV_EN_MASK 0x00000010
2093 #define CST4336_ILPDIV_EN_SHIFT 4
2094 #define CST4336_XTAL_PD_POL_MASK 0x00000020
2095 #define CST4336_XTAL_PD_POL_SHIFT 5
2096 #define CST4336_LPO_SEL_MASK 0x00000040
2097 #define CST4336_LPO_SEL_SHIFT 6
2098 #define CST4336_RES_INIT_MODE_MASK 0x00000180
2099 #define CST4336_RES_INIT_MODE_SHIFT 7
2100 #define CST4336_CBUCK_MODE_MASK 0x00000600
2101 #define CST4336_CBUCK_MODE_SHIFT 9
2102
2103 /* 4336 Chip specific PMU ChipControl register bits */
2104 #define PCTL_4336_SERIAL_ENAB (1 << 24)
2105
2106 /* 4330 resources */
2107 #define RES4330_CBUCK_LPOM 0
2108 #define RES4330_CBUCK_BURST 1
2109 #define RES4330_CBUCK_LP_PWM 2
2110 #define RES4330_CBUCK_PWM 3
2111 #define RES4330_CLDO_PU 4
2112 #define RES4330_DIS_INT_RESET_PD 5
2113 #define RES4330_ILP_REQUEST 6
2114 #define RES4330_LNLDO_PU 7
2115 #define RES4330_LDO3P3_PU 8
2116 #define RES4330_OTP_PU 9
2117 #define RES4330_XTAL_PU 10
2118 #define RES4330_ALP_AVAIL 11
2119 #define RES4330_RADIO_PU 12
2120 #define RES4330_BG_PU 13
2121 #define RES4330_VREG1p4_PU_PU 14
2122 #define RES4330_AFE_PWRSW_PU 15
2123 #define RES4330_RX_PWRSW_PU 16
2124 #define RES4330_TX_PWRSW_PU 17
2125 #define RES4330_BB_PWRSW_PU 18
2126 #define RES4330_SYNTH_PWRSW_PU 19
2127 #define RES4330_MISC_PWRSW_PU 20
2128 #define RES4330_LOGEN_PWRSW_PU 21
2129 #define RES4330_BBPLL_PWRSW_PU 22
2130 #define RES4330_MACPHY_CLKAVAIL 23
2131 #define RES4330_HT_AVAIL 24
2132 #define RES4330_5gRX_PWRSW_PU 25
2133 #define RES4330_5gTX_PWRSW_PU 26
2134 #define RES4330_5g_LOGEN_PWRSW_PU 27
2135
2136 /* 4330 chip-specific ChipStatus register bits */
2137 #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */
2138 #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */
2139 #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */
2140 #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */
2141 #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */
2142 #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */
2143 #define CST4330_OTP_PRESENT 0x00000010
2144 #define CST4330_LPO_AUTODET_EN 0x00000020
2145 #define CST4330_ARMREMAP_0 0x00000040
2146 #define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */
2147 #define CST4330_ILPDIV_EN 0x00000100
2148 #define CST4330_LPO_SEL 0x00000200
2149 #define CST4330_RES_INIT_MODE_SHIFT 10
2150 #define CST4330_RES_INIT_MODE_MASK 0x00000c00
2151 #define CST4330_CBUCK_MODE_SHIFT 12
2152 #define CST4330_CBUCK_MODE_MASK 0x00003000
2153 #define CST4330_CBUCK_POWER_OK 0x00004000
2154 #define CST4330_BB_PLL_LOCKED 0x00008000
2155 #define SOCDEVRAM_BP_ADDR 0x1E000000
2156 #define SOCDEVRAM_ARM_ADDR 0x00800000
2157
2158 /* 4330 Chip specific PMU ChipControl register bits */
2159 #define PCTL_4330_SERIAL_ENAB (1 << 24)
2160
2161 /* 4330 Chip specific ChipControl register bits */
2162 #define CCTRL_4330_GPIO_SEL 0x00000001 /* 1=select GPIOs to be muxed out */
2163 #define CCTRL_4330_ERCX_SEL 0x00000002 /* 1=select ERCX BT coex to be muxed out */
2164 #define CCTRL_4330_SDIO_HOST_WAKE 0x00000004 /* SDIO: 1=configure GPIO0 for host wake */
2165 #define CCTRL_4330_JTAG_DISABLE 0x00000008 /* 1=disable JTAG interface on mux'd pins */
2166
2167 /* 4334 resources */
2168 #define RES4334_LPLDO_PU 0
2169 #define RES4334_RESET_PULLDN_DIS 1
2170 #define RES4334_PMU_BG_PU 2
2171 #define RES4334_HSIC_LDO_PU 3
2172 #define RES4334_CBUCK_LPOM_PU 4
2173 #define RES4334_CBUCK_PFM_PU 5
2174 #define RES4334_CLDO_PU 6
2175 #define RES4334_LPLDO2_LVM 7
2176 #define RES4334_LNLDO_PU 8
2177 #define RES4334_LDO3P3_PU 9
2178 #define RES4334_OTP_PU 10
2179 #define RES4334_XTAL_PU 11
2180 #define RES4334_WL_PWRSW_PU 12
2181 #define RES4334_LQ_AVAIL 13
2182 #define RES4334_LOGIC_RET 14
2183 #define RES4334_MEM_SLEEP 15
2184 #define RES4334_MACPHY_RET 16
2185 #define RES4334_WL_CORE_READY 17
2186 #define RES4334_ILP_REQ 18
2187 #define RES4334_ALP_AVAIL 19
2188 #define RES4334_MISC_PWRSW_PU 20
2189 #define RES4334_SYNTH_PWRSW_PU 21
2190 #define RES4334_RX_PWRSW_PU 22
2191 #define RES4334_RADIO_PU 23
2192 #define RES4334_WL_PMU_PU 24
2193 #define RES4334_VCO_LDO_PU 25
2194 #define RES4334_AFE_LDO_PU 26
2195 #define RES4334_RX_LDO_PU 27
2196 #define RES4334_TX_LDO_PU 28
2197 #define RES4334_HT_AVAIL 29
2198 #define RES4334_MACPHY_CLK_AVAIL 30
2199
2200 /* 4334 chip-specific ChipStatus register bits */
2201 #define CST4334_CHIPMODE_MASK 7
2202 #define CST4334_SDIO_MODE 0x00000000
2203 #define CST4334_SPI_MODE 0x00000004
2204 #define CST4334_HSIC_MODE 0x00000006
2205 #define CST4334_BLUSB_MODE 0x00000007
2206 #define CST4334_CHIPMODE_HSIC(cs) (((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE)
2207 #define CST4334_OTP_PRESENT 0x00000010
2208 #define CST4334_LPO_AUTODET_EN 0x00000020
2209 #define CST4334_ARMREMAP_0 0x00000040
2210 #define CST4334_SPROM_PRESENT 0x00000080
2211 #define CST4334_ILPDIV_EN_MASK 0x00000100
2212 #define CST4334_ILPDIV_EN_SHIFT 8
2213 #define CST4334_LPO_SEL_MASK 0x00000200
2214 #define CST4334_LPO_SEL_SHIFT 9
2215 #define CST4334_RES_INIT_MODE_MASK 0x00000C00
2216 #define CST4334_RES_INIT_MODE_SHIFT 10
2217
2218 /* 4334 Chip specific PMU ChipControl register bits */
2219 #define PCTL_4334_GPIO3_ENAB (1 << 3)
2220
2221 /* 4334 Chip control */
2222 #define CCTRL4334_HSIC_LDO_PU (1 << 23)
2223
2224 /* 4324 Chip specific ChipControl1 register bits */
2225 #define CCTRL1_4324_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2226 #define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2227
2228 /* 43143 chip-specific ChipStatus register bits based on Confluence documentation */
2229 /* register contains strap values sampled during POR */
2230 #define CST43143_REMAP_TO_ROM (3 << 0) /* 00=Boot SRAM, 01=Boot ROM, 10=Boot SFLASH */
2231 #define CST43143_SDIO_EN (1 << 2) /* 0 = USB Enab, SDIO pins are GPIO or I2S */
2232 #define CST43143_SDIO_ISO (1 << 3) /* 1 = SDIO isolated */
2233 #define CST43143_USB_CPU_LESS (1 << 4) /* 1 = CPULess mode Enabled */
2234 #define CST43143_CBUCK_MODE (3 << 6) /* Indicates what controller mode CBUCK is in */
2235 #define CST43143_POK_CBUCK (1 << 8) /* 1 = 1.2V CBUCK voltage ready */
2236 #define CST43143_PMU_OVRSPIKE (1 << 9)
2237 #define CST43143_PMU_OVRTEMP (0xF << 10)
2238 #define CST43143_SR_FLL_CAL_DONE (1 << 14)
2239 #define CST43143_USB_PLL_LOCKDET (1 << 15)
2240 #define CST43143_PMU_PLL_LOCKDET (1 << 16)
2241 #define CST43143_CHIPMODE_SDIOD(cs) (((cs) & CST43143_SDIO_EN) != 0) /* SDIO */
2242
2243 /* 43143 Chip specific ChipControl register bits */
2244 /* 00: SECI is disabled (JATG functional), 01: 2 wire, 10: 4 wire */
2245 #define CCTRL_43143_SECI (1<<0)
2246 #define CCTRL_43143_BT_LEGACY (1<<1)
2247 #define CCTRL_43143_I2S_MODE (1<<2) /* 0: SDIO enabled */
2248 #define CCTRL_43143_I2S_MASTER (1<<3) /* 0: I2S MCLK input disabled */
2249 #define CCTRL_43143_I2S_FULL (1<<4) /* 0: I2S SDIN and SPDIF_TX inputs disabled */
2250 #define CCTRL_43143_GSIO (1<<5) /* 0: sFlash enabled */
2251 #define CCTRL_43143_RF_SWCTRL_MASK (7<<6) /* 0: disabled */
2252 #define CCTRL_43143_RF_SWCTRL_0 (1<<6)
2253 #define CCTRL_43143_RF_SWCTRL_1 (2<<6)
2254 #define CCTRL_43143_RF_SWCTRL_2 (4<<6)
2255 #define CCTRL_43143_RF_XSWCTRL (1<<9) /* 0: UART enabled */
2256 #define CCTRL_43143_HOST_WAKE0 (1<<11) /* 1: SDIO separate interrupt output from GPIO4 */
2257 #define CCTRL_43143_HOST_WAKE1 (1<<12) /* 1: SDIO separate interrupt output from GPIO16 */
2258
2259 /* 43143 resources, based on pmu_params.xls V1.19 */
2260 #define RES43143_EXT_SWITCHER_PWM 0 /* 0x00001 */
2261 #define RES43143_XTAL_PU 1 /* 0x00002 */
2262 #define RES43143_ILP_REQUEST 2 /* 0x00004 */
2263 #define RES43143_ALP_AVAIL 3 /* 0x00008 */
2264 #define RES43143_WL_CORE_READY 4 /* 0x00010 */
2265 #define RES43143_BBPLL_PWRSW_PU 5 /* 0x00020 */
2266 #define RES43143_HT_AVAIL 6 /* 0x00040 */
2267 #define RES43143_RADIO_PU 7 /* 0x00080 */
2268 #define RES43143_MACPHY_CLK_AVAIL 8 /* 0x00100 */
2269 #define RES43143_OTP_PU 9 /* 0x00200 */
2270 #define RES43143_LQ_AVAIL 10 /* 0x00400 */
2271
2272 #define PMU43143_XTAL_CORE_SIZE_MASK 0x3F
2273
2274 /* 4313 resources */
2275 #define RES4313_BB_PU_RSRC 0
2276 #define RES4313_ILP_REQ_RSRC 1
2277 #define RES4313_XTAL_PU_RSRC 2
2278 #define RES4313_ALP_AVAIL_RSRC 3
2279 #define RES4313_RADIO_PU_RSRC 4
2280 #define RES4313_BG_PU_RSRC 5
2281 #define RES4313_VREG1P4_PU_RSRC 6
2282 #define RES4313_AFE_PWRSW_RSRC 7
2283 #define RES4313_RX_PWRSW_RSRC 8
2284 #define RES4313_TX_PWRSW_RSRC 9
2285 #define RES4313_BB_PWRSW_RSRC 10
2286 #define RES4313_SYNTH_PWRSW_RSRC 11
2287 #define RES4313_MISC_PWRSW_RSRC 12
2288 #define RES4313_BB_PLL_PWRSW_RSRC 13
2289 #define RES4313_HT_AVAIL_RSRC 14
2290 #define RES4313_MACPHY_CLK_AVAIL_RSRC 15
2291
2292 /* 4313 chip-specific ChipStatus register bits */
2293 #define CST4313_SPROM_PRESENT 1
2294 #define CST4313_OTP_PRESENT 2
2295 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
2296 #define CST4313_SPROM_OTP_SEL_SHIFT 0
2297
2298 /* 4313 Chip specific ChipControl register bits */
2299 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2300
2301 /* PMU respources for 4314 */
2302 #define RES4314_LPLDO_PU 0
2303 #define RES4314_PMU_SLEEP_DIS 1
2304 #define RES4314_PMU_BG_PU 2
2305 #define RES4314_CBUCK_LPOM_PU 3
2306 #define RES4314_CBUCK_PFM_PU 4
2307 #define RES4314_CLDO_PU 5
2308 #define RES4314_LPLDO2_LVM 6
2309 #define RES4314_WL_PMU_PU 7
2310 #define RES4314_LNLDO_PU 8
2311 #define RES4314_LDO3P3_PU 9
2312 #define RES4314_OTP_PU 10
2313 #define RES4314_XTAL_PU 11
2314 #define RES4314_WL_PWRSW_PU 12
2315 #define RES4314_LQ_AVAIL 13
2316 #define RES4314_LOGIC_RET 14
2317 #define RES4314_MEM_SLEEP 15
2318 #define RES4314_MACPHY_RET 16
2319 #define RES4314_WL_CORE_READY 17
2320 #define RES4314_ILP_REQ 18
2321 #define RES4314_ALP_AVAIL 19
2322 #define RES4314_MISC_PWRSW_PU 20
2323 #define RES4314_SYNTH_PWRSW_PU 21
2324 #define RES4314_RX_PWRSW_PU 22
2325 #define RES4314_RADIO_PU 23
2326 #define RES4314_VCO_LDO_PU 24
2327 #define RES4314_AFE_LDO_PU 25
2328 #define RES4314_RX_LDO_PU 26
2329 #define RES4314_TX_LDO_PU 27
2330 #define RES4314_HT_AVAIL 28
2331 #define RES4314_MACPHY_CLK_AVAIL 29
2332
2333 /* 4314 chip-specific ChipStatus register bits */
2334 #define CST4314_OTP_ENABLED 0x00200000
2335
2336 /* 43228 resources */
2337 #define RES43228_NOT_USED 0
2338 #define RES43228_ILP_REQUEST 1
2339 #define RES43228_XTAL_PU 2
2340 #define RES43228_ALP_AVAIL 3
2341 #define RES43228_PLL_EN 4
2342 #define RES43228_HT_PHY_AVAIL 5
2343
2344 /* 43228 chipstatus reg bits */
2345 #define CST43228_ILP_DIV_EN 0x1
2346 #define CST43228_OTP_PRESENT 0x2
2347 #define CST43228_SERDES_REFCLK_PADSEL 0x4
2348 #define CST43228_SDIO_MODE 0x8
2349 #define CST43228_SDIO_OTP_PRESENT 0x10
2350 #define CST43228_SDIO_RESET 0x20
2351
2352 /* 4706 chipstatus reg bits */
2353 #define CST4706_PKG_OPTION (1<<0) /* 0: full-featured package 1: low-cost package */
2354 #define CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */
2355 #define CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2356 #define CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */
2357 #define CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */
2358
2359 /* 4706 flashstrconfig reg bits */
2360 #define FLSTRCF4706_MASK 0x000000ff
2361 #define FLSTRCF4706_SF1 0x00000001 /* 2nd serial flash present */
2362 #define FLSTRCF4706_PF1 0x00000002 /* 2nd parallel flash present */
2363 #define FLSTRCF4706_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
2364 #define FLSTRCF4706_NF1 0x00000008 /* 2nd NAND flash present */
2365 #define FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /* Valid value mask */
2366 #define FLSTRCF4706_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
2367 #define FLSTRCF4706_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
2368 #define FLSTRCF4706_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
2369 #define FLSTRCF4706_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
2370 #define FLSTRCF4706_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
2371 #define FLSTRCF4706_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
2372 #define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
2373
2374 /* 4360 Chip specific ChipControl register bits */
2375 #define CCTRL4360_I2C_MODE (1 << 0)
2376 #define CCTRL4360_UART_MODE (1 << 1)
2377 #define CCTRL4360_SECI_MODE (1 << 2)
2378 #define CCTRL4360_BTSWCTRL_MODE (1 << 3)
2379 #define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4)
2380 #define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5)
2381 #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6)
2382 #define CCTRL4360_EXTRA_GPIO_MODE (1 << 7)
2383 #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8)
2384 #define CCTRL4360_BT_LGCY_MODE (1 << 9)
2385 #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21)
2386 #define CCTRL4360_SECI_ON_GPIO01 (1 << 24)
2387
2388 /* 4360 Chip specific Regulator Control register bits */
2389 #define RCTRL4360_RFLDO_PWR_DOWN (1 << 1)
2390
2391 /* 4360 PMU resources and chip status bits */
2392 #define RES4360_REGULATOR 0
2393 #define RES4360_ILP_AVAIL 1
2394 #define RES4360_ILP_REQ 2
2395 #define RES4360_XTAL_LDO_PU 3
2396 #define RES4360_XTAL_PU 4
2397 #define RES4360_ALP_AVAIL 5
2398 #define RES4360_BBPLLPWRSW_PU 6
2399 #define RES4360_HT_AVAIL 7
2400 #define RES4360_OTP_PU 8
2401
2402 #define CST4360_XTAL_40MZ 0x00000001
2403 #define CST4360_SFLASH 0x00000002
2404 #define CST4360_SPROM_PRESENT 0x00000004
2405 #define CST4360_SFLASH_TYPE 0x00000004
2406 #define CST4360_OTP_ENABLED 0x00000008
2407 #define CST4360_REMAP_ROM 0x00000010
2408 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060
2409 #define CST4360_RSRC_INIT_MODE_SHIFT 5
2410 #define CST4360_ILP_DIVEN 0x00000080
2411 #define CST4360_MODE_USB 0x00000100
2412 #define CST4360_SPROM_SIZE_MASK 0x00000600
2413 #define CST4360_SPROM_SIZE_SHIFT 9
2414 #define CST4360_BBPLL_LOCK 0x00000800
2415 #define CST4360_AVBBPLL_LOCK 0x00001000
2416 #define CST4360_USBBBPLL_LOCK 0x00002000
2417 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \
2418 CST4360_RSRC_INIT_MODE_SHIFT)
2419
2420
2421 /* defines to detect active host interface in use */
2422 #define CHIP_HOSTIF_PCIEMODE 0x1
2423 #define CHIP_HOSTIF_USBMODE 0x2
2424 #define CHIP_HOSTIF_SDIOMODE 0x4
2425 #define CHIP_HOSTIF_PCIE(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE)
2426 #define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE)
2427 #define CHIP_HOSTIF_SDIO(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE)
2428
2429 /* 4335 resources */
2430 #define RES4335_LPLDO_PO 0
2431 #define RES4335_PMU_BG_PU 1
2432 #define RES4335_PMU_SLEEP 2
2433 #define RES4335_RSVD_3 3
2434 #define RES4335_CBUCK_LPOM_PU 4
2435 #define RES4335_CBUCK_PFM_PU 5
2436 #define RES4335_RSVD_6 6
2437 #define RES4335_RSVD_7 7
2438 #define RES4335_LNLDO_PU 8
2439 #define RES4335_XTALLDO_PU 9
2440 #define RES4335_LDO3P3_PU 10
2441 #define RES4335_OTP_PU 11
2442 #define RES4335_XTAL_PU 12
2443 #define RES4335_SR_CLK_START 13
2444 #define RES4335_LQ_AVAIL 14
2445 #define RES4335_LQ_START 15
2446 #define RES4335_RSVD_16 16
2447 #define RES4335_WL_CORE_RDY 17
2448 #define RES4335_ILP_REQ 18
2449 #define RES4335_ALP_AVAIL 19
2450 #define RES4335_MINI_PMU 20
2451 #define RES4335_RADIO_PU 21
2452 #define RES4335_SR_CLK_STABLE 22
2453 #define RES4335_SR_SAVE_RESTORE 23
2454 #define RES4335_SR_PHY_PWRSW 24
2455 #define RES4335_SR_VDDM_PWRSW 25
2456 #define RES4335_SR_SUBCORE_PWRSW 26
2457 #define RES4335_SR_SLEEP 27
2458 #define RES4335_HT_START 28
2459 #define RES4335_HT_AVAIL 29
2460 #define RES4335_MACPHY_CLKAVAIL 30
2461
2462 /* 4335 Chip specific ChipStatus register bits */
2463 #define CST4335_SPROM_MASK 0x00000020
2464 #define CST4335_SFLASH_MASK 0x00000040
2465 #define CST4335_RES_INIT_MODE_SHIFT 7
2466 #define CST4335_RES_INIT_MODE_MASK 0x00000180
2467 #define CST4335_CHIPMODE_MASK 0xF
2468 #define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */
2469 #define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */
2470 #define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) /* HSIC || USBDA */
2471 #define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */
2472
2473 /* 4335 Chip specific ChipControl1 register bits */
2474 #define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2475 #define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2476
2477 #define CR4_RAM_BASE (0x180000)
2478 #define PATCHTBL_SIZE (0x800)
2479
2480 /* 4335 chip OTP present & OTP select bits. */
2481 #define SPROM4335_OTP_SELECT 0x00000010
2482 #define SPROM4335_OTP_PRESENT 0x00000020
2483
2484 /* 4335 GCI specific bits. */
2485 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24)
2486 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25
2487 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770
2488
2489 /* SFLASH clkdev specific bits. */
2490 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000
2491 #define CC4335_SFLASH_CLKDIV_SHIFT 25
2492
2493 /* 4335 OTP bits for SFLASH. */
2494 #define CC4335_SROM_OTP_SFLASH 40
2495 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1
2496 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2
2497 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C
2498 #define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2
2499
2500 /* 4335 resources--END */
2501
2502 /* 4345 ChipID bits */
2503 #define CID4345_REV_TC0 0
2504 #define CID4345_REV_A0 1
2505
2506 /* 4345 Chip specific ChipStatus register bits */
2507 #define CST4345_SPROM_MASK 0x00000020
2508 #define CST4345_SFLASH_MASK 0x00000040
2509 #define CST4345_RES_INIT_MODE_SHIFT 7
2510 #define CST4345_RES_INIT_MODE_MASK 0x00000180
2511 #define CST4345_CHIPMODE_MASK 0x4000F
2512 #define CST4345_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */
2513 #define CST4345_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */
2514 #define CST4345_CHIPMODE_HSIC(cs) (((cs) & (1 << 2)) != 0) /* HSIC */
2515 #define CST4345_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */
2516 #define CST4345_CHIPMODE_USB20D(cs) (((cs) & (1 << 18)) != 0) /* USBDA */
2517
2518 /* 4350 Chipcommon ChipStatus bits */
2519 #define CST4350_SDIO_MODE 0x00000001
2520 #define CST4350_HSIC20D_MODE 0x00000002
2521 #define CST4350_BP_ON_HSIC_CLK 0x00000004
2522 #define CST4350_PCIE_MODE 0x00000008
2523 #define CST4350_USB20D_MODE 0x00000010
2524 #define CST4350_USB30D_MODE 0x00000020
2525 #define CST4350_SPROM_PRESENT 0x00000040
2526 #define CST4350_RSRC_INIT_MODE_0 0x00000080
2527 #define CST4350_RSRC_INIT_MODE_1 0x00000100
2528 #define CST4350_SEL0_SDIO 0x00000200
2529 #define CST4350_SEL1_SDIO 0x00000400
2530 #define CST4350_SDIO_PAD_MODE 0x00000800
2531 #define CST4350_BBPLL_LOCKED 0x00001000
2532 #define CST4350_USBPLL_LOCKED 0x00002000
2533 #define CST4350_LINE_STATE 0x0000C000
2534 #define CST4350_SERDES_PIPE_PLLLOCK 0x00010000
2535 #define CST4350_BT_READY 0x00020000
2536 #define CST4350_SFLASH_PRESENT 0x00040000
2537 #define CST4350_CPULESS_ENABLE 0x00080000
2538 #define CST4350_STRAP_HOST_IFC_1 0x00100000
2539 #define CST4350_STRAP_HOST_IFC_2 0x00200000
2540 #define CST4350_STRAP_HOST_IFC_3 0x00400000
2541 #define CST4350_RAW_SPROM_PRESENT 0x00800000
2542 #define CST4350_APP_CLK_SWITCH_SEL_RDBACK 0x01000000
2543 #define CST4350_RAW_RSRC_INIT_MODE_0 0x02000000
2544 #define CST4350_SDIO_PAD_VDDIO 0x04000000
2545 #define CST4350_GSPI_MODE 0x08000000
2546 #define CST4350_PACKAGE_OPTION 0xF0000000
2547
2548 /* strap_host_ifc strap value */
2549 #define CST4350_HOST_IFC_MASK 0x00700000
2550 #define CST4350_HOST_IFC_SHIFT 20
2551
2552 /* host_ifc raw mode */
2553 #define CST4350_IFC_MODE_SDIOD 0x0
2554 #define CST4350_IFC_MODE_HSIC20D 0x1
2555 #define CST4350_IFC_MODE_HSIC30D 0x2
2556 #define CST4350_IFC_MODE_PCIE 0x3
2557 #define CST4350_IFC_MODE_USB20D 0x4
2558 #define CST4350_IFC_MODE_USB30D 0x5
2559 #define CST4350_IFC_MODE_USB30D_WL 0x6
2560 #define CST4350_IFC_MODE_USB30D_BT 0x7
2561
2562 #define CST4350_IFC_MODE(cs) ((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT)
2563
2564 #define CST4350_CHIPMODE_SDIOD(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD))
2565 #define CST4350_CHIPMODE_USB20D(cs) ((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D))
2566 #define CST4350_CHIPMODE_HSIC20D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D))
2567 #define CST4350_CHIPMODE_HSIC30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D))
2568 #define CST4350_CHIPMODE_USB30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D))
2569 #define CST4350_CHIPMODE_USB30D_WL(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL))
2570 #define CST4350_CHIPMODE_PCIE(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_PCIE))
2571
2572 /* 4350 PMU resources */
2573 #define RES4350_LPLDO_PU 0
2574 #define RES4350_PMU_BG_PU 1
2575 #define RES4350_PMU_SLEEP 2
2576 #define RES4350_RSVD_3 3
2577 #define RES4350_CBUCK_LPOM_PU 4
2578 #define RES4350_CBUCK_PFM_PU 5
2579 #define RES4350_COLD_START_WAIT 6
2580 #define RES4350_RSVD_7 7
2581 #define RES4350_LNLDO_PU 8
2582 #define RES4350_XTALLDO_PU 9
2583 #define RES4350_LDO3P3_PU 10
2584 #define RES4350_OTP_PU 11
2585 #define RES4350_XTAL_PU 12
2586 #define RES4350_SR_CLK_START 13
2587 #define RES4350_LQ_AVAIL 14
2588 #define RES4350_LQ_START 15
2589 #define RES4350_RSVD_16 16
2590 #define RES4350_WL_CORE_RDY 17
2591 #define RES4350_ILP_REQ 18
2592 #define RES4350_ALP_AVAIL 19
2593 #define RES4350_MINI_PMU 20
2594 #define RES4350_RADIO_PU 21
2595 #define RES4350_SR_CLK_STABLE 22
2596 #define RES4350_SR_SAVE_RESTORE 23
2597 #define RES4350_SR_PHY_PWRSW 24
2598 #define RES4350_SR_VDDM_PWRSW 25
2599 #define RES4350_SR_SUBCORE_PWRSW 26
2600 #define RES4350_SR_SLEEP 27
2601 #define RES4350_HT_START 28
2602 #define RES4350_HT_AVAIL 29
2603 #define RES4350_MACPHY_CLKAVAIL 30
2604
2605 #define MUXENAB4350_UART_MASK (0x0000000f)
2606 #define MUXENAB4350_UART_SHIFT 0
2607 #define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */
2608 #define MUXENAB4350_HOSTWAKE_SHIFT 4
2609
2610
2611 /* 4350 GCI function sel values */
2612 #define CC4350_FNSEL_HWDEF (0)
2613 #define CC4350_FNSEL_SAMEASPIN (1)
2614 #define CC4350_FNSEL_UART (2)
2615 #define CC4350_FNSEL_SFLASH (3)
2616 #define CC4350_FNSEL_SPROM (4)
2617 #define CC4350_FNSEL_I2C (5)
2618 #define CC4350_FNSEL_MISC0 (6)
2619 #define CC4350_FNSEL_GCI (7)
2620 #define CC4350_FNSEL_MISC1 (8)
2621 #define CC4350_FNSEL_MISC2 (9)
2622 #define CC4350_FNSEL_PWDOG (10)
2623 #define CC4350_FNSEL_IND (12)
2624 #define CC4350_FNSEL_PDN (13)
2625 #define CC4350_FNSEL_PUP (14)
2626 #define CC4350_FNSEL_TRISTATE (15)
2627
2628 /* 4350 GPIO */
2629 #define CC4350_PIN_GPIO_00 (0)
2630 #define CC4350_PIN_GPIO_01 (1)
2631 #define CC4350_PIN_GPIO_02 (2)
2632 #define CC4350_PIN_GPIO_03 (3)
2633 #define CC4350_PIN_GPIO_04 (4)
2634 #define CC4350_PIN_GPIO_05 (5)
2635 #define CC4350_PIN_GPIO_06 (6)
2636 #define CC4350_PIN_GPIO_07 (7)
2637 #define CC4350_PIN_GPIO_08 (8)
2638 #define CC4350_PIN_GPIO_09 (9)
2639 #define CC4350_PIN_GPIO_10 (10)
2640 #define CC4350_PIN_GPIO_11 (11)
2641 #define CC4350_PIN_GPIO_12 (12)
2642 #define CC4350_PIN_GPIO_13 (13)
2643 #define CC4350_PIN_GPIO_14 (14)
2644 #define CC4350_PIN_GPIO_15 (15)
2645
2646 #define CC2_4350_PHY_PWRSW_UPTIME_MASK (0xf << 0)
2647 #define CC2_4350_PHY_PWRSW_UPTIME_SHIFT (0)
2648 #define CC2_4350_VDDM_PWRSW_UPDELAY_MASK (0xf << 4)
2649 #define CC2_4350_VDDM_PWRSW_UPDELAY_SHIFT (4)
2650 #define CC2_4350_VDDM_PWRSW_UPTIME_MASK (0xf << 8)
2651 #define CC2_4350_VDDM_PWRSW_UPTIME_SHIFT (8)
2652 #define CC2_4350_SBC_PWRSW_DNDELAY_MASK (0x3 << 12)
2653 #define CC2_4350_SBC_PWRSW_DNDELAY_SHIFT (12)
2654 #define CC2_4350_PHY_PWRSW_DNDELAY_MASK (0x3 << 14)
2655 #define CC2_4350_PHY_PWRSW_DNDELAY_SHIFT (14)
2656 #define CC2_4350_VDDM_PWRSW_DNDELAY_MASK (0x3 << 16)
2657 #define CC2_4350_VDDM_PWRSW_DNDELAY_SHIFT (16)
2658 #define CC2_4350_VDDM_PWRSW_EN_MASK (1 << 20)
2659 #define CC2_4350_VDDM_PWRSW_EN_SHIFT (20)
2660 #define CC2_4350_MEMLPLDO_PWRSW_EN_MASK (1 << 21)
2661 #define CC2_4350_MEMLPLDO_PWRSW_EN_SHIFT (21)
2662 #define CC2_4350_SDIO_AOS_WAKEUP_MASK (1 << 24)
2663 #define CC2_4350_SDIO_AOS_WAKEUP_SHIFT (24)
2664
2665 /* Applies to 4335/4350/4345 */
2666 #define CC3_SR_CLK_SR_MEM_MASK (1 << 0)
2667 #define CC3_SR_CLK_SR_MEM_SHIFT (0)
2668 #define CC3_SR_BIT1_TBD_MASK (1 << 1)
2669 #define CC3_SR_BIT1_TBD_SHIFT (1)
2670 #define CC3_SR_ENGINE_ENABLE_MASK (1 << 2)
2671 #define CC3_SR_ENGINE_ENABLE_SHIFT (2)
2672 #define CC3_SR_BIT3_TBD_MASK (1 << 3)
2673 #define CC3_SR_BIT3_TBD_SHIFT (3)
2674 #define CC3_SR_MINDIV_FAST_CLK_MASK (0xF << 4)
2675 #define CC3_SR_MINDIV_FAST_CLK_SHIFT (4)
2676 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_MASK (1 << 8)
2677 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_SHIFT (8)
2678 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_MASK (1 << 9)
2679 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_SHIFT (9)
2680 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_MASK (1 << 10)
2681 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_SHIFT (10)
2682 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_MASK (1 << 11)
2683 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_SHIFT (11)
2684 #define CC3_SR_NUM_CLK_HIGH_MASK (0x7 << 12)
2685 #define CC3_SR_NUM_CLK_HIGH_SHIFT (12)
2686 #define CC3_SR_BIT15_TBD_MASK (1 << 15)
2687 #define CC3_SR_BIT15_TBD_SHIFT (15)
2688 #define CC3_SR_PHY_FUNC_PIC_MASK (1 << 16)
2689 #define CC3_SR_PHY_FUNC_PIC_SHIFT (16)
2690 #define CC3_SR_BIT17_19_TBD_MASK (0x7 << 17)
2691 #define CC3_SR_BIT17_19_TBD_SHIFT (17)
2692 #define CC3_SR_CHIP_TRIGGER_1_MASK (1 << 20)
2693 #define CC3_SR_CHIP_TRIGGER_1_SHIFT (20)
2694 #define CC3_SR_CHIP_TRIGGER_2_MASK (1 << 21)
2695 #define CC3_SR_CHIP_TRIGGER_2_SHIFT (21)
2696 #define CC3_SR_CHIP_TRIGGER_3_MASK (1 << 22)
2697 #define CC3_SR_CHIP_TRIGGER_3_SHIFT (22)
2698 #define CC3_SR_CHIP_TRIGGER_4_MASK (1 << 23)
2699 #define CC3_SR_CHIP_TRIGGER_4_SHIFT (23)
2700 #define CC3_SR_ALLOW_SBC_FUNC_PIC_MASK (1 << 24)
2701 #define CC3_SR_ALLOW_SBC_FUNC_PIC_SHIFT (24)
2702 #define CC3_SR_BIT25_26_TBD_MASK (0x3 << 25)
2703 #define CC3_SR_BIT25_26_TBD_SHIFT (25)
2704 #define CC3_SR_ALLOW_SBC_STBY_MASK (1 << 27)
2705 #define CC3_SR_ALLOW_SBC_STBY_SHIFT (27)
2706 #define CC3_SR_GPIO_MUX_MASK (0xF << 28)
2707 #define CC3_SR_GPIO_MUX_SHIFT (28)
2708
2709 /* Applies to 4335/4350/4345 */
2710 #define CC4_SR_INIT_ADDR_MASK (0x3FF0000)
2711 #define CC4_4350_SR_ASM_ADDR (0x30)
2712 #define CC4_4335_SR_ASM_ADDR (0x48)
2713 #define CC4_4345_SR_ASM_ADDR (0x48)
2714 #define CC4_SR_INIT_ADDR_SHIFT (16)
2715
2716 #define CC4_4350_EN_SR_CLK_ALP_MASK (1 << 30)
2717 #define CC4_4350_EN_SR_CLK_ALP_SHIFT (30)
2718 #define CC4_4350_EN_SR_CLK_HT_MASK (1 << 31)
2719 #define CC4_4350_EN_SR_CLK_HT_SHIFT (31)
2720
2721 #define VREG4_4350_MEMLPDO_PU_MASK (1 << 31)
2722 #define VREG4_4350_MEMLPDO_PU_SHIFT 31
2723
2724 #define CC6_4350_PCIE_CLKREQ_WAKEUP_MASK (1 << 4)
2725 #define CC6_4350_PCIE_CLKREQ_WAKEUP_SHIFT (4)
2726 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6)
2727 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_SHIFT (6)
2728
2729 /* GCI chipcontrol register indices */
2730 #define CC_GCI_CHIPCTRL_00 (0)
2731 #define CC_GCI_CHIPCTRL_01 (1)
2732 #define CC_GCI_CHIPCTRL_02 (2)
2733 #define CC_GCI_CHIPCTRL_03 (3)
2734 #define CC_GCI_CHIPCTRL_04 (4)
2735 #define CC_GCI_CHIPCTRL_05 (5)
2736 #define CC_GCI_CHIPCTRL_06 (6)
2737 #define CC_GCI_06_JTAG_SEL_SHIFT 4
2738 #define CC_GCI_06_JTAG_SEL_MASK (1 << 4)
2739 #define CC_GCI_CHIPCTRL_07 (7)
2740 #define CC_GCI_CHIPCTRL_08 (8)
2741 #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12)
2742 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8)
2743
2744 /* 4345 PMU resources */
2745 #define RES4345_LPLDO_PU 0
2746 #define RES4345_PMU_BG_PU 1
2747 #define RES4345_PMU_SLEEP 2
2748 #define RES4345_HSICLDO_PU 3
2749 #define RES4345_CBUCK_LPOM_PU 4
2750 #define RES4345_CBUCK_PFM_PU 5
2751 #define RES4345_COLD_START_WAIT 6
2752 #define RES4345_RSVD_7 7
2753 #define RES4345_LNLDO_PU 8
2754 #define RES4345_XTALLDO_PU 9
2755 #define RES4345_LDO3P3_PU 10
2756 #define RES4345_OTP_PU 11
2757 #define RES4345_XTAL_PU 12
2758 #define RES4345_SR_CLK_START 13
2759 #define RES4345_LQ_AVAIL 14
2760 #define RES4345_LQ_START 15
2761 #define RES4345_PERST_OVR 16
2762 #define RES4345_WL_CORE_RDY 17
2763 #define RES4345_ILP_REQ 18
2764 #define RES4345_ALP_AVAIL 19
2765 #define RES4345_MINI_PMU 20
2766 #define RES4345_RADIO_PU 21
2767 #define RES4345_SR_CLK_STABLE 22
2768 #define RES4345_SR_SAVE_RESTORE 23
2769 #define RES4345_SR_PHY_PWRSW 24
2770 #define RES4345_SR_VDDM_PWRSW 25
2771 #define RES4345_SR_SUBCORE_PWRSW 26
2772 #define RES4345_SR_SLEEP 27
2773 #define RES4345_HT_START 28
2774 #define RES4345_HT_AVAIL 29
2775 #define RES4345_MACPHY_CLK_AVAIL 30
2776
2777 /* 4335 pins
2778 * note: only the values set as default/used are added here.
2779 */
2780 #define CC4335_PIN_GPIO_00 (0)
2781 #define CC4335_PIN_GPIO_01 (1)
2782 #define CC4335_PIN_GPIO_02 (2)
2783 #define CC4335_PIN_GPIO_03 (3)
2784 #define CC4335_PIN_GPIO_04 (4)
2785 #define CC4335_PIN_GPIO_05 (5)
2786 #define CC4335_PIN_GPIO_06 (6)
2787 #define CC4335_PIN_GPIO_07 (7)
2788 #define CC4335_PIN_GPIO_08 (8)
2789 #define CC4335_PIN_GPIO_09 (9)
2790 #define CC4335_PIN_GPIO_10 (10)
2791 #define CC4335_PIN_GPIO_11 (11)
2792 #define CC4335_PIN_GPIO_12 (12)
2793 #define CC4335_PIN_GPIO_13 (13)
2794 #define CC4335_PIN_GPIO_14 (14)
2795 #define CC4335_PIN_GPIO_15 (15)
2796 #define CC4335_PIN_SDIO_CLK (16)
2797 #define CC4335_PIN_SDIO_CMD (17)
2798 #define CC4335_PIN_SDIO_DATA0 (18)
2799 #define CC4335_PIN_SDIO_DATA1 (19)
2800 #define CC4335_PIN_SDIO_DATA2 (20)
2801 #define CC4335_PIN_SDIO_DATA3 (21)
2802 #define CC4335_PIN_RF_SW_CTRL_6 (22)
2803 #define CC4335_PIN_RF_SW_CTRL_7 (23)
2804 #define CC4335_PIN_RF_SW_CTRL_8 (24)
2805 #define CC4335_PIN_RF_SW_CTRL_9 (25)
2806
2807 /* 4335 GCI function sel values
2808 */
2809 #define CC4335_FNSEL_HWDEF (0)
2810 #define CC4335_FNSEL_SAMEASPIN (1)
2811 #define CC4335_FNSEL_GPIO0 (2)
2812 #define CC4335_FNSEL_GPIO1 (3)
2813 #define CC4335_FNSEL_GCI0 (4)
2814 #define CC4335_FNSEL_GCI1 (5)
2815 #define CC4335_FNSEL_UART (6)
2816 #define CC4335_FNSEL_SFLASH (7)
2817 #define CC4335_FNSEL_SPROM (8)
2818 #define CC4335_FNSEL_MISC0 (9)
2819 #define CC4335_FNSEL_MISC1 (10)
2820 #define CC4335_FNSEL_MISC2 (11)
2821 #define CC4335_FNSEL_IND (12)
2822 #define CC4335_FNSEL_PDN (13)
2823 #define CC4335_FNSEL_PUP (14)
2824 #define CC4335_FNSEL_TRI (15)
2825
2826 /* find the 4 bit mask given the bit position */
2827 #define GCIMASK(pos) (((uint32)0xF) << pos)
2828
2829 /* get the value which can be used to directly OR with chipcontrol reg */
2830 #define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos))
2831
2832 /* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic
2833 * for now only UART for bootloader and sdio host wakeup.
2834 */
2835 #define MUXENAB4335_UART_MASK (0x0000000f)
2836 #define MUXENAB4335_UART_SHIFT 0
2837 #define MUXENAB4335_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */
2838 #define MUXENAB4335_HOSTWAKE_SHIFT 4
2839
2840 #define MUXENAB4335_GETIX(val, name) \
2841 ((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1)
2842
2843 /*
2844 * Maximum delay for the PMU state transition in us.
2845 * This is an upper bound intended for spinwaits etc.
2846 */
2847 #define PMU_MAX_TRANSITION_DLY 20000
2848
2849 /* PMU resource up transition time in ILP cycles */
2850 #define PMURES_UP_TRANSITION 2
2851
2852 /*
2853 * Information from BT to WLAN over eci_inputlo, eci_inputmi &
2854 * eci_inputhi register. Rev >=21
2855 */
2856 /* Fields in eci_inputlo register - [0:31] */
2857 #define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */
2858 #define ECI_INLO_TASKTYPE_SHIFT 0
2859 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */
2860 #define ECI_INLO_PKTDUR_SHIFT 4
2861 #define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */
2862 #define ECI_INLO_ROLE_SHIFT 8
2863 #define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */
2864 #define ECI_INLO_MLP_SHIFT 9
2865 #define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */
2866 #define ECI_INLO_TXPWR_SHIFT 12
2867 #define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */
2868 #define ECI_INLO_RSSI_SHIFT 20
2869 #define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */
2870 #define ECI_INLO_VAD_SHIFT 28
2871
2872 /*
2873 * Register eci_inputlo bitfield values.
2874 * - BT packet type information bits [7:0]
2875 */
2876 /* [3:0] - Task (link) type */
2877 #define BT_ACL 0x00
2878 #define BT_SCO 0x01
2879 #define BT_eSCO 0x02
2880 #define BT_A2DP 0x03
2881 #define BT_SNIFF 0x04
2882 #define BT_PAGE_SCAN 0x05
2883 #define BT_INQUIRY_SCAN 0x06
2884 #define BT_PAGE 0x07
2885 #define BT_INQUIRY 0x08
2886 #define BT_MSS 0x09
2887 #define BT_PARK 0x0a
2888 #define BT_RSSISCAN 0x0b
2889 #define BT_MD_ACL 0x0c
2890 #define BT_MD_eSCO 0x0d
2891 #define BT_SCAN_WITH_SCO_LINK 0x0e
2892 #define BT_SCAN_WITHOUT_SCO_LINK 0x0f
2893 /* [7:4] = packet duration code */
2894 /* [8] - Master / Slave */
2895 #define BT_MASTER 0
2896 #define BT_SLAVE 1
2897 /* [11:9] - multi-level priority */
2898 #define BT_LOWEST_PRIO 0x0
2899 #define BT_HIGHEST_PRIO 0x3
2900 /* [19:12] - BT transmit power */
2901 /* [27:20] - BT RSSI */
2902 /* [28] - VAD silence */
2903 /* [31:29] - Undefined */
2904 /* Register eci_inputmi values - [32:63] - none defined */
2905 /* [63:32] - Undefined */
2906
2907 /* Information from WLAN to BT over eci_output register. */
2908 /* Fields in eci_output register - [0:31] */
2909 #define ECI48_OUT_MASKMAGIC_HIWORD 0x55550000
2910 #define ECI_OUT_CHANNEL_MASK(ccrev) ((ccrev) < 35 ? 0xf : (ECI48_OUT_MASKMAGIC_HIWORD | 0xf000))
2911 #define ECI_OUT_CHANNEL_SHIFT(ccrev) ((ccrev) < 35 ? 0 : 12)
2912 #define ECI_OUT_BW_MASK(ccrev) ((ccrev) < 35 ? 0x70 : (ECI48_OUT_MASKMAGIC_HIWORD | 0xe00))
2913 #define ECI_OUT_BW_SHIFT(ccrev) ((ccrev) < 35 ? 4 : 9)
2914 #define ECI_OUT_ANTENNA_MASK(ccrev) ((ccrev) < 35 ? 0x80 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x100))
2915 #define ECI_OUT_ANTENNA_SHIFT(ccrev) ((ccrev) < 35 ? 7 : 8)
2916 #define ECI_OUT_SIMUL_TXRX_MASK(ccrev) \
2917 ((ccrev) < 35 ? 0x10000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x80))
2918 #define ECI_OUT_SIMUL_TXRX_SHIFT(ccrev) ((ccrev) < 35 ? 16 : 7)
2919 #define ECI_OUT_FM_DISABLE_MASK(ccrev) \
2920 ((ccrev) < 35 ? 0x40000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x40))
2921 #define ECI_OUT_FM_DISABLE_SHIFT(ccrev) ((ccrev) < 35 ? 18 : 6)
2922
2923 /* Indicate control of ECI bits between s/w and dot11mac.
2924 * 0 => FW control, 1=> MAC/ucode control
2925
2926 * Current assignment (ccrev >= 35):
2927 * 0 - TxConf (ucode)
2928 * 38 - FM disable (wl)
2929 * 39 - Allow sim rx (ucode)
2930 * 40 - Num antennas (wl)
2931 * 43:41 - WLAN channel exclusion BW (wl)
2932 * 47:44 - WLAN channel (wl)
2933 *
2934 * (ccrev < 35)
2935 * 15:0 - wl
2936 * 16 -
2937 * 18 - FM disable
2938 * 30 - wl interrupt
2939 * 31 - ucode interrupt
2940 * others - unassigned (presumed to be with dot11mac/ucode)
2941 */
2942 #define ECI_MACCTRL_BITS 0xbffb0000
2943 #define ECI_MACCTRLLO_BITS 0x1
2944 #define ECI_MACCTRLHI_BITS 0xFF
2945
2946 /* SECI configuration */
2947 #define SECI_MODE_UART 0x0
2948 #define SECI_MODE_SECI 0x1
2949 #define SECI_MODE_LEGACY_3WIRE_BT 0x2
2950 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3
2951 #define SECI_MODE_HALF_SECI 0x4
2952
2953 #define SECI_RESET (1 << 0)
2954 #define SECI_RESET_BAR_UART (1 << 1)
2955 #define SECI_ENAB_SECI_ECI (1 << 2)
2956 #define SECI_ENAB_SECIOUT_DIS (1 << 3)
2957 #define SECI_MODE_MASK 0x7
2958 #define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */
2959 #define SECI_UPD_SECI (1 << 7)
2960
2961 #define SECI_SLIP_ESC_CHAR 0xDB
2962 #define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR
2963 #define SECI_SIGNOFF_1 0
2964 #define SECI_REFRESH_REQ 0xDA
2965
2966 /* seci clk_ctl_st bits */
2967 #define CLKCTL_STS_SECI_CLK_REQ (1 << 8)
2968 #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24)
2969
2970 #define SECI_UART_MSR_CTS_STATE (1 << 0)
2971 #define SECI_UART_MSR_RTS_STATE (1 << 1)
2972 #define SECI_UART_SECI_IN_STATE (1 << 2)
2973 #define SECI_UART_SECI_IN2_STATE (1 << 3)
2974
2975 /* SECI UART LCR/MCR register bits */
2976 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */
2977 #define SECI_UART_LCR_PARITY_EN (1 << 1)
2978 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */
2979 #define SECI_UART_LCR_RX_EN (1 << 3)
2980 #define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */
2981 #define SECI_UART_LCR_TXO_EN (1 << 5)
2982 #define SECI_UART_LCR_RTSO_EN (1 << 6)
2983 #define SECI_UART_LCR_SLIPMODE_EN (1 << 7)
2984 #define SECI_UART_LCR_RXCRC_CHK (1 << 8)
2985 #define SECI_UART_LCR_TXCRC_INV (1 << 9)
2986 #define SECI_UART_LCR_TXCRC_LSBF (1 << 10)
2987 #define SECI_UART_LCR_TXCRC_EN (1 << 11)
2988
2989 #define SECI_UART_MCR_TX_EN (1 << 0)
2990 #define SECI_UART_MCR_PRTS (1 << 1)
2991 #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2)
2992 #define SECI_UART_MCR_HIGHRATE_EN (1 << 3)
2993 #define SECI_UART_MCR_LOOPBK_EN (1 << 4)
2994 #define SECI_UART_MCR_AUTO_RTS (1 << 5)
2995 #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6)
2996 #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7)
2997 #define SECI_UART_MCR_XONOFF_RPT (1 << 9)
2998
2999 /* WLAN channel numbers - used from wifi.h */
3000
3001 /* WLAN BW */
3002 #define ECI_BW_20 0x0
3003 #define ECI_BW_25 0x1
3004 #define ECI_BW_30 0x2
3005 #define ECI_BW_35 0x3
3006 #define ECI_BW_40 0x4
3007 #define ECI_BW_45 0x5
3008 #define ECI_BW_50 0x6
3009 #define ECI_BW_ALL 0x7
3010
3011 /* WLAN - number of antenna */
3012 #define WLAN_NUM_ANT1 TXANT_0
3013 #define WLAN_NUM_ANT2 TXANT_1
3014
3015 #endif /* _SBCHIPC_H */
Tomato firmware and modifications.