release/src-rt-6.x.4708/include/dmemc_core.h

   1 /*
   2  * BCM47XX Denali DDR1/DDR2 and SDR/DDR1 memory controlers.
   3  *
   4  * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: dmemc_core.h 419467 2013-08-21 09:19:48Z $
  19  */
  20
  21 #ifndef _DMEMC_H
  22 #define _DMEMC_H
  23
  24 #ifndef PAD
  25 #define _PADLINE(line)  pad ## line
  26 #define _XSTR(line)     _PADLINE(line)
  27 #define PAD             _XSTR(__LINE__)
  28 #endif  /* PAD */
  29
  30 #ifdef _LANGUAGE_ASSEMBLY
  31
  32 #if     defined(IL_BIGENDIAN) && defined(BCMHND74K)
  33 /* Swapped defines for big-endian code in 74K based chips */
  34
  35 #define DMEMC_CONTROL00         0x004
  36 #define DMEMC_CONTROL01         0x000
  37 #define DMEMC_CONTROL02         0x00c
  38 #define DMEMC_CONTROL03         0x008
  39 #define DMEMC_CONTROL04         0x014
  40 #define DMEMC_CONTROL05         0x010
  41 #define DMEMC_CONTROL06         0x01c
  42 #define DMEMC_CONTROL07         0x018
  43 #define DMEMC_CONTROL08         0x024
  44 #define DMEMC_CONTROL09         0x020
  45 #define DMEMC_CONTROL10         0x02c
  46 #define DMEMC_CONTROL11         0x028
  47 #define DMEMC_CONTROL12         0x034
  48 #define DMEMC_CONTROL13         0x030
  49 #define DMEMC_CONTROL14         0x03c
  50 #define DMEMC_CONTROL15         0x038
  51 #define DMEMC_CONTROL16         0x044
  52 #define DMEMC_CONTROL17         0x040
  53 #define DMEMC_CONTROL18         0x04c
  54 #define DMEMC_CONTROL19         0x048
  55 #define DMEMC_CONTROL20         0x054
  56 #define DMEMC_CONTROL21         0x050
  57 #define DMEMC_CONTROL22         0x05c
  58 #define DMEMC_CONTROL23         0x058
  59 #define DMEMC_CONTROL24         0x064
  60 #define DMEMC_CONTROL25         0x060
  61 #define DMEMC_CONTROL26         0x06c
  62 #define DMEMC_CONTROL27         0x068
  63 #define DMEMC_CONTROL28         0x074
  64 #define DMEMC_CONTROL29         0x070
  65 #define DMEMC_CONTROL30         0x07c
  66 #define DMEMC_CONTROL31         0x078
  67 #define DMEMC_CONTROL32         0x084
  68 #define DMEMC_CONTROL33         0x080
  69 #define DMEMC_CONTROL34         0x08c
  70 #define DMEMC_CONTROL35         0x088
  71 #define DMEMC_CONTROL36         0x094
  72 #define DMEMC_CONTROL37         0x090
  73 #define DMEMC_CONTROL38         0x09c
  74 #define DMEMC_CONTROL39         0x098
  75 #define DMEMC_CONTROL40         0x0a4
  76 #define DMEMC_CONTROL41         0x0a0
  77 #define DMEMC_CONTROL42         0x0ac
  78 #define DMEMC_CONTROL43         0x0a8
  79 #define DMEMC_CONTROL44         0x0b4
  80 #define DMEMC_CONTROL45         0x0b0
  81 #define DMEMC_CONTROL46         0x0bc
  82 #define DMEMC_CONTROL47         0x0b8
  83 #define DMEMC_CONTROL48         0x0c4
  84 #define DMEMC_CONTROL49         0x0c0
  85 #define DMEMC_CONTROL50         0x0cc
  86 #define DMEMC_CONTROL51         0x0c8
  87 #define DMEMC_CONTROL52         0x0d4
  88 #define DMEMC_CONTROL53         0x0d0
  89
  90 #define DMEMC_CLK_CTL_ST        0x1e4
  91 #define DMEMC_DDR_CTRL          0x1e0
  92 #define DMEMC_STAT              0x1f4
  93
  94 #define DMEMC_CONTROL125        0x1f0
  95 #define DMEMC_CONTROL126        0x1fc
  96 #define DMEMC_CONTROL127        0x1f8
  97 #define DMEMC_CONTROL128        0x204
  98 #define DMEMC_CONTROL129        0x200
  99 #define DMEMC_CONTROL130        0x20c
 100 #define DMEMC_CONTROL131        0x208
 101 #define DMEMC_CONTROL132        0x214
 102 #define DMEMC_CONTROL133        0x210
 103 #define DMEMC_CONTROL134        0x21c
 104 #define DMEMC_CONTROL135        0x218
 105 #define DMEMC_CONTROL136        0x224
 106 #define DMEMC_CONTROL137        0x220
 107 #define DMEMC_CONTROL138        0x22c
 108 #define DMEMC_CONTROL139        0x228
 109 #define DMEMC_CONTROL140        0x234
 110 #define DMEMC_CONTROL141        0x230
 111 #define DMEMC_CONTROL142        0x23c
 112 #define DMEMC_CONTROL143        0x238
 113 #define DMEMC_CONTROL144        0x244
 114 #define DMEMC_CONTROL145        0x240
 115 #define DMEMC_CONTROL146        0x24c
 116 #define DMEMC_CONTROL147        0x248
 117 #define DMEMC_CONTROL148        0x254
 118 #define DMEMC_CONTROL149        0x250
 119 #define DMEMC_CONTROL150        0x25c
 120 #define DMEMC_CONTROL151        0x258
 121
 122 #define DMEMC_PVTGROUPA         0x404
 123 #define DMEMC_PVTGROUPB         0x400
 124 #define DMEMC_PVTGROUPC         0x40c
 125 #define DMEMC_PVTGROUPE         0x408
 126 #define DMEMC_PVTGROUPF         0x414
 127 #define DMEMC_PVTGROUPG         0x410
 128 #define DMEMC_PVTGROUPH         0x41c
 129 #define DMEMC_PVTGROUPI         0x418
 130 #define DMEMC_PVTGROUPJ         0x424
 131
 132 #define DMEMC_GPIOSEL           0x804
 133 #define DMEMC_GPIOOUTEN         0x800
 134
 135 #else   /* !IL_BIGENDIAN || !BCMHND74K */
 136
 137 #define DMEMC_CONTROL00         0x000
 138 #define DMEMC_CONTROL01         0x004
 139 #define DMEMC_CONTROL02         0x008
 140 #define DMEMC_CONTROL03         0x00c
 141 #define DMEMC_CONTROL04         0x010
 142 #define DMEMC_CONTROL05         0x014
 143 #define DMEMC_CONTROL06         0x018
 144 #define DMEMC_CONTROL07         0x01c
 145 #define DMEMC_CONTROL08         0x020
 146 #define DMEMC_CONTROL09         0x024
 147 #define DMEMC_CONTROL10         0x028
 148 #define DMEMC_CONTROL11         0x02c
 149 #define DMEMC_CONTROL12         0x030
 150 #define DMEMC_CONTROL13         0x034
 151 #define DMEMC_CONTROL14         0x038
 152 #define DMEMC_CONTROL15         0x03c
 153 #define DMEMC_CONTROL16         0x040
 154 #define DMEMC_CONTROL17         0x044
 155 #define DMEMC_CONTROL18         0x048
 156 #define DMEMC_CONTROL19         0x04c
 157 #define DMEMC_CONTROL20         0x050
 158 #define DMEMC_CONTROL21         0x054
 159 #define DMEMC_CONTROL22         0x058
 160 #define DMEMC_CONTROL23         0x05c
 161 #define DMEMC_CONTROL24         0x060
 162 #define DMEMC_CONTROL25         0x064
 163 #define DMEMC_CONTROL26         0x068
 164 #define DMEMC_CONTROL27         0x06c
 165 #define DMEMC_CONTROL28         0x070
 166 #define DMEMC_CONTROL29         0x074
 167 #define DMEMC_CONTROL30         0x078
 168 #define DMEMC_CONTROL31         0x07c
 169 #define DMEMC_CONTROL32         0x080
 170 #define DMEMC_CONTROL33         0x084
 171 #define DMEMC_CONTROL34         0x088
 172 #define DMEMC_CONTROL35         0x08c
 173 #define DMEMC_CONTROL36         0x090
 174 #define DMEMC_CONTROL37         0x094
 175 #define DMEMC_CONTROL38         0x098
 176 #define DMEMC_CONTROL39         0x09c
 177 #define DMEMC_CONTROL40         0x0a0
 178 #define DMEMC_CONTROL41         0x0a4
 179 #define DMEMC_CONTROL42         0x0a8
 180 #define DMEMC_CONTROL43         0x0ac
 181 #define DMEMC_CONTROL44         0x0b0
 182 #define DMEMC_CONTROL45         0x0b4
 183 #define DMEMC_CONTROL46         0x0b8
 184 #define DMEMC_CONTROL47         0x0bc
 185 #define DMEMC_CONTROL48         0x0c0
 186 #define DMEMC_CONTROL49         0x0c4
 187 #define DMEMC_CONTROL50         0x0c8
 188 #define DMEMC_CONTROL51         0x0cc
 189 #define DMEMC_CONTROL52         0x0d0
 190 #define DMEMC_CONTROL53         0x0d4
 191
 192 #define DMEMC_CLK_CTL_ST        0x1e0
 193 #define DMEMC_DDR_CTRL          0x1e4
 194 #define DMEMC_STAT              0x1f0
 195
 196 #define DMEMC_CONTROL125        0x1f4
 197 #define DMEMC_CONTROL126        0x1f8
 198 #define DMEMC_CONTROL127        0x1fc
 199 #define DMEMC_CONTROL128        0x200
 200 #define DMEMC_CONTROL129        0x204
 201 #define DMEMC_CONTROL130        0x208
 202 #define DMEMC_CONTROL131        0x20c
 203 #define DMEMC_CONTROL132        0x210
 204 #define DMEMC_CONTROL133        0x214
 205 #define DMEMC_CONTROL134        0x218
 206 #define DMEMC_CONTROL135        0x21c
 207 #define DMEMC_CONTROL136        0x220
 208 #define DMEMC_CONTROL137        0x224
 209 #define DMEMC_CONTROL138        0x228
 210 #define DMEMC_CONTROL139        0x22c
 211 #define DMEMC_CONTROL140        0x230
 212 #define DMEMC_CONTROL141        0x234
 213 #define DMEMC_CONTROL142        0x238
 214 #define DMEMC_CONTROL143        0x23c
 215 #define DMEMC_CONTROL144        0x240
 216 #define DMEMC_CONTROL145        0x244
 217 #define DMEMC_CONTROL146        0x248
 218 #define DMEMC_CONTROL147        0x24c
 219 #define DMEMC_CONTROL148        0x250
 220 #define DMEMC_CONTROL149        0x254
 221 #define DMEMC_CONTROL150        0x258
 222 #define DMEMC_CONTROL151        0x25c
 223
 224
 225 #define DMEMC_PVTGROUPA         0x400
 226 #define DMEMC_PVTGROUPB         0x404
 227 #define DMEMC_PVTGROUPC         0x408
 228 #define DMEMC_PVTGROUPE         0x40c
 229 #define DMEMC_PVTGROUPF         0x410
 230 #define DMEMC_PVTGROUPG         0x414
 231 #define DMEMC_PVTGROUPH         0x418
 232 #define DMEMC_PVTGROUPI         0x41c
 233 #define DMEMC_PVTGROUPJ         0x420
 234
 235 #define DMEMC_GPIOSEL           0x800
 236 #define DMEMC_GPIOOUTEN         0x804
 237 #endif  /* IL_BIGENDIAN && BCMHND74K */
 238
 239 #else   /* !_LANGUAGE_ASSEMBLY */
 240
 241 #define DMEMC_MAXREG            151
 242 #define DMEMC_PVTREGS           9
 243
 244 /* DMEMC core registers */
 245 typedef struct dmemcregs {
 246         uint32  control[DMEMC_MAXREG];
 247         uint32  PAD[105];
 248         uint32  pvtgroup[DMEMC_PVTREGS];        /* 0x400 */
 249         uint32  PAD[247];
 250         uint32  gpiosel;                        /* 0x800 */
 251         uint32  gpioouten;                      /* 0x804 */
 252 } _dmemcregs_t;
 253
 254 typedef volatile _dmemcregs_t dmemcregs_t;
 255
 256 #define DMEMS_MAXREG            53
 257
 258 /* DMEMC core registers */
 259 typedef volatile struct dmemsregs {
 260         uint32  control[DMEMS_MAXREG];
 261         uint32  PAD[66];
 262         uint32  clk_ctl_st;                     /* 0x1e0 */
 263         uint32  ddr_ctrl;                       /* 0x1e4 */
 264         uint32  PAD[2];
 265         uint32  stat;                           /* 0x1f0 */
 266         uint32  PAD[386];
 267         uint32  gpiosel;                        /* 0x800 */
 268         uint32  gpioouten;                      /* 0x804 */
 269 } dmemsregs_t;
 270
 271 #endif  /* _LANGUAGE_ASSEMBLY */
 272
 273 #define DMEMC_TABLE_END         0xffffffff
 274
 275 /* Bits in control3 */
 276 #define DMC03_BIST_DATA         0x01000000
 277 #define DMC03_BIST_ADDR         0x00010000
 278
 279 /* Bits in control4 */
 280 #define DMC04_DLLLOCK           0x01000000
 281 #define DMC04_DDR2              0x00010000
 282 #define DMC04_BIST_GO           0x00000001
 283
 284 /* Bits in control09 */
 285 #define DMC09_SREFRESH          0x00010000
 286 #define DMC09_START             0x01000000
 287
 288 /* Bits in control11 */
 289 #define DMC11_BIST_DATA_OK      0x01000000
 290 #define DMC11_BIST_ADDR_OK      0x02000000
 291
 292 /* Bits in control19 */
 293 #define DMC19_ADDRSP_MASK       0x1f000000
 294 #define DMC19_ADDRSP_SHIFT      24
 295
 296 /* Bits in control23 */
 297 #define DMC23_INTMASK_MASK      0xff000000
 298 #define DMC23_INTMASK_SHIFT     24
 299 #define DMC23_INTACK_MASK       0x0000007f
 300
 301 /* Bits in control24 */
 302 #define DMC24_INTSTAT_MASK      0x000000ff
 303
 304 /* Interrupt bits (in control24.status, control23.int_ack and
 305  * control23.int_mask)
 306  */
 307 #define DM_INT_SINGLE_BAD       0x01
 308 #define DM_INT_MULTI_BAD        0x02
 309 #define DM_INT_CMD_ERR          0x04
 310 #define DM_INT_DATA_ERR         0x08
 311 #define DM_INT_INIT_DONE        0x10
 312 #define DM_INT_BIST_DONE        0x20
 313 #define DM_INT_DLL_UNLOCK       0x40
 314 #define DM_INT_ANY              0x80
 315
 316 /* Interrupt bits redefined in revision 2 */
 317 #define DMC132_INTMASK_MASK     0x07ff0000
 318 #define DMC132_INTMASK_SHIFT    16
 319 #define DMC132_INTACK_MASK      0x000003ff
 320
 321 #define DMC133_INTSTAT_MASK     0x000007ff
 322
 323 #define DM2_INT_SINGLE_BAD      (1 << 0)
 324 #define DM2_INT_MULTI_BAD       (1 << 1)
 325 #define DM2_INT_CMD_ERR         (1 << 2)
 326 #define DM2_INT_DATA_ERR        (1 << 3)
 327 #define DM2_INT_INIT_DONE       (1 << 4)
 328 #define DM2_INT_BIST_DONE       (1 << 5)
 329 #define DM2_INT_ODT_CAS3_ERR    (1 << 6)
 330 #define DM2_INT_DQS_ERR         (1 << 7)
 331 #define DM2_INT_DLL_LOCKCHANGE  (1 << 8)
 332 #define DM2_INT_DLLRESYNC_DONE  (1 << 9)
 333 #define DM2_INT_ANY             (1 << 10)
 334
 335 /* Stat bits */
 336 #define DM_STAT_DDR2_CAP        0x0400
 337 #define DM_STAT_DDR1_CAP        0x0200
 338 #define DM_STAT_SDR_CAP         0x0100
 339 #define DM_STAT_DDR2            0x0004
 340 #define DM_STAT_DDR1            0x0002
 341 #define DM_STAT_SDR             0x0001
 342 #define DM_STAT_MASK            0x0007
 343
 344 #endif  /* _SBMEMC_H */