2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #define MAX_OPERANDS 3
23 typedef struct ASMInstr
{
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
42 /* in order to compress the operand type, we use specific operands and
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
72 /* can be ored with any OPT_xxx */
76 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
79 typedef struct Operand
{
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg
; /* register, -1 if none */
106 int8_t reg2
; /* second register, -1 if none */
111 static const uint8_t reg_to_size
[5] = {
120 #define WORD_PREFIX_OPCODE 0x66
122 #define NB_TEST_OPCODES 30
124 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
157 static const uint8_t segment_prefixes
[] = {
166 static const ASMInstr asm_instrs
[] = {
168 #define DEF_ASM_OP0(name, opcode)
169 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
170 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
171 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
172 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
173 #include "i386-asm.h"
179 static const uint16_t op0_codes
[] = {
181 #define DEF_ASM_OP0(x, opcode) opcode,
182 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
183 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
184 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
185 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
186 #include "i386-asm.h"
189 static inline int get_reg_shift(TCCState
*s1
)
193 v
= asm_int_expr(s1
);
208 expect("1, 2, 4 or 8 constant");
215 static int asm_parse_reg(void)
221 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
222 reg
= tok
- TOK_ASM_eax
;
227 expect("32 bit register");
232 static void parse_operand(TCCState
*s1
, Operand
*op
)
246 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
247 reg
= tok
- TOK_ASM_al
;
248 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
250 if ((op
->type
& OP_REG
) && op
->reg
== TREG_EAX
)
252 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_ECX
)
254 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_EDX
)
256 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
258 op
->reg
= tok
- TOK_ASM_dr0
;
259 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
261 op
->reg
= tok
- TOK_ASM_es
;
262 } else if (tok
== TOK_ASM_st
) {
268 if (tok
!= TOK_PPNUM
)
272 if ((unsigned)reg
>= 8 || p
[1] != '\0')
283 error("unknown register");
287 } else if (tok
== '$') {
295 if (op
->e
.v
== (uint8_t)op
->e
.v
)
297 if (op
->e
.v
== (int8_t)op
->e
.v
)
299 if (op
->e
.v
== (uint16_t)op
->e
.v
)
303 /* address(reg,reg2,shift) with all variants */
319 op
->reg
= asm_parse_reg();
324 op
->reg2
= asm_parse_reg();
328 op
->shift
= get_reg_shift(s1
);
333 if (op
->reg
== -1 && op
->reg2
== -1)
339 /* XXX: unify with C code output ? */
340 static void gen_expr32(ExprValue
*pe
)
343 greloc(cur_text_section
, pe
->sym
, ind
, R_386_32
);
347 /* XXX: unify with C code output ? */
348 static void gen_disp32(ExprValue
*pe
)
353 if (sym
->r
== cur_text_section
->sh_num
) {
354 /* same section: we can output an absolute value. Note
355 that the TCC compiler behaves differently here because
356 it always outputs a relocation to ease (future) code
357 elimination in the linker */
358 gen_le32(pe
->v
+ (long)sym
->next
- ind
- 4);
360 greloc(cur_text_section
, sym
, ind
, R_386_PC32
);
364 /* put an empty PC32 relocation */
365 put_elf_reloc(symtab_section
, cur_text_section
,
372 static void gen_le16(int v
)
378 /* generate the modrm operand */
379 static inline void asm_modrm(int reg
, Operand
*op
)
381 int mod
, reg1
, reg2
, sib_reg1
;
383 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
384 g(0xc0 + (reg
<< 3) + op
->reg
);
385 } else if (op
->reg
== -1 && op
->reg2
== -1) {
386 /* displacement only */
387 g(0x05 + (reg
<< 3));
391 /* fist compute displacement encoding */
392 if (sib_reg1
== -1) {
395 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
397 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
402 /* compute if sib byte needed */
406 g(mod
+ (reg
<< 3) + reg1
);
411 reg2
= 4; /* indicate no index */
412 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
418 } else if (mod
== 0x80 || op
->reg
== -1) {
424 static void asm_opcode(TCCState
*s1
, int opcode
)
427 int i
, modrm_index
, reg
, v
, op1
, is_short_jmp
, has_seg_prefix
;
429 Operand ops
[MAX_OPERANDS
], *pop
, seg_prefix
;
430 int op_type
[3]; /* decoded op type */
437 if (tok
== ';' || tok
== TOK_LINEFEED
)
439 if (nb_ops
>= MAX_OPERANDS
) {
440 error("incorrect number of operands");
442 parse_operand(s1
, pop
);
444 if (pop
->type
!= OP_SEG
|| has_seg_prefix
) {
445 error("incorrect prefix");
450 parse_operand(s1
, pop
);
451 if (!(pop
->type
& OP_EA
)) {
452 error("segment prefix must be followed by memory reference");
463 s
= 0; /* avoid warning */
465 /* optimize matching by using a lookup table (no hashing is needed
467 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
469 if (pa
->instr_type
& OPC_FARITH
) {
470 v
= opcode
- pa
->sym
;
471 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
473 } else if (pa
->instr_type
& OPC_ARITH
) {
474 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8 * 4))
477 } else if (pa
->instr_type
& OPC_SHIFT
) {
478 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7 * 4))
481 } else if (pa
->instr_type
& OPC_TEST
) {
482 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
484 } else if (pa
->instr_type
& OPC_B
) {
485 if (!(opcode
>= pa
->sym
&& opcode
<= pa
->sym
+ 3))
488 s
= (opcode
- pa
->sym
) & 3;
489 } else if (pa
->instr_type
& OPC_WL
) {
490 if (!(opcode
>= pa
->sym
&& opcode
<= pa
->sym
+ 2))
492 s
= opcode
- pa
->sym
+ 1;
494 if (pa
->sym
!= opcode
)
497 if (pa
->nb_ops
!= nb_ops
)
499 /* now decode and check each operand */
500 for(i
= 0; i
< nb_ops
; i
++) {
502 op1
= pa
->op_type
[i
];
506 v
= OP_IM8
| OP_IM16
| OP_IM32
;
509 v
= OP_REG8
| OP_REG16
| OP_REG32
;
512 v
= OP_REG16
| OP_REG32
;
515 v
= OP_IM16
| OP_IM32
;
524 if ((ops
[i
].type
& v
) == 0)
527 /* all is matching ! */
532 if (opcode
>= TOK_ASM_pusha
&& opcode
<= TOK_ASM_emms
) {
534 b
= op0_codes
[opcode
- TOK_ASM_pusha
];
540 error("unknown opcode '%s'",
541 get_tok_str(opcode
, NULL
));
544 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
546 for(i
= 0; s
== 3 && i
< nb_ops
; i
++) {
547 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
548 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
551 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
552 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
)))
555 error("cannot infer opcode suffix");
559 /* generate data16 prefix if needed */
561 if (s
== 1 || (pa
->instr_type
& OPC_D16
))
562 g(WORD_PREFIX_OPCODE
);
565 /* now generates the operation */
566 if (pa
->instr_type
& OPC_FWAIT
)
569 g(segment_prefixes
[seg_prefix
.reg
]);
572 if (v
== 0x69 || v
== 0x69) {
573 /* kludge for imul $im, %reg */
576 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
577 v
--; /* int $3 case */
579 } else if ((v
== 0x06 || v
== 0x07)) {
580 if (ops
[0].reg
>= 4) {
581 /* push/pop %fs or %gs */
582 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
584 v
+= ops
[0].reg
<< 3;
587 } else if (v
<= 0x05) {
589 v
+= ((opcode
- TOK_ASM_addb
) >> 2) << 3;
590 } else if ((pa
->instr_type
& (OPC_FARITH
| OPC_MODRM
)) == OPC_FARITH
) {
592 v
+= ((opcode
- pa
->sym
) / 6) << 3;
594 if (pa
->instr_type
& OPC_REG
) {
595 for(i
= 0; i
< nb_ops
; i
++) {
596 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
601 /* mov $im, %reg case */
602 if (pa
->opcode
== 0xb0 && s
>= 1)
605 if (pa
->instr_type
& OPC_B
)
607 if (pa
->instr_type
& OPC_TEST
)
608 v
+= test_bits
[opcode
- pa
->sym
];
609 if (pa
->instr_type
& OPC_SHORTJMP
) {
613 /* see if we can really generate the jump with a byte offset */
617 if (sym
->r
!= cur_text_section
->sh_num
)
619 jmp_disp
= ops
[0].e
.v
+ (long)sym
->next
- ind
- 2;
620 if (jmp_disp
== (int8_t)jmp_disp
) {
621 /* OK to generate jump */
623 ops
[0].e
.v
= jmp_disp
;
626 if (pa
->instr_type
& OPC_JMP
) {
627 /* long jump will be allowed. need to modify the
634 error("invalid displacement");
643 /* search which operand will used for modrm */
645 if (pa
->instr_type
& OPC_SHIFT
) {
646 reg
= (opcode
- pa
->sym
) >> 2;
649 } else if (pa
->instr_type
& OPC_ARITH
) {
650 reg
= (opcode
- pa
->sym
) >> 2;
651 } else if (pa
->instr_type
& OPC_FARITH
) {
652 reg
= (opcode
- pa
->sym
) / 6;
654 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
656 if (pa
->instr_type
& OPC_MODRM
) {
657 /* first look for an ea operand */
658 for(i
= 0;i
< nb_ops
; i
++) {
659 if (op_type
[i
] & OP_EA
)
662 /* then if not found, a register or indirection (shift instructions) */
663 for(i
= 0;i
< nb_ops
; i
++) {
664 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
668 error("bad op table");
672 /* if a register is used in another operand then it is
673 used instead of group */
674 for(i
= 0;i
< nb_ops
; i
++) {
676 if (i
!= modrm_index
&&
677 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
683 asm_modrm(reg
, &ops
[modrm_index
]);
687 if (pa
->opcode
== 0x9a || pa
->opcode
== 0xea) {
688 /* ljmp or lcall kludge */
689 gen_expr32(&ops
[1].e
);
691 error("cannot relocate");
692 gen_le16(ops
[0].e
.v
);
694 for(i
= 0;i
< nb_ops
; i
++) {
696 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM8S
| OP_ADDR
)) {
697 /* if multiple sizes are given it means we must look
699 if (v
== (OP_IM8
| OP_IM16
| OP_IM32
) ||
700 v
== (OP_IM16
| OP_IM32
)) {
708 if (v
& (OP_IM8
| OP_IM8S
)) {
712 } else if (v
& OP_IM16
) {
715 error("cannot relocate");
717 gen_le16(ops
[i
].e
.v
);
719 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
723 gen_disp32(&ops
[i
].e
);
725 gen_expr32(&ops
[i
].e
);
733 #define NB_SAVED_REGS 3
734 #define NB_ASM_REGS 8
736 /* return the constraint priority (we allocate first the lowest
737 numbered constraints) */
738 static inline int constraint_priority(const char *str
)
742 /* we take the lowest priority */
776 error("unknown constraint '%c'", c
);
785 static const char *skip_constraint_modifiers(const char *p
)
787 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
792 #define REG_OUT_MASK 0x01
793 #define REG_IN_MASK 0x02
795 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
797 static void asm_compute_constraints(ASMOperand
*operands
,
798 int nb_operands
, int nb_outputs
,
799 const uint8_t *clobber_regs
,
803 int sorted_op
[MAX_ASM_OPERANDS
];
804 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
806 uint8_t regs_allocated
[NB_ASM_REGS
];
809 for(i
=0;i
<nb_operands
;i
++) {
811 op
->input_index
= -1;
817 /* compute constraint priority and evaluate references to output
818 constraints if input constraints */
819 for(i
=0;i
<nb_operands
;i
++) {
821 str
= op
->constraint
;
822 str
= skip_constraint_modifiers(str
);
823 if (isnum(*str
) || *str
== '[') {
824 /* this is a reference to another constraint */
825 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
826 if ((unsigned)k
>= i
|| i
< nb_outputs
)
827 error("invalid reference in constraint %d ('%s')",
830 if (operands
[k
].input_index
>= 0)
831 error("cannot reference twice the same operand");
832 operands
[k
].input_index
= i
;
835 op
->priority
= constraint_priority(str
);
839 /* sort operands according to their priority */
840 for(i
=0;i
<nb_operands
;i
++)
842 for(i
=0;i
<nb_operands
- 1;i
++) {
843 for(j
=i
+1;j
<nb_operands
;j
++) {
844 p1
= operands
[sorted_op
[i
]].priority
;
845 p2
= operands
[sorted_op
[j
]].priority
;
848 sorted_op
[i
] = sorted_op
[j
];
854 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
856 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
858 regs_allocated
[i
] = 0;
860 /* esp cannot be used */
861 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
862 /* ebp cannot be used yet */
863 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
865 /* allocate registers and generate corresponding asm moves */
866 for(i
=0;i
<nb_operands
;i
++) {
869 str
= op
->constraint
;
870 /* no need to allocate references */
871 if (op
->ref_index
>= 0)
873 /* select if register is used for output, input or both */
874 if (op
->input_index
>= 0) {
875 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
876 } else if (j
< nb_outputs
) {
877 reg_mask
= REG_OUT_MASK
;
879 reg_mask
= REG_IN_MASK
;
891 error("'%c' modifier can only be applied to outputs", c
);
892 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
895 /* allocate both eax and edx */
896 if (is_reg_allocated(TREG_EAX
) ||
897 is_reg_allocated(TREG_EDX
))
901 regs_allocated
[TREG_EAX
] |= reg_mask
;
902 regs_allocated
[TREG_EDX
] |= reg_mask
;
922 if (is_reg_allocated(reg
))
926 /* eax, ebx, ecx or edx */
927 for(reg
= 0; reg
< 4; reg
++) {
928 if (!is_reg_allocated(reg
))
933 /* any general register */
934 for(reg
= 0; reg
< 8; reg
++) {
935 if (!is_reg_allocated(reg
))
940 /* now we can reload in the register */
943 regs_allocated
[reg
] |= reg_mask
;
946 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
952 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
957 /* nothing special to do because the operand is already in
958 memory, except if the pointer itself is stored in a
959 memory variable (VT_LLOCAL case) */
960 /* XXX: fix constant case */
961 /* if it is a reference to a memory zone, it must lie
962 in a register, so we reserve the register in the
963 input registers and a load will be generated
965 if (j
< nb_outputs
|| c
== 'm') {
966 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
967 /* any general register */
968 for(reg
= 0; reg
< 8; reg
++) {
969 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
974 /* now we can reload in the register */
975 regs_allocated
[reg
] |= REG_IN_MASK
;
982 error("asm constraint %d ('%s') could not be satisfied",
986 /* if a reference is present for that operand, we assign it too */
987 if (op
->input_index
>= 0) {
988 operands
[op
->input_index
].reg
= op
->reg
;
989 operands
[op
->input_index
].is_llong
= op
->is_llong
;
993 /* compute out_reg. It is used to store outputs registers to memory
994 locations references by pointers (VT_LLOCAL case) */
996 for(i
=0;i
<nb_operands
;i
++) {
999 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1001 for(reg
= 0; reg
< 8; reg
++) {
1002 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1005 error("could not find free output register for reloading");
1012 /* print sorted constraints */
1014 for(i
=0;i
<nb_operands
;i
++) {
1017 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1019 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1025 printf("out_reg=%d\n", *pout_reg
);
1029 static void subst_asm_operand(CString
*add_str
,
1030 SValue
*sv
, int modifier
)
1032 int r
, reg
, size
, val
;
1036 if ((r
& VT_VALMASK
) == VT_CONST
) {
1037 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n')
1038 cstr_ccat(add_str
, '$');
1040 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
));
1042 cstr_ccat(add_str
, '+');
1048 if (modifier
== 'n')
1050 snprintf(buf
, sizeof(buf
), "%d", sv
->c
.i
);
1051 cstr_cat(add_str
, buf
);
1052 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1053 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", sv
->c
.i
);
1054 cstr_cat(add_str
, buf
);
1055 } else if (r
& VT_LVAL
) {
1056 reg
= r
& VT_VALMASK
;
1057 if (reg
>= VT_CONST
)
1058 error("internal compiler error");
1059 snprintf(buf
, sizeof(buf
), "(%%%s)",
1060 get_tok_str(TOK_ASM_eax
+ reg
, NULL
));
1061 cstr_cat(add_str
, buf
);
1064 reg
= r
& VT_VALMASK
;
1065 if (reg
>= VT_CONST
)
1066 error("internal compiler error");
1068 /* choose register operand size */
1069 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1071 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1075 if (size
== 1 && reg
>= 4)
1078 if (modifier
== 'b') {
1080 error("cannot use byte register");
1082 } else if (modifier
== 'h') {
1084 error("cannot use byte register");
1086 } else if (modifier
== 'w') {
1092 reg
= TOK_ASM_ah
+ reg
;
1095 reg
= TOK_ASM_al
+ reg
;
1098 reg
= TOK_ASM_ax
+ reg
;
1101 reg
= TOK_ASM_eax
+ reg
;
1104 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1105 cstr_cat(add_str
, buf
);
1109 /* generate prolog and epilog code for asm statment */
1110 static void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1111 int nb_outputs
, int is_output
,
1112 uint8_t *clobber_regs
,
1115 uint8_t regs_allocated
[NB_ASM_REGS
];
1118 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1120 /* mark all used registers */
1121 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1122 for(i
= 0; i
< nb_operands
;i
++) {
1125 regs_allocated
[op
->reg
] = 1;
1128 /* generate reg save code */
1129 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1131 if (regs_allocated
[reg
])
1135 /* generate load code */
1136 for(i
= 0; i
< nb_operands
; i
++) {
1139 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1141 /* memory reference case (for both input and
1145 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1147 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1148 /* load value in register */
1149 load(op
->reg
, op
->vt
);
1154 load(TREG_EDX
, &sv
);
1160 /* generate save code */
1161 for(i
= 0 ; i
< nb_outputs
; i
++) {
1164 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1165 if (!op
->is_memory
) {
1168 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1171 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1172 store(op
->reg
, &sv
);
1175 store(op
->reg
, op
->vt
);
1180 store(TREG_EDX
, &sv
);
1185 /* generate reg restore code */
1186 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1188 if (regs_allocated
[reg
])
1194 static void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1199 if (!strcmp(str
, "memory") ||
1202 ts
= tok_alloc(str
, strlen(str
));
1204 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1206 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1209 error("invalid clobber register '%s'", str
);
1211 clobber_regs
[reg
] = 1;