2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #define MAX_OPERANDS 3
24 #define TOK_ASM_first TOK_ASM_clc
25 #define TOK_ASM_last TOK_ASM_emms
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used with OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #ifdef TCC_TARGET_X86_64
41 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
42 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
43 # define OPC_WLX OPC_WLQ
45 # define OPC_WLX OPC_WL
48 #define OPC_GROUP_SHIFT 13
50 /* in order to compress the operand type, we use specific operands and
53 OPT_REG8
=0, /* warning: value is hardcoded from TOK_ASM_xxx */
54 OPT_REG16
, /* warning: value is hardcoded from TOK_ASM_xxx */
55 OPT_REG32
, /* warning: value is hardcoded from TOK_ASM_xxx */
56 #ifdef TCC_TARGET_X86_64
57 OPT_REG64
, /* warning: value is hardcoded from TOK_ASM_xxx */
59 OPT_MMX
, /* warning: value is hardcoded from TOK_ASM_xxx */
60 OPT_SSE
, /* warning: value is hardcoded from TOK_ASM_xxx */
61 OPT_CR
, /* warning: value is hardcoded from TOK_ASM_xxx */
62 OPT_TR
, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_DB
, /* warning: value is hardcoded from TOK_ASM_xxx */
70 #ifdef TCC_TARGET_X86_64
73 OPT_EAX
, /* %al, %ax, %eax or %rax register */
74 OPT_ST0
, /* %st(0) register */
75 OPT_CL
, /* %cl register */
76 OPT_DX
, /* %dx register */
77 OPT_ADDR
, /* OP_EA with only offset */
78 OPT_INDIR
, /* *(expr) */
81 OPT_IM
, /* IM8 | IM16 | IM32 | IM64 */
82 OPT_REG
, /* REG8 | REG16 | REG32 | REG64 */
83 OPT_REGW
, /* REG16 | REG32 | REG64 */
84 OPT_IMW
, /* IM16 | IM32 | IM64 */
85 #ifdef TCC_TARGET_X86_64
86 OPT_IMNO64
, /* IM16 | IM32 */
88 /* can be ored with any OPT_xxx */
92 #define OP_REG8 (1 << OPT_REG8)
93 #define OP_REG16 (1 << OPT_REG16)
94 #define OP_REG32 (1 << OPT_REG32)
95 #define OP_MMX (1 << OPT_MMX)
96 #define OP_SSE (1 << OPT_SSE)
97 #define OP_CR (1 << OPT_CR)
98 #define OP_TR (1 << OPT_TR)
99 #define OP_DB (1 << OPT_DB)
100 #define OP_SEG (1 << OPT_SEG)
101 #define OP_ST (1 << OPT_ST)
102 #define OP_IM8 (1 << OPT_IM8)
103 #define OP_IM8S (1 << OPT_IM8S)
104 #define OP_IM16 (1 << OPT_IM16)
105 #define OP_IM32 (1 << OPT_IM32)
106 #define OP_EAX (1 << OPT_EAX)
107 #define OP_ST0 (1 << OPT_ST0)
108 #define OP_CL (1 << OPT_CL)
109 #define OP_DX (1 << OPT_DX)
110 #define OP_ADDR (1 << OPT_ADDR)
111 #define OP_INDIR (1 << OPT_INDIR)
112 #ifdef TCC_TARGET_X86_64
113 # define OP_REG64 (1 << OPT_REG64)
114 # define OP_IM64 (1 << OPT_IM64)
120 #define OP_EA 0x40000000
121 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
123 #ifdef TCC_TARGET_X86_64
124 # define OP_IM OP_IM64
125 # define TREG_XAX TREG_RAX
126 # define TREG_XCX TREG_RCX
127 # define TREG_XDX TREG_RDX
129 # define OP_IM OP_IM32
130 # define TREG_XAX TREG_EAX
131 # define TREG_XCX TREG_ECX
132 # define TREG_XDX TREG_EDX
135 typedef struct ASMInstr
{
140 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
143 typedef struct Operand
{
145 int8_t reg
; /* register, -1 if none */
146 int8_t reg2
; /* second register, -1 if none */
151 static const uint8_t reg_to_size
[9] = {
156 #ifdef TCC_TARGET_X86_64
160 0, 0, 1, 0, 2, 0, 0, 0, 3
163 #define NB_TEST_OPCODES 30
165 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
198 static const uint8_t segment_prefixes
[] = {
207 static const ASMInstr asm_instrs
[] = {
209 #define DEF_ASM_OP0(name, opcode)
210 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
211 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
212 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
213 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
214 #ifdef TCC_TARGET_X86_64
215 # include "x86_64-asm.h"
217 # include "i386-asm.h"
223 static const uint16_t op0_codes
[] = {
225 #define DEF_ASM_OP0(x, opcode) opcode,
226 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
227 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
228 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
229 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
230 #ifdef TCC_TARGET_X86_64
231 # include "x86_64-asm.h"
233 # include "i386-asm.h"
237 static inline int get_reg_shift(TCCState
*s1
)
241 if (s1
->seg_size
== 16)
242 error("invalid effective address");
244 v
= asm_int_expr(s1
);
259 expect("1, 2, 4 or 8 constant");
266 static int asm_parse_reg(void)
272 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
273 reg
= tok
- TOK_ASM_eax
;
274 #ifdef TCC_TARGET_X86_64
275 } else if (tok
>= TOK_ASM_rax
&& tok
<= TOK_ASM_rdi
) {
276 reg
= tok
- TOK_ASM_rax
;
279 } else if (tok
>= TOK_ASM_ax
&& tok
<= TOK_ASM_di
) {
280 reg
= tok
- TOK_ASM_ax
;
290 static void parse_operand(TCCState
*s1
, Operand
*op
)
304 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
305 reg
= tok
- TOK_ASM_al
;
306 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
308 if ((op
->type
& OP_REG
) && op
->reg
== TREG_XAX
)
310 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_XCX
)
312 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_XDX
)
314 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
316 op
->reg
= tok
- TOK_ASM_dr0
;
317 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
319 op
->reg
= tok
- TOK_ASM_es
;
320 } else if (tok
== TOK_ASM_st
) {
326 if (tok
!= TOK_PPNUM
)
330 if ((unsigned)reg
>= 8 || p
[1] != '\0')
341 error("unknown register");
345 } else if (tok
== '$') {
353 if (op
->e
.v
== (uint8_t)op
->e
.v
)
355 if (op
->e
.v
== (int8_t)op
->e
.v
)
357 if (op
->e
.v
== (uint16_t)op
->e
.v
)
359 #ifdef TCC_TARGET_X86_64
360 if (op
->e
.v
== (uint32_t)op
->e
.v
)
365 /* address(reg,reg2,shift) with all variants */
381 op
->reg
= asm_parse_reg();
386 op
->reg2
= asm_parse_reg();
390 op
->shift
= get_reg_shift(s1
);
395 if (op
->reg
== -1 && op
->reg2
== -1)
401 static void gen_expr32(ExprValue
*pe
)
403 gen_addr32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
406 #ifdef TCC_TARGET_X86_64
407 static void gen_expr64(ExprValue
*pe
)
409 gen_addr64(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
413 /* XXX: unify with C code output ? */
414 static void gen_disp32(ExprValue
*pe
)
417 if (sym
&& sym
->r
== cur_text_section
->sh_num
) {
418 /* same section: we can output an absolute value. Note
419 that the TCC compiler behaves differently here because
420 it always outputs a relocation to ease (future) code
421 elimination in the linker */
422 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
424 gen_addrpc32(VT_SYM
, sym
, pe
->v
);
429 static void gen_expr16(ExprValue
*pe
)
432 greloc(cur_text_section
, pe
->sym
, ind
, R_386_16
);
435 static void gen_disp16(ExprValue
*pe
)
440 if (sym
->r
== cur_text_section
->sh_num
) {
441 /* same section: we can output an absolute value. Note
442 that the TCC compiler behaves differently here because
443 it always outputs a relocation to ease (future) code
444 elimination in the linker */
445 gen_le16(pe
->v
+ sym
->jnext
- ind
- 2);
447 greloc(cur_text_section
, sym
, ind
, R_386_PC16
);
451 /* put an empty PC32 relocation */
452 put_elf_reloc(symtab_section
, cur_text_section
,
459 /* generate the modrm operand */
460 static inline void asm_modrm(int reg
, Operand
*op
)
462 int mod
, reg1
, reg2
, sib_reg1
;
464 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
465 g(0xc0 + (reg
<< 3) + op
->reg
);
466 } else if (op
->reg
== -1 && op
->reg2
== -1) {
467 /* displacement only */
469 if (tcc_state
->seg_size
== 16) {
470 g(0x06 + (reg
<< 3));
472 } else if (tcc_state
->seg_size
== 32)
475 g(0x05 + (reg
<< 3));
480 /* fist compute displacement encoding */
481 if (sib_reg1
== -1) {
484 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
486 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
491 /* compute if sib byte needed */
496 if (tcc_state
->seg_size
== 32) {
498 g(mod
+ (reg
<< 3) + reg1
);
503 reg2
= 4; /* indicate no index */
504 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
507 } else if (tcc_state
->seg_size
== 16) {
508 /* edi = 7, esi = 6 --> di = 5, si = 4 */
509 if ((reg1
== 6) || (reg1
== 7)) {
511 /* ebx = 3 --> bx = 7 */
512 } else if (reg1
== 3) {
514 /* o32 = 5 --> o16 = 6 */
515 } else if (reg1
== 5) {
517 /* sib not valid in 16-bit mode */
518 } else if (reg1
== 4) {
520 /* bp + si + offset */
521 if ((sib_reg1
== 5) && (reg2
== 6)) {
523 /* bp + di + offset */
524 } else if ((sib_reg1
== 5) && (reg2
== 7)) {
526 /* bx + si + offset */
527 } else if ((sib_reg1
== 3) && (reg2
== 6)) {
529 /* bx + di + offset */
530 } else if ((sib_reg1
== 3) && (reg2
== 7)) {
533 error("invalid effective address");
538 error("invalid register");
540 g(mod
+ (reg
<< 3) + reg1
);
546 } else if (mod
== 0x80 || op
->reg
== -1) {
548 if (tcc_state
->seg_size
== 16)
550 else if (tcc_state
->seg_size
== 32)
557 static void asm_opcode(TCCState
*s1
, int opcode
)
560 int i
, modrm_index
, reg
, v
, op1
, is_short_jmp
, seg_prefix
;
562 Operand ops
[MAX_OPERANDS
], *pop
;
563 int op_type
[3]; /* decoded op type */
565 static int a32
= 0, o32
= 0, addr32
= 0, data32
= 0;
573 if (tok
== ';' || tok
== TOK_LINEFEED
)
575 if (nb_ops
>= MAX_OPERANDS
) {
576 error("incorrect number of operands");
578 parse_operand(s1
, pop
);
580 if (pop
->type
!= OP_SEG
|| seg_prefix
)
581 error("incorrect prefix");
582 seg_prefix
= segment_prefixes
[pop
->reg
];
584 parse_operand(s1
, pop
);
586 if (!(pop
->type
& OP_EA
)) {
587 error("segment prefix must be followed by memory reference");
599 s
= 0; /* avoid warning */
601 /* optimize matching by using a lookup table (no hashing is needed
603 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
605 if (pa
->instr_type
& OPC_FARITH
) {
606 v
= opcode
- pa
->sym
;
607 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
609 } else if (pa
->instr_type
& OPC_ARITH
) {
610 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8*NBWLX
))
612 s
= (opcode
- pa
->sym
) % NBWLX
;
613 } else if (pa
->instr_type
& OPC_SHIFT
) {
614 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7*NBWLX
))
616 s
= (opcode
- pa
->sym
) % NBWLX
;
617 } else if (pa
->instr_type
& OPC_TEST
) {
618 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
620 } else if (pa
->instr_type
& OPC_B
) {
621 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
))
623 s
= opcode
- pa
->sym
;
624 } else if (pa
->instr_type
& OPC_WLX
) {
625 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
627 s
= opcode
- pa
->sym
+ 1;
629 if (pa
->sym
!= opcode
)
632 if (pa
->nb_ops
!= nb_ops
)
634 /* now decode and check each operand */
635 for(i
= 0; i
< nb_ops
; i
++) {
637 op1
= pa
->op_type
[i
];
641 v
= OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
;
644 v
= OP_REG8
| OP_REG16
| OP_REG32
| OP_REG64
;
647 v
= OP_REG16
| OP_REG32
| OP_REG64
;
650 v
= OP_IM16
| OP_IM32
| OP_IM64
;
652 #ifdef TCC_TARGET_X86_64
654 v
= OP_IM16
| OP_IM32
;
664 if ((ops
[i
].type
& v
) == 0)
667 /* all is matching ! */
672 if (opcode
>= TOK_ASM_first
&& opcode
<= TOK_ASM_last
) {
674 b
= op0_codes
[opcode
- TOK_ASM_first
];
676 if (opcode
== TOK_ASM_o32
) {
677 if (s1
->seg_size
== 32)
678 error("incorrect prefix");
681 } else if (opcode
== TOK_ASM_a32
) {
682 if (s1
->seg_size
== 32)
683 error("incorrect prefix");
693 error("unknown opcode '%s'",
694 get_tok_str(opcode
, NULL
));
697 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
699 for(i
= 0; s
== NBWLX
-1 && i
< nb_ops
; i
++) {
700 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
701 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
704 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
705 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
| OP_IM64
)))
708 error("cannot infer opcode suffix");
713 for(i
= 0; i
< nb_ops
; i
++) {
714 if (ops
[i
].type
& OP_REG32
) {
715 if (s1
->seg_size
== 16)
717 } else if (!(ops
[i
].type
& OP_REG32
)) {
718 if (s1
->seg_size
== 32)
724 if (s
== 1 || (pa
->instr_type
& OPC_D16
)) {
725 if (s1
->seg_size
== 32)
728 if (s1
->seg_size
== 16) {
729 if (!(pa
->instr_type
& OPC_D16
))
734 /* generate a16/a32 prefix if needed */
735 if ((a32
== 1) && (addr32
== 0))
737 /* generate o16/o32 prefix if needed */
738 if ((o32
== 1) && (data32
== 0))
743 /* generate data16 prefix if needed */
744 if (s
== 1 || (pa
->instr_type
& OPC_D16
))
746 #ifdef TCC_TARGET_X86_64
748 /* generate REX prefix */
749 if ((opcode
!= TOK_ASM_push
&& opcode
!= TOK_ASM_pop
)
750 || !(ops
[0].type
& OP_REG64
))
756 /* now generates the operation */
757 if (pa
->instr_type
& OPC_FWAIT
)
763 if ((v
== 0x69 || v
== 0x6b) && nb_ops
== 2) {
764 /* kludge for imul $im, %reg */
767 op_type
[2] = op_type
[1];
768 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
769 v
--; /* int $3 case */
771 } else if ((v
== 0x06 || v
== 0x07)) {
772 if (ops
[0].reg
>= 4) {
773 /* push/pop %fs or %gs */
774 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
776 v
+= ops
[0].reg
<< 3;
779 } else if (v
<= 0x05) {
781 v
+= ((opcode
- TOK_ASM_addb
) / NBWLX
) << 3;
782 } else if ((pa
->instr_type
& (OPC_FARITH
| OPC_MODRM
)) == OPC_FARITH
) {
784 v
+= ((opcode
- pa
->sym
) / 6) << 3;
786 if (pa
->instr_type
& OPC_REG
) {
787 for(i
= 0; i
< nb_ops
; i
++) {
788 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
793 /* mov $im, %reg case */
794 if (pa
->opcode
== 0xb0 && s
>= 1)
797 if (pa
->instr_type
& OPC_B
)
799 if (pa
->instr_type
& OPC_TEST
)
800 v
+= test_bits
[opcode
- pa
->sym
];
801 if (pa
->instr_type
& OPC_SHORTJMP
) {
805 /* see if we can really generate the jump with a byte offset */
809 if (sym
->r
!= cur_text_section
->sh_num
)
811 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2;
812 if (jmp_disp
== (int8_t)jmp_disp
) {
813 /* OK to generate jump */
815 ops
[0].e
.v
= jmp_disp
;
818 if (pa
->instr_type
& OPC_JMP
) {
819 /* long jump will be allowed. need to modify the
826 error("invalid displacement");
835 /* search which operand will used for modrm */
837 if (pa
->instr_type
& OPC_SHIFT
) {
838 reg
= (opcode
- pa
->sym
) / NBWLX
;
841 } else if (pa
->instr_type
& OPC_ARITH
) {
842 reg
= (opcode
- pa
->sym
) / NBWLX
;
843 } else if (pa
->instr_type
& OPC_FARITH
) {
844 reg
= (opcode
- pa
->sym
) / 6;
846 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
848 if (pa
->instr_type
& OPC_MODRM
) {
849 /* first look for an ea operand */
850 for(i
= 0;i
< nb_ops
; i
++) {
851 if (op_type
[i
] & OP_EA
)
854 /* then if not found, a register or indirection (shift instructions) */
855 for(i
= 0;i
< nb_ops
; i
++) {
856 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
860 error("bad op table");
864 /* if a register is used in another operand then it is
865 used instead of group */
866 for(i
= 0;i
< nb_ops
; i
++) {
868 if (i
!= modrm_index
&&
869 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
875 asm_modrm(reg
, &ops
[modrm_index
]);
879 #ifndef TCC_TARGET_X86_64
880 if (pa
->opcode
== 0x9a || pa
->opcode
== 0xea) {
881 /* ljmp or lcall kludge */
883 if (s1
->seg_size
== 16 && o32
== 0)
884 gen_expr16(&ops
[1].e
);
887 gen_expr32(&ops
[1].e
);
889 error("cannot relocate");
890 gen_le16(ops
[0].e
.v
);
894 for(i
= 0;i
< nb_ops
; i
++) {
896 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
| OP_IM8S
| OP_ADDR
)) {
897 /* if multiple sizes are given it means we must look
899 if ((v
| OP_IM8
| OP_IM64
) == (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
)) {
904 else if (s
== 2 || (v
& OP_IM64
) == 0)
909 if (v
& (OP_IM8
| OP_IM8S
)) {
913 } else if (v
& OP_IM16
) {
915 if (s1
->seg_size
== 16)
916 gen_expr16(&ops
[i
].e
);
921 error("cannot relocate");
923 gen_le16(ops
[i
].e
.v
);
925 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
929 else if (s1
->seg_size
== 16)
930 gen_disp16(&ops
[i
].e
);
933 gen_disp32(&ops
[i
].e
);
936 if (s1
->seg_size
== 16 && !((o32
== 1) && (v
& OP_IM32
)))
937 gen_expr16(&ops
[i
].e
);
940 #ifdef TCC_TARGET_X86_64
942 gen_expr64(&ops
[i
].e
);
945 gen_expr32(&ops
[i
].e
);
949 } else if (v
& (OP_REG16
| OP_REG32
)) {
950 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
952 g(0xE0 + ops
[i
].reg
);
955 #ifdef TCC_TARGET_X86_64
956 } else if (v
& (OP_REG32
| OP_REG64
)) {
957 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
959 g(0xE0 + ops
[i
].reg
);
969 #define NB_SAVED_REGS 3
970 #define NB_ASM_REGS 8
972 /* return the constraint priority (we allocate first the lowest
973 numbered constraints) */
974 static inline int constraint_priority(const char *str
)
978 /* we take the lowest priority */
1012 error("unknown constraint '%c'", c
);
1021 static const char *skip_constraint_modifiers(const char *p
)
1023 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1028 #define REG_OUT_MASK 0x01
1029 #define REG_IN_MASK 0x02
1031 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1033 static void asm_compute_constraints(ASMOperand
*operands
,
1034 int nb_operands
, int nb_outputs
,
1035 const uint8_t *clobber_regs
,
1039 int sorted_op
[MAX_ASM_OPERANDS
];
1040 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1042 uint8_t regs_allocated
[NB_ASM_REGS
];
1045 for(i
=0;i
<nb_operands
;i
++) {
1047 op
->input_index
= -1;
1053 /* compute constraint priority and evaluate references to output
1054 constraints if input constraints */
1055 for(i
=0;i
<nb_operands
;i
++) {
1057 str
= op
->constraint
;
1058 str
= skip_constraint_modifiers(str
);
1059 if (isnum(*str
) || *str
== '[') {
1060 /* this is a reference to another constraint */
1061 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1062 if ((unsigned)k
>= i
|| i
< nb_outputs
)
1063 error("invalid reference in constraint %d ('%s')",
1066 if (operands
[k
].input_index
>= 0)
1067 error("cannot reference twice the same operand");
1068 operands
[k
].input_index
= i
;
1071 op
->priority
= constraint_priority(str
);
1075 /* sort operands according to their priority */
1076 for(i
=0;i
<nb_operands
;i
++)
1078 for(i
=0;i
<nb_operands
- 1;i
++) {
1079 for(j
=i
+1;j
<nb_operands
;j
++) {
1080 p1
= operands
[sorted_op
[i
]].priority
;
1081 p2
= operands
[sorted_op
[j
]].priority
;
1084 sorted_op
[i
] = sorted_op
[j
];
1090 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
1091 if (clobber_regs
[i
])
1092 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1094 regs_allocated
[i
] = 0;
1096 /* esp cannot be used */
1097 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
1098 /* ebp cannot be used yet */
1099 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1101 /* allocate registers and generate corresponding asm moves */
1102 for(i
=0;i
<nb_operands
;i
++) {
1105 str
= op
->constraint
;
1106 /* no need to allocate references */
1107 if (op
->ref_index
>= 0)
1109 /* select if register is used for output, input or both */
1110 if (op
->input_index
>= 0) {
1111 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1112 } else if (j
< nb_outputs
) {
1113 reg_mask
= REG_OUT_MASK
;
1115 reg_mask
= REG_IN_MASK
;
1126 if (j
>= nb_outputs
)
1127 error("'%c' modifier can only be applied to outputs", c
);
1128 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1131 /* allocate both eax and edx */
1132 if (is_reg_allocated(TREG_XAX
) ||
1133 is_reg_allocated(TREG_XDX
))
1137 regs_allocated
[TREG_XAX
] |= reg_mask
;
1138 regs_allocated
[TREG_XDX
] |= reg_mask
;
1158 if (is_reg_allocated(reg
))
1162 /* eax, ebx, ecx or edx */
1163 for(reg
= 0; reg
< 4; reg
++) {
1164 if (!is_reg_allocated(reg
))
1169 /* any general register */
1170 for(reg
= 0; reg
< 8; reg
++) {
1171 if (!is_reg_allocated(reg
))
1176 /* now we can reload in the register */
1179 regs_allocated
[reg
] |= reg_mask
;
1182 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1188 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1193 /* nothing special to do because the operand is already in
1194 memory, except if the pointer itself is stored in a
1195 memory variable (VT_LLOCAL case) */
1196 /* XXX: fix constant case */
1197 /* if it is a reference to a memory zone, it must lie
1198 in a register, so we reserve the register in the
1199 input registers and a load will be generated
1201 if (j
< nb_outputs
|| c
== 'm') {
1202 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1203 /* any general register */
1204 for(reg
= 0; reg
< 8; reg
++) {
1205 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1210 /* now we can reload in the register */
1211 regs_allocated
[reg
] |= REG_IN_MASK
;
1218 error("asm constraint %d ('%s') could not be satisfied",
1222 /* if a reference is present for that operand, we assign it too */
1223 if (op
->input_index
>= 0) {
1224 operands
[op
->input_index
].reg
= op
->reg
;
1225 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1229 /* compute out_reg. It is used to store outputs registers to memory
1230 locations references by pointers (VT_LLOCAL case) */
1232 for(i
=0;i
<nb_operands
;i
++) {
1235 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1237 for(reg
= 0; reg
< 8; reg
++) {
1238 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1241 error("could not find free output register for reloading");
1248 /* print sorted constraints */
1250 for(i
=0;i
<nb_operands
;i
++) {
1253 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1255 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1261 printf("out_reg=%d\n", *pout_reg
);
1265 static void subst_asm_operand(CString
*add_str
,
1266 SValue
*sv
, int modifier
)
1268 int r
, reg
, size
, val
;
1272 if ((r
& VT_VALMASK
) == VT_CONST
) {
1273 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n')
1274 cstr_ccat(add_str
, '$');
1276 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
));
1278 cstr_ccat(add_str
, '+');
1284 if (modifier
== 'n')
1286 snprintf(buf
, sizeof(buf
), "%d", sv
->c
.i
);
1287 cstr_cat(add_str
, buf
);
1288 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1289 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", sv
->c
.i
);
1290 cstr_cat(add_str
, buf
);
1291 } else if (r
& VT_LVAL
) {
1292 reg
= r
& VT_VALMASK
;
1293 if (reg
>= VT_CONST
)
1294 error("internal compiler error");
1295 snprintf(buf
, sizeof(buf
), "(%%%s)",
1296 get_tok_str(TOK_ASM_eax
+ reg
, NULL
));
1297 cstr_cat(add_str
, buf
);
1300 reg
= r
& VT_VALMASK
;
1301 if (reg
>= VT_CONST
)
1302 error("internal compiler error");
1304 /* choose register operand size */
1305 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1307 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1309 #ifdef TCC_TARGET_X86_64
1310 else if ((sv
->type
.t
& VT_BTYPE
) == VT_LLONG
)
1315 if (size
== 1 && reg
>= 4)
1318 if (modifier
== 'b') {
1320 error("cannot use byte register");
1322 } else if (modifier
== 'h') {
1324 error("cannot use byte register");
1326 } else if (modifier
== 'w') {
1328 #ifdef TCC_TARGET_X86_64
1329 } else if (modifier
== 'q') {
1336 reg
= TOK_ASM_ah
+ reg
;
1339 reg
= TOK_ASM_al
+ reg
;
1342 reg
= TOK_ASM_ax
+ reg
;
1345 reg
= TOK_ASM_eax
+ reg
;
1347 #ifdef TCC_TARGET_X86_64
1349 reg
= TOK_ASM_rax
+ reg
;
1353 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1354 cstr_cat(add_str
, buf
);
1358 /* generate prolog and epilog code for asm statment */
1359 static void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1360 int nb_outputs
, int is_output
,
1361 uint8_t *clobber_regs
,
1364 uint8_t regs_allocated
[NB_ASM_REGS
];
1367 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1369 /* mark all used registers */
1370 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1371 for(i
= 0; i
< nb_operands
;i
++) {
1374 regs_allocated
[op
->reg
] = 1;
1377 /* generate reg save code */
1378 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1380 if (regs_allocated
[reg
]) {
1382 if (tcc_state
->seg_size
== 16)
1389 /* generate load code */
1390 for(i
= 0; i
< nb_operands
; i
++) {
1393 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1395 /* memory reference case (for both input and
1399 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1401 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1402 /* load value in register */
1403 load(op
->reg
, op
->vt
);
1408 load(TREG_XDX
, &sv
);
1414 /* generate save code */
1415 for(i
= 0 ; i
< nb_outputs
; i
++) {
1418 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1419 if (!op
->is_memory
) {
1422 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1425 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1426 store(op
->reg
, &sv
);
1429 store(op
->reg
, op
->vt
);
1434 store(TREG_XDX
, &sv
);
1439 /* generate reg restore code */
1440 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1442 if (regs_allocated
[reg
]) {
1444 if (tcc_state
->seg_size
== 16)
1453 static void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1458 if (!strcmp(str
, "memory") ||
1461 ts
= tok_alloc(str
, strlen(str
));
1463 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1465 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1467 #ifdef TCC_TARGET_X86_64
1468 } else if (reg
>= TOK_ASM_rax
&& reg
<= TOK_ASM_rdi
) {
1472 error("invalid clobber register '%s'", str
);
1474 clobber_regs
[reg
] = 1;