2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #define MAX_OPERANDS 3
23 typedef struct ASMInstr
{
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
42 /* in order to compress the operand type, we use specific operands and
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
72 /* can be ored with any OPT_xxx */
76 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
79 typedef struct Operand
{
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg
; /* register, -1 if none */
106 int8_t reg2
; /* second register, -1 if none */
111 static const uint8_t reg_to_size
[5] = {
120 #define NB_TEST_OPCODES 30
122 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
155 static const uint8_t segment_prefixes
[] = {
164 static const ASMInstr asm_instrs
[] = {
166 #define DEF_ASM_OP0(name, opcode)
167 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
168 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
169 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
170 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
171 #include "i386-asm.h"
177 static const uint16_t op0_codes
[] = {
179 #define DEF_ASM_OP0(x, opcode) opcode,
180 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
181 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
182 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
183 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
184 #include "i386-asm.h"
187 static inline int get_reg_shift(TCCState
*s1
)
191 if (s1
->seg_size
== 16) {
192 error("invalid effective address");
195 v
= asm_int_expr(s1
);
210 expect("1, 2, 4 or 8 constant");
217 static int asm_parse_reg(void)
223 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
224 reg
= tok
- TOK_ASM_eax
;
227 } else if (tok
>= TOK_ASM_ax
&& tok
<= TOK_ASM_di
) {
228 reg
= tok
- TOK_ASM_ax
;
238 static void parse_operand(TCCState
*s1
, Operand
*op
)
252 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
253 reg
= tok
- TOK_ASM_al
;
254 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
256 if ((op
->type
& OP_REG
) && op
->reg
== TREG_EAX
)
258 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_ECX
)
260 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_EDX
)
262 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
264 op
->reg
= tok
- TOK_ASM_dr0
;
265 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
267 op
->reg
= tok
- TOK_ASM_es
;
268 } else if (tok
== TOK_ASM_st
) {
274 if (tok
!= TOK_PPNUM
)
278 if ((unsigned)reg
>= 8 || p
[1] != '\0')
289 error("unknown register");
293 } else if (tok
== '$') {
301 if (op
->e
.v
== (uint8_t)op
->e
.v
)
303 if (op
->e
.v
== (int8_t)op
->e
.v
)
305 if (op
->e
.v
== (uint16_t)op
->e
.v
)
309 /* address(reg,reg2,shift) with all variants */
325 op
->reg
= asm_parse_reg();
330 op
->reg2
= asm_parse_reg();
334 op
->shift
= get_reg_shift(s1
);
339 if (op
->reg
== -1 && op
->reg2
== -1)
345 static void gen_le16(int v
)
351 /* XXX: unify with C code output ? */
352 static void gen_expr32(ExprValue
*pe
)
355 greloc(cur_text_section
, pe
->sym
, ind
, R_386_32
);
359 static void gen_expr16(ExprValue
*pe
)
362 greloc(cur_text_section
, pe
->sym
, ind
, R_386_16
);
366 /* XXX: unify with C code output ? */
367 static void gen_disp32(ExprValue
*pe
)
372 if (sym
->r
== cur_text_section
->sh_num
) {
373 /* same section: we can output an absolute value. Note
374 that the TCC compiler behaves differently here because
375 it always outputs a relocation to ease (future) code
376 elimination in the linker */
377 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
379 greloc(cur_text_section
, sym
, ind
, R_386_PC32
);
383 /* put an empty PC32 relocation */
384 put_elf_reloc(symtab_section
, cur_text_section
,
390 static void gen_disp16(ExprValue
*pe
)
395 if (sym
->r
== cur_text_section
->sh_num
) {
396 /* same section: we can output an absolute value. Note
397 that the TCC compiler behaves differently here because
398 it always outputs a relocation to ease (future) code
399 elimination in the linker */
400 gen_le16(pe
->v
+ sym
->jnext
- ind
- 2);
402 greloc(cur_text_section
, sym
, ind
, R_386_PC16
);
406 /* put an empty PC32 relocation */
407 put_elf_reloc(symtab_section
, cur_text_section
,
413 /* generate the modrm operand */
414 static inline void asm_modrm(int reg
, Operand
*op
)
416 int mod
, reg1
, reg2
, sib_reg1
;
418 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
419 g(0xc0 + (reg
<< 3) + op
->reg
);
420 } else if (op
->reg
== -1 && op
->reg2
== -1) {
421 /* displacement only */
422 if (tcc_state
->seg_size
== 16) {
423 g(0x06 + (reg
<< 3));
425 } else if (tcc_state
->seg_size
== 32) {
426 g(0x05 + (reg
<< 3));
431 /* fist compute displacement encoding */
432 if (sib_reg1
== -1) {
435 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
437 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
442 /* compute if sib byte needed */
446 if (tcc_state
->seg_size
== 32) {
447 g(mod
+ (reg
<< 3) + reg1
);
452 reg2
= 4; /* indicate no index */
453 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
455 } else if (tcc_state
->seg_size
== 16) {
456 /* edi = 7, esi = 6 --> di = 5, si = 4 */
457 if ((reg1
== 6) || (reg1
== 7)) {
459 /* ebx = 3 --> bx = 7 */
460 } else if (reg1
== 3) {
462 /* o32 = 5 --> o16 = 6 */
463 } else if (reg1
== 5) {
465 /* sib not valid in 16-bit mode */
466 } else if (reg1
== 4) {
468 /* bp + si + offset */
469 if ((sib_reg1
== 5) && (reg2
== 6)) {
471 /* bp + di + offset */
472 } else if ((sib_reg1
== 5) && (reg2
== 7)) {
474 /* bx + si + offset */
475 } else if ((sib_reg1
== 3) && (reg2
== 6)) {
477 /* bx + di + offset */
478 } else if ((sib_reg1
== 3) && (reg2
== 7)) {
481 error("invalid effective address");
486 error("invalid register");
488 g(mod
+ (reg
<< 3) + reg1
);
494 } else if (mod
== 0x80 || op
->reg
== -1) {
495 if (tcc_state
->seg_size
== 16)
497 else if (tcc_state
->seg_size
== 32)
503 static void asm_opcode(TCCState
*s1
, int opcode
)
506 int i
, modrm_index
, reg
, v
, op1
, is_short_jmp
, seg_prefix
;
508 Operand ops
[MAX_OPERANDS
], *pop
;
509 int op_type
[3]; /* decoded op type */
512 static int addr32
= 0, data32
= 0;
519 if (tok
== ';' || tok
== TOK_LINEFEED
)
521 if (nb_ops
>= MAX_OPERANDS
) {
522 error("incorrect number of operands");
524 parse_operand(s1
, pop
);
526 if (pop
->type
!= OP_SEG
|| seg_prefix
) {
528 error("incorrect prefix");
530 seg_prefix
= segment_prefixes
[pop
->reg
];
532 parse_operand(s1
, pop
);
534 if (!(pop
->type
& OP_EA
)) {
535 error("segment prefix must be followed by memory reference");
547 s
= 0; /* avoid warning */
549 /* optimize matching by using a lookup table (no hashing is needed
551 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
553 if (pa
->instr_type
& OPC_FARITH
) {
554 v
= opcode
- pa
->sym
;
555 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
557 } else if (pa
->instr_type
& OPC_ARITH
) {
558 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8 * 4))
561 } else if (pa
->instr_type
& OPC_SHIFT
) {
562 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7 * 4))
565 } else if (pa
->instr_type
& OPC_TEST
) {
566 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
568 } else if (pa
->instr_type
& OPC_B
) {
569 if (!(opcode
>= pa
->sym
&& opcode
<= pa
->sym
+ 3))
572 s
= (opcode
- pa
->sym
) & 3;
573 } else if (pa
->instr_type
& OPC_WL
) {
574 if (!(opcode
>= pa
->sym
&& opcode
<= pa
->sym
+ 2))
576 s
= opcode
- pa
->sym
+ 1;
578 if (pa
->sym
!= opcode
)
581 if (pa
->nb_ops
!= nb_ops
)
583 /* now decode and check each operand */
584 for(i
= 0; i
< nb_ops
; i
++) {
586 op1
= pa
->op_type
[i
];
590 v
= OP_IM8
| OP_IM16
| OP_IM32
;
593 v
= OP_REG8
| OP_REG16
| OP_REG32
;
596 v
= OP_REG16
| OP_REG32
;
599 v
= OP_IM16
| OP_IM32
;
608 if ((ops
[i
].type
& v
) == 0)
611 /* all is matching ! */
616 if (opcode
>= TOK_ASM_pusha
&& opcode
<= TOK_ASM_emms
) {
618 b
= op0_codes
[opcode
- TOK_ASM_pusha
];
619 if (opcode
== TOK_ASM_o32
) {
620 if (s1
->seg_size
== 32)
624 } else if (opcode
== TOK_ASM_a32
) {
625 if (s1
->seg_size
== 32)
635 error("unknown opcode '%s'",
636 get_tok_str(opcode
, NULL
));
639 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
641 for(i
= 0; s
== 3 && i
< nb_ops
; i
++) {
642 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
643 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
646 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
647 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
)))
650 error("cannot infer opcode suffix");
655 if (s
== 1 || (pa
->instr_type
& OPC_D16
)) {
656 if (s1
->seg_size
== 32)
658 } else if (s
== 2 && !(pa
->instr_type
& OPC_D16
)) {
659 if (s1
->seg_size
== 16)
663 /* generate a16/a32 prefix if needed */
664 if ((a32
== 1) && (addr32
== 0))
666 /* generate o16/o32 prefix if needed */
667 if ((o32
== 1) && (data32
== 0))
672 /* now generates the operation */
673 if (pa
->instr_type
& OPC_FWAIT
)
679 if ((v
== 0x69 || v
== 0x6b) && nb_ops
== 2) {
680 /* kludge for imul $im, %reg */
683 op_type
[2] = op_type
[1];
684 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
685 v
--; /* int $3 case */
687 } else if ((v
== 0x06 || v
== 0x07)) {
688 if (ops
[0].reg
>= 4) {
689 /* push/pop %fs or %gs */
690 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
692 v
+= ops
[0].reg
<< 3;
695 } else if (v
<= 0x05) {
697 v
+= ((opcode
- TOK_ASM_addb
) >> 2) << 3;
698 } else if ((pa
->instr_type
& (OPC_FARITH
| OPC_MODRM
)) == OPC_FARITH
) {
700 v
+= ((opcode
- pa
->sym
) / 6) << 3;
702 if (pa
->instr_type
& OPC_REG
) {
703 for(i
= 0; i
< nb_ops
; i
++) {
704 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
709 /* mov $im, %reg case */
710 if (pa
->opcode
== 0xb0 && s
>= 1)
713 if (pa
->instr_type
& OPC_B
)
715 if (pa
->instr_type
& OPC_TEST
)
716 v
+= test_bits
[opcode
- pa
->sym
];
717 if (pa
->instr_type
& OPC_SHORTJMP
) {
721 /* see if we can really generate the jump with a byte offset */
725 if (sym
->r
!= cur_text_section
->sh_num
)
727 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2;
728 if (jmp_disp
== (int8_t)jmp_disp
) {
729 /* OK to generate jump */
731 ops
[0].e
.v
= jmp_disp
;
734 if (pa
->instr_type
& OPC_JMP
) {
735 /* long jump will be allowed. need to modify the
742 error("invalid displacement");
751 /* search which operand will used for modrm */
753 if (pa
->instr_type
& OPC_SHIFT
) {
754 reg
= (opcode
- pa
->sym
) >> 2;
757 } else if (pa
->instr_type
& OPC_ARITH
) {
758 reg
= (opcode
- pa
->sym
) >> 2;
759 } else if (pa
->instr_type
& OPC_FARITH
) {
760 reg
= (opcode
- pa
->sym
) / 6;
762 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
764 if (pa
->instr_type
& OPC_MODRM
) {
765 /* first look for an ea operand */
766 for(i
= 0;i
< nb_ops
; i
++) {
767 if (op_type
[i
] & OP_EA
)
770 /* then if not found, a register or indirection (shift instructions) */
771 for(i
= 0;i
< nb_ops
; i
++) {
772 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
776 error("bad op table");
780 /* if a register is used in another operand then it is
781 used instead of group */
782 for(i
= 0;i
< nb_ops
; i
++) {
784 if (i
!= modrm_index
&&
785 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
791 asm_modrm(reg
, &ops
[modrm_index
]);
795 if (pa
->opcode
== 0x9a || pa
->opcode
== 0xea) {
796 /* ljmp or lcall kludge */
797 if (s1
->seg_size
== 16) {
799 gen_expr16(&ops
[1].e
);
801 gen_expr32(&ops
[1].e
);
803 gen_expr32(&ops
[1].e
);
806 error("cannot relocate");
808 gen_le16(ops
[0].e
.v
);
810 for(i
= 0;i
< nb_ops
; i
++) {
812 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM8S
| OP_ADDR
)) {
813 /* if multiple sizes are given it means we must look
815 if (v
== (OP_IM8
| OP_IM16
| OP_IM32
) ||
816 v
== (OP_IM16
| OP_IM32
)) {
824 if (v
& (OP_IM8
| OP_IM8S
)) {
828 } else if (v
& OP_IM16
) {
829 if (s1
->seg_size
== 16)
830 gen_expr16(&ops
[i
].e
);
834 gen_le16(ops
[i
].e
.v
);
837 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
841 if (s1
->seg_size
== 16)
842 gen_disp16(&ops
[i
].e
);
844 gen_disp32(&ops
[i
].e
);
847 if (s1
->seg_size
== 16) {
848 if ((o32
== 1) && (v
& OP_IM32
))
849 gen_expr32(&ops
[i
].e
);
851 gen_expr16(&ops
[i
].e
);
852 } else if (s1
->seg_size
== 32) {
854 gen_expr16(&ops
[i
].e
);
856 gen_expr32(&ops
[i
].e
);
860 } else if (v
& (OP_REG16
| OP_REG32
)) {
861 if (pa
->instr_type
& (OPC_JMP
| OPC_SHORTJMP
)) {
863 g(0xE0 + ops
[i
].reg
);
870 #define NB_SAVED_REGS 3
871 #define NB_ASM_REGS 8
873 /* return the constraint priority (we allocate first the lowest
874 numbered constraints) */
875 static inline int constraint_priority(const char *str
)
879 /* we take the lowest priority */
913 error("unknown constraint '%c'", c
);
922 static const char *skip_constraint_modifiers(const char *p
)
924 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
929 #define REG_OUT_MASK 0x01
930 #define REG_IN_MASK 0x02
932 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
934 static void asm_compute_constraints(ASMOperand
*operands
,
935 int nb_operands
, int nb_outputs
,
936 const uint8_t *clobber_regs
,
940 int sorted_op
[MAX_ASM_OPERANDS
];
941 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
943 uint8_t regs_allocated
[NB_ASM_REGS
];
946 for(i
=0;i
<nb_operands
;i
++) {
948 op
->input_index
= -1;
954 /* compute constraint priority and evaluate references to output
955 constraints if input constraints */
956 for(i
=0;i
<nb_operands
;i
++) {
958 str
= op
->constraint
;
959 str
= skip_constraint_modifiers(str
);
960 if (isnum(*str
) || *str
== '[') {
961 /* this is a reference to another constraint */
962 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
963 if ((unsigned)k
>= i
|| i
< nb_outputs
)
964 error("invalid reference in constraint %d ('%s')",
967 if (operands
[k
].input_index
>= 0)
968 error("cannot reference twice the same operand");
969 operands
[k
].input_index
= i
;
972 op
->priority
= constraint_priority(str
);
976 /* sort operands according to their priority */
977 for(i
=0;i
<nb_operands
;i
++)
979 for(i
=0;i
<nb_operands
- 1;i
++) {
980 for(j
=i
+1;j
<nb_operands
;j
++) {
981 p1
= operands
[sorted_op
[i
]].priority
;
982 p2
= operands
[sorted_op
[j
]].priority
;
985 sorted_op
[i
] = sorted_op
[j
];
991 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
993 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
995 regs_allocated
[i
] = 0;
997 /* esp cannot be used */
998 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
999 /* ebp cannot be used yet */
1000 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1002 /* allocate registers and generate corresponding asm moves */
1003 for(i
=0;i
<nb_operands
;i
++) {
1006 str
= op
->constraint
;
1007 /* no need to allocate references */
1008 if (op
->ref_index
>= 0)
1010 /* select if register is used for output, input or both */
1011 if (op
->input_index
>= 0) {
1012 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1013 } else if (j
< nb_outputs
) {
1014 reg_mask
= REG_OUT_MASK
;
1016 reg_mask
= REG_IN_MASK
;
1027 if (j
>= nb_outputs
)
1028 error("'%c' modifier can only be applied to outputs", c
);
1029 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1032 /* allocate both eax and edx */
1033 if (is_reg_allocated(TREG_EAX
) ||
1034 is_reg_allocated(TREG_EDX
))
1038 regs_allocated
[TREG_EAX
] |= reg_mask
;
1039 regs_allocated
[TREG_EDX
] |= reg_mask
;
1059 if (is_reg_allocated(reg
))
1063 /* eax, ebx, ecx or edx */
1064 for(reg
= 0; reg
< 4; reg
++) {
1065 if (!is_reg_allocated(reg
))
1070 /* any general register */
1071 for(reg
= 0; reg
< 8; reg
++) {
1072 if (!is_reg_allocated(reg
))
1077 /* now we can reload in the register */
1080 regs_allocated
[reg
] |= reg_mask
;
1083 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1089 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1094 /* nothing special to do because the operand is already in
1095 memory, except if the pointer itself is stored in a
1096 memory variable (VT_LLOCAL case) */
1097 /* XXX: fix constant case */
1098 /* if it is a reference to a memory zone, it must lie
1099 in a register, so we reserve the register in the
1100 input registers and a load will be generated
1102 if (j
< nb_outputs
|| c
== 'm') {
1103 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1104 /* any general register */
1105 for(reg
= 0; reg
< 8; reg
++) {
1106 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1111 /* now we can reload in the register */
1112 regs_allocated
[reg
] |= REG_IN_MASK
;
1119 error("asm constraint %d ('%s') could not be satisfied",
1123 /* if a reference is present for that operand, we assign it too */
1124 if (op
->input_index
>= 0) {
1125 operands
[op
->input_index
].reg
= op
->reg
;
1126 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1130 /* compute out_reg. It is used to store outputs registers to memory
1131 locations references by pointers (VT_LLOCAL case) */
1133 for(i
=0;i
<nb_operands
;i
++) {
1136 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1138 for(reg
= 0; reg
< 8; reg
++) {
1139 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1142 error("could not find free output register for reloading");
1149 /* print sorted constraints */
1151 for(i
=0;i
<nb_operands
;i
++) {
1154 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1156 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1162 printf("out_reg=%d\n", *pout_reg
);
1166 static void subst_asm_operand(CString
*add_str
,
1167 SValue
*sv
, int modifier
)
1169 int r
, reg
, size
, val
;
1173 if ((r
& VT_VALMASK
) == VT_CONST
) {
1174 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n')
1175 cstr_ccat(add_str
, '$');
1177 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
));
1179 cstr_ccat(add_str
, '+');
1185 if (modifier
== 'n')
1187 snprintf(buf
, sizeof(buf
), "%d", sv
->c
.i
);
1188 cstr_cat(add_str
, buf
);
1189 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1190 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", sv
->c
.i
);
1191 cstr_cat(add_str
, buf
);
1192 } else if (r
& VT_LVAL
) {
1193 reg
= r
& VT_VALMASK
;
1194 if (reg
>= VT_CONST
)
1195 error("internal compiler error");
1196 snprintf(buf
, sizeof(buf
), "(%%%s)",
1197 get_tok_str(TOK_ASM_eax
+ reg
, NULL
));
1198 cstr_cat(add_str
, buf
);
1201 reg
= r
& VT_VALMASK
;
1202 if (reg
>= VT_CONST
)
1203 error("internal compiler error");
1205 /* choose register operand size */
1206 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1208 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1212 if (size
== 1 && reg
>= 4)
1215 if (modifier
== 'b') {
1217 error("cannot use byte register");
1219 } else if (modifier
== 'h') {
1221 error("cannot use byte register");
1223 } else if (modifier
== 'w') {
1229 reg
= TOK_ASM_ah
+ reg
;
1232 reg
= TOK_ASM_al
+ reg
;
1235 reg
= TOK_ASM_ax
+ reg
;
1238 reg
= TOK_ASM_eax
+ reg
;
1241 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1242 cstr_cat(add_str
, buf
);
1246 /* generate prolog and epilog code for asm statment */
1247 static void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1248 int nb_outputs
, int is_output
,
1249 uint8_t *clobber_regs
,
1252 uint8_t regs_allocated
[NB_ASM_REGS
];
1255 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1257 /* mark all used registers */
1258 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1259 for(i
= 0; i
< nb_operands
;i
++) {
1262 regs_allocated
[op
->reg
] = 1;
1265 /* generate reg save code */
1266 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1268 if (regs_allocated
[reg
]) {
1269 if (tcc_state
->seg_size
== 16)
1275 /* generate load code */
1276 for(i
= 0; i
< nb_operands
; i
++) {
1279 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1281 /* memory reference case (for both input and
1285 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1287 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1288 /* load value in register */
1289 load(op
->reg
, op
->vt
);
1294 load(TREG_EDX
, &sv
);
1300 /* generate save code */
1301 for(i
= 0 ; i
< nb_outputs
; i
++) {
1304 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1305 if (!op
->is_memory
) {
1308 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1311 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1312 store(op
->reg
, &sv
);
1315 store(op
->reg
, op
->vt
);
1320 store(TREG_EDX
, &sv
);
1325 /* generate reg restore code */
1326 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1328 if (regs_allocated
[reg
]) {
1329 if (tcc_state
->seg_size
== 16)
1337 static void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1342 if (!strcmp(str
, "memory") ||
1345 ts
= tok_alloc(str
, strlen(str
));
1347 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1349 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1352 error("invalid clobber register '%s'", str
);
1354 clobber_regs
[reg
] = 1;