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Rewrote '?' for constants
[tinycc/kirr.git] / i386-asm.c
blob21b28d7a0939f764350fef023d8f02524ff030a5
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #define MAX_OPERANDS 3
22
23 typedef struct ASMInstr {
24 uint16_t sym;
25 uint16_t opcode;
26 uint16_t instr_type;
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
41
42 /* in order to compress the operand type, we use specific operands and
43 we or only with EA */
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_SEG 8
53 #define OPT_ST 9
54 #define OPT_IM8 10
55 #define OPT_IM8S 11
56 #define OPT_IM16 12
57 #define OPT_IM32 13
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
64
65 /* composite types */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
71
72 /* can be ored with any OPT_xxx */
73 #define OPT_EA 0x80
74
75 uint8_t nb_ops;
76 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
77 } ASMInstr;
78
79 typedef struct Operand {
80 uint32_t type;
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
101
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg; /* register, -1 if none */
106 int8_t reg2; /* second register, -1 if none */
107 uint8_t shift;
108 ExprValue e;
109 } Operand;
110
111 static const uint8_t reg_to_size[5] = {
112 /*
113 [OP_REG8] = 0,
114 [OP_REG16] = 1,
115 [OP_REG32] = 2,
116 */
117 0, 0, 1, 0, 2
118 };
119
120 #define WORD_PREFIX_OPCODE 0x66
121
122 #define NB_TEST_OPCODES 30
123
124 static const uint8_t test_bits[NB_TEST_OPCODES] = {
125 0x00, /* o */
126 0x01, /* no */
127 0x02, /* b */
128 0x02, /* c */
129 0x02, /* nae */
130 0x03, /* nb */
131 0x03, /* nc */
132 0x03, /* ae */
133 0x04, /* e */
134 0x04, /* z */
135 0x05, /* ne */
136 0x05, /* nz */
137 0x06, /* be */
138 0x06, /* na */
139 0x07, /* nbe */
140 0x07, /* a */
141 0x08, /* s */
142 0x09, /* ns */
143 0x0a, /* p */
144 0x0a, /* pe */
145 0x0b, /* np */
146 0x0b, /* po */
147 0x0c, /* l */
148 0x0c, /* nge */
149 0x0d, /* nl */
150 0x0d, /* ge */
151 0x0e, /* le */
152 0x0e, /* ng */
153 0x0f, /* nle */
154 0x0f, /* g */
155 };
156
157 static const uint8_t segment_prefixes[] = {
158 0x26, /* es */
159 0x2e, /* cs */
160 0x36, /* ss */
161 0x3e, /* ds */
162 0x64, /* fs */
163 0x65 /* gs */
164 };
165
166 static const ASMInstr asm_instrs[] = {
167 #define ALT(x) x
168 #define DEF_ASM_OP0(name, opcode)
169 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
170 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
171 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
172 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
173 #include "i386-asm.h"
174
175 /* last operation */
176 { 0, },
177 };
178
179 static const uint16_t op0_codes[] = {
180 #define ALT(x)
181 #define DEF_ASM_OP0(x, opcode) opcode,
182 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
183 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
184 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
185 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
186 #include "i386-asm.h"
187 };
188
189 static inline int get_reg_shift(TCCState *s1)
190 {
191 int shift, v;
192
193 v = asm_int_expr(s1);
194 switch(v) {
195 case 1:
196 shift = 0;
197 break;
198 case 2:
199 shift = 1;
200 break;
201 case 4:
202 shift = 2;
203 break;
204 case 8:
205 shift = 3;
206 break;
207 default:
208 expect("1, 2, 4 or 8 constant");
209 shift = 0;
210 break;
211 }
212 return shift;
213 }
214
215 static int asm_parse_reg(void)
216 {
217 int reg;
218 if (tok != '%')
219 goto error_32;
220 next();
221 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
222 reg = tok - TOK_ASM_eax;
223 next();
224 return reg;
225 } else {
226 error_32:
227 expect("32 bit register");
228 return 0;
229 }
230 }
231
232 static void parse_operand(TCCState *s1, Operand *op)
233 {
234 ExprValue e;
235 int reg, indir;
236 const char *p;
237
238 indir = 0;
239 if (tok == '*') {
240 next();
241 indir = OP_INDIR;
242 }
243
244 if (tok == '%') {
245 next();
246 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
247 reg = tok - TOK_ASM_al;
248 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
249 op->reg = reg & 7;
250 if ((op->type & OP_REG) && op->reg == TREG_EAX)
251 op->type |= OP_EAX;
252 else if (op->type == OP_REG8 && op->reg == TREG_ECX)
253 op->type |= OP_CL;
254 else if (op->type == OP_REG16 && op->reg == TREG_EDX)
255 op->type |= OP_DX;
256 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
257 op->type = OP_DB;
258 op->reg = tok - TOK_ASM_dr0;
259 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
260 op->type = OP_SEG;
261 op->reg = tok - TOK_ASM_es;
262 } else if (tok == TOK_ASM_st) {
263 op->type = OP_ST;
264 op->reg = 0;
265 next();
266 if (tok == '(') {
267 next();
268 if (tok != TOK_PPNUM)
269 goto reg_error;
270 p = tokc.cstr->data;
271 reg = p[0] - '0';
272 if ((unsigned)reg >= 8 || p[1] != '\0')
273 goto reg_error;
274 op->reg = reg;
275 next();
276 skip(')');
277 }
278 if (op->reg == 0)
279 op->type |= OP_ST0;
280 goto no_skip;
281 } else {
282 reg_error:
283 error("unknown register");
284 }
285 next();
286 no_skip: ;
287 } else if (tok == '$') {
288 /* constant value */
289 next();
290 asm_expr(s1, &e);
291 op->type = OP_IM32;
292 op->e.v = e.v;
293 op->e.sym = e.sym;
294 if (!op->e.sym) {
295 if (op->e.v == (uint8_t)op->e.v)
296 op->type |= OP_IM8;
297 if (op->e.v == (int8_t)op->e.v)
298 op->type |= OP_IM8S;
299 if (op->e.v == (uint16_t)op->e.v)
300 op->type |= OP_IM16;
301 }
302 } else {
303 /* address(reg,reg2,shift) with all variants */
304 op->type = OP_EA;
305 op->reg = -1;
306 op->reg2 = -1;
307 op->shift = 0;
308 if (tok != '(') {
309 asm_expr(s1, &e);
310 op->e.v = e.v;
311 op->e.sym = e.sym;
312 } else {
313 op->e.v = 0;
314 op->e.sym = NULL;
315 }
316 if (tok == '(') {
317 next();
318 if (tok != ',') {
319 op->reg = asm_parse_reg();
320 }
321 if (tok == ',') {
322 next();
323 if (tok != ',') {
324 op->reg2 = asm_parse_reg();
325 }
326 if (tok == ',') {
327 next();
328 op->shift = get_reg_shift(s1);
329 }
330 }
331 skip(')');
332 }
333 if (op->reg == -1 && op->reg2 == -1)
334 op->type |= OP_ADDR;
335 }
336 op->type |= indir;
337 }
338
339 /* XXX: unify with C code output ? */
340 static void gen_expr32(ExprValue *pe)
341 {
342 if (pe->sym)
343 greloc(cur_text_section, pe->sym, ind, R_386_32);
344 gen_le32(pe->v);
345 }
346
347 /* XXX: unify with C code output ? */
348 static void gen_disp32(ExprValue *pe)
349 {
350 Sym *sym;
351 sym = pe->sym;
352 if (sym) {
353 if (sym->r == cur_text_section->sh_num) {
354 /* same section: we can output an absolute value. Note
355 that the TCC compiler behaves differently here because
356 it always outputs a relocation to ease (future) code
357 elimination in the linker */
358 gen_le32(pe->v + (long)sym->next - ind - 4);
359 } else {
360 greloc(cur_text_section, sym, ind, R_386_PC32);
361 gen_le32(pe->v - 4);
362 }
363 } else {
364 /* put an empty PC32 relocation */
365 put_elf_reloc(symtab_section, cur_text_section,
366 ind, R_386_PC32, 0);
367 gen_le32(pe->v - 4);
368 }
369 }
370
371
372 static void gen_le16(int v)
373 {
374 g(v);
375 g(v >> 8);
376 }
377
378 /* generate the modrm operand */
379 static inline void asm_modrm(int reg, Operand *op)
380 {
381 int mod, reg1, reg2, sib_reg1;
382
383 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
384 g(0xc0 + (reg << 3) + op->reg);
385 } else if (op->reg == -1 && op->reg2 == -1) {
386 /* displacement only */
387 g(0x05 + (reg << 3));
388 gen_expr32(&op->e);
389 } else {
390 sib_reg1 = op->reg;
391 /* fist compute displacement encoding */
392 if (sib_reg1 == -1) {
393 sib_reg1 = 5;
394 mod = 0x00;
395 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
396 mod = 0x00;
397 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
398 mod = 0x40;
399 } else {
400 mod = 0x80;
401 }
402 /* compute if sib byte needed */
403 reg1 = op->reg;
404 if (op->reg2 != -1)
405 reg1 = 4;
406 g(mod + (reg << 3) + reg1);
407 if (reg1 == 4) {
408 /* add sib byte */
409 reg2 = op->reg2;
410 if (reg2 == -1)
411 reg2 = 4; /* indicate no index */
412 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
413 }
414
415 /* add offset */
416 if (mod == 0x40) {
417 g(op->e.v);
418 } else if (mod == 0x80 || op->reg == -1) {
419 gen_expr32(&op->e);
420 }
421 }
422 }
423
424 static void asm_opcode(TCCState *s1, int opcode)
425 {
426 const ASMInstr *pa;
427 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
428 int nb_ops, s, ss;
429 Operand ops[MAX_OPERANDS], *pop;
430 int op_type[3]; /* decoded op type */
431
432 /* get operands */
433 pop = ops;
434 nb_ops = 0;
435 seg_prefix = 0;
436 for(;;) {
437 if (tok == ';' || tok == TOK_LINEFEED)
438 break;
439 if (nb_ops >= MAX_OPERANDS) {
440 error("incorrect number of operands");
441 }
442 parse_operand(s1, pop);
443 if (tok == ':') {
444 if (pop->type != OP_SEG || seg_prefix) {
445 error("incorrect prefix");
446 }
447 seg_prefix = segment_prefixes[pop->reg];
448 next();
449 parse_operand(s1, pop);
450 if (!(pop->type & OP_EA)) {
451 error("segment prefix must be followed by memory reference");
452 }
453 }
454 pop++;
455 nb_ops++;
456 if (tok != ',')
457 break;
458 next();
459 }
460
461 is_short_jmp = 0;
462 s = 0; /* avoid warning */
463
464 /* optimize matching by using a lookup table (no hashing is needed
465 !) */
466 for(pa = asm_instrs; pa->sym != 0; pa++) {
467 s = 0;
468 if (pa->instr_type & OPC_FARITH) {
469 v = opcode - pa->sym;
470 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
471 continue;
472 } else if (pa->instr_type & OPC_ARITH) {
473 if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
474 continue;
475 goto compute_size;
476 } else if (pa->instr_type & OPC_SHIFT) {
477 if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
478 continue;
479 goto compute_size;
480 } else if (pa->instr_type & OPC_TEST) {
481 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
482 continue;
483 } else if (pa->instr_type & OPC_B) {
484 if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
485 continue;
486 compute_size:
487 s = (opcode - pa->sym) & 3;
488 } else if (pa->instr_type & OPC_WL) {
489 if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
490 continue;
491 s = opcode - pa->sym + 1;
492 } else {
493 if (pa->sym != opcode)
494 continue;
495 }
496 if (pa->nb_ops != nb_ops)
497 continue;
498 /* now decode and check each operand */
499 for(i = 0; i < nb_ops; i++) {
500 int op1, op2;
501 op1 = pa->op_type[i];
502 op2 = op1 & 0x1f;
503 switch(op2) {
504 case OPT_IM:
505 v = OP_IM8 | OP_IM16 | OP_IM32;
506 break;
507 case OPT_REG:
508 v = OP_REG8 | OP_REG16 | OP_REG32;
509 break;
510 case OPT_REGW:
511 v = OP_REG16 | OP_REG32;
512 break;
513 case OPT_IMW:
514 v = OP_IM16 | OP_IM32;
515 break;
516 default:
517 v = 1 << op2;
518 break;
519 }
520 if (op1 & OPT_EA)
521 v |= OP_EA;
522 op_type[i] = v;
523 if ((ops[i].type & v) == 0)
524 goto next;
525 }
526 /* all is matching ! */
527 break;
528 next: ;
529 }
530 if (pa->sym == 0) {
531 if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
532 int b;
533 b = op0_codes[opcode - TOK_ASM_pusha];
534 if (b & 0xff00)
535 g(b >> 8);
536 g(b);
537 return;
538 } else {
539 error("unknown opcode '%s'",
540 get_tok_str(opcode, NULL));
541 }
542 }
543 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
544 if (s == 3) {
545 for(i = 0; s == 3 && i < nb_ops; i++) {
546 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
547 s = reg_to_size[ops[i].type & OP_REG];
548 }
549 if (s == 3) {
550 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
551 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
552 s = 2;
553 else
554 error("cannot infer opcode suffix");
555 }
556 }
557
558 /* generate data16 prefix if needed */
559 ss = s;
560 if (s == 1 || (pa->instr_type & OPC_D16))
561 g(WORD_PREFIX_OPCODE);
562 else if (s == 2)
563 s = 1;
564 /* now generates the operation */
565 if (pa->instr_type & OPC_FWAIT)
566 g(0x9b);
567 if (seg_prefix)
568 g(seg_prefix);
569
570 v = pa->opcode;
571 if (v == 0x69 || v == 0x69) {
572 /* kludge for imul $im, %reg */
573 nb_ops = 3;
574 ops[2] = ops[1];
575 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
576 v--; /* int $3 case */
577 nb_ops = 0;
578 } else if ((v == 0x06 || v == 0x07)) {
579 if (ops[0].reg >= 4) {
580 /* push/pop %fs or %gs */
581 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
582 } else {
583 v += ops[0].reg << 3;
584 }
585 nb_ops = 0;
586 } else if (v <= 0x05) {
587 /* arith case */
588 v += ((opcode - TOK_ASM_addb) >> 2) << 3;
589 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
590 /* fpu arith case */
591 v += ((opcode - pa->sym) / 6) << 3;
592 }
593 if (pa->instr_type & OPC_REG) {
594 for(i = 0; i < nb_ops; i++) {
595 if (op_type[i] & (OP_REG | OP_ST)) {
596 v += ops[i].reg;
597 break;
598 }
599 }
600 /* mov $im, %reg case */
601 if (pa->opcode == 0xb0 && s >= 1)
602 v += 7;
603 }
604 if (pa->instr_type & OPC_B)
605 v += s;
606 if (pa->instr_type & OPC_TEST)
607 v += test_bits[opcode - pa->sym];
608 if (pa->instr_type & OPC_SHORTJMP) {
609 Sym *sym;
610 int jmp_disp;
611
612 /* see if we can really generate the jump with a byte offset */
613 sym = ops[0].e.sym;
614 if (!sym)
615 goto no_short_jump;
616 if (sym->r != cur_text_section->sh_num)
617 goto no_short_jump;
618 jmp_disp = ops[0].e.v + (long)sym->next - ind - 2;
619 if (jmp_disp == (int8_t)jmp_disp) {
620 /* OK to generate jump */
621 is_short_jmp = 1;
622 ops[0].e.v = jmp_disp;
623 } else {
624 no_short_jump:
625 if (pa->instr_type & OPC_JMP) {
626 /* long jump will be allowed. need to modify the
627 opcode slightly */
628 if (v == 0xeb)
629 v = 0xe9;
630 else
631 v += 0x0f10;
632 } else {
633 error("invalid displacement");
634 }
635 }
636 }
637 op1 = v >> 8;
638 if (op1)
639 g(op1);
640 g(v);
641
642 /* search which operand will used for modrm */
643 modrm_index = 0;
644 if (pa->instr_type & OPC_SHIFT) {
645 reg = (opcode - pa->sym) >> 2;
646 if (reg == 6)
647 reg = 7;
648 } else if (pa->instr_type & OPC_ARITH) {
649 reg = (opcode - pa->sym) >> 2;
650 } else if (pa->instr_type & OPC_FARITH) {
651 reg = (opcode - pa->sym) / 6;
652 } else {
653 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
654 }
655 if (pa->instr_type & OPC_MODRM) {
656 /* first look for an ea operand */
657 for(i = 0;i < nb_ops; i++) {
658 if (op_type[i] & OP_EA)
659 goto modrm_found;
660 }
661 /* then if not found, a register or indirection (shift instructions) */
662 for(i = 0;i < nb_ops; i++) {
663 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
664 goto modrm_found;
665 }
666 #ifdef ASM_DEBUG
667 error("bad op table");
668 #endif
669 modrm_found:
670 modrm_index = i;
671 /* if a register is used in another operand then it is
672 used instead of group */
673 for(i = 0;i < nb_ops; i++) {
674 v = op_type[i];
675 if (i != modrm_index &&
676 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
677 reg = ops[i].reg;
678 break;
679 }
680 }
681
682 asm_modrm(reg, &ops[modrm_index]);
683 }
684
685 /* emit constants */
686 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
687 /* ljmp or lcall kludge */
688 gen_expr32(&ops[1].e);
689 if (ops[0].e.sym)
690 error("cannot relocate");
691 gen_le16(ops[0].e.v);
692 } else {
693 for(i = 0;i < nb_ops; i++) {
694 v = op_type[i];
695 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
696 /* if multiple sizes are given it means we must look
697 at the op size */
698 if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
699 v == (OP_IM16 | OP_IM32)) {
700 if (ss == 0)
701 v = OP_IM8;
702 else if (ss == 1)
703 v = OP_IM16;
704 else
705 v = OP_IM32;
706 }
707 if (v & (OP_IM8 | OP_IM8S)) {
708 if (ops[i].e.sym)
709 goto error_relocate;
710 g(ops[i].e.v);
711 } else if (v & OP_IM16) {
712 if (ops[i].e.sym) {
713 error_relocate:
714 error("cannot relocate");
715 }
716 gen_le16(ops[i].e.v);
717 } else {
718 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
719 if (is_short_jmp)
720 g(ops[i].e.v);
721 else
722 gen_disp32(&ops[i].e);
723 } else {
724 gen_expr32(&ops[i].e);
725 }
726 }
727 }
728 }
729 }
730 }
731
732 #define NB_SAVED_REGS 3
733 #define NB_ASM_REGS 8
734
735 /* return the constraint priority (we allocate first the lowest
736 numbered constraints) */
737 static inline int constraint_priority(const char *str)
738 {
739 int priority, c, pr;
740
741 /* we take the lowest priority */
742 priority = 0;
743 for(;;) {
744 c = *str;
745 if (c == '\0')
746 break;
747 str++;
748 switch(c) {
749 case 'A':
750 pr = 0;
751 break;
752 case 'a':
753 case 'b':
754 case 'c':
755 case 'd':
756 case 'S':
757 case 'D':
758 pr = 1;
759 break;
760 case 'q':
761 pr = 2;
762 break;
763 case 'r':
764 pr = 3;
765 break;
766 case 'N':
767 case 'M':
768 case 'I':
769 case 'i':
770 case 'm':
771 case 'g':
772 pr = 4;
773 break;
774 default:
775 error("unknown constraint '%c'", c);
776 pr = 0;
777 }
778 if (pr > priority)
779 priority = pr;
780 }
781 return priority;
782 }
783
784 static const char *skip_constraint_modifiers(const char *p)
785 {
786 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
787 p++;
788 return p;
789 }
790
791 #define REG_OUT_MASK 0x01
792 #define REG_IN_MASK 0x02
793
794 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
795
796 static void asm_compute_constraints(ASMOperand *operands,
797 int nb_operands, int nb_outputs,
798 const uint8_t *clobber_regs,
799 int *pout_reg)
800 {
801 ASMOperand *op;
802 int sorted_op[MAX_ASM_OPERANDS];
803 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
804 const char *str;
805 uint8_t regs_allocated[NB_ASM_REGS];
806
807 /* init fields */
808 for(i=0;i<nb_operands;i++) {
809 op = &operands[i];
810 op->input_index = -1;
811 op->ref_index = -1;
812 op->reg = -1;
813 op->is_memory = 0;
814 op->is_rw = 0;
815 }
816 /* compute constraint priority and evaluate references to output
817 constraints if input constraints */
818 for(i=0;i<nb_operands;i++) {
819 op = &operands[i];
820 str = op->constraint;
821 str = skip_constraint_modifiers(str);
822 if (isnum(*str) || *str == '[') {
823 /* this is a reference to another constraint */
824 k = find_constraint(operands, nb_operands, str, NULL);
825 if ((unsigned)k >= i || i < nb_outputs)
826 error("invalid reference in constraint %d ('%s')",
827 i, str);
828 op->ref_index = k;
829 if (operands[k].input_index >= 0)
830 error("cannot reference twice the same operand");
831 operands[k].input_index = i;
832 op->priority = 5;
833 } else {
834 op->priority = constraint_priority(str);
835 }
836 }
837
838 /* sort operands according to their priority */
839 for(i=0;i<nb_operands;i++)
840 sorted_op[i] = i;
841 for(i=0;i<nb_operands - 1;i++) {
842 for(j=i+1;j<nb_operands;j++) {
843 p1 = operands[sorted_op[i]].priority;
844 p2 = operands[sorted_op[j]].priority;
845 if (p2 < p1) {
846 tmp = sorted_op[i];
847 sorted_op[i] = sorted_op[j];
848 sorted_op[j] = tmp;
849 }
850 }
851 }
852
853 for(i = 0;i < NB_ASM_REGS; i++) {
854 if (clobber_regs[i])
855 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
856 else
857 regs_allocated[i] = 0;
858 }
859 /* esp cannot be used */
860 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
861 /* ebp cannot be used yet */
862 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
863
864 /* allocate registers and generate corresponding asm moves */
865 for(i=0;i<nb_operands;i++) {
866 j = sorted_op[i];
867 op = &operands[j];
868 str = op->constraint;
869 /* no need to allocate references */
870 if (op->ref_index >= 0)
871 continue;
872 /* select if register is used for output, input or both */
873 if (op->input_index >= 0) {
874 reg_mask = REG_IN_MASK | REG_OUT_MASK;
875 } else if (j < nb_outputs) {
876 reg_mask = REG_OUT_MASK;
877 } else {
878 reg_mask = REG_IN_MASK;
879 }
880 try_next:
881 c = *str++;
882 switch(c) {
883 case '=':
884 goto try_next;
885 case '+':
886 op->is_rw = 1;
887 /* FALL THRU */
888 case '&':
889 if (j >= nb_outputs)
890 error("'%c' modifier can only be applied to outputs", c);
891 reg_mask = REG_IN_MASK | REG_OUT_MASK;
892 goto try_next;
893 case 'A':
894 /* allocate both eax and edx */
895 if (is_reg_allocated(TREG_EAX) ||
896 is_reg_allocated(TREG_EDX))
897 goto try_next;
898 op->is_llong = 1;
899 op->reg = TREG_EAX;
900 regs_allocated[TREG_EAX] |= reg_mask;
901 regs_allocated[TREG_EDX] |= reg_mask;
902 break;
903 case 'a':
904 reg = TREG_EAX;
905 goto alloc_reg;
906 case 'b':
907 reg = 3;
908 goto alloc_reg;
909 case 'c':
910 reg = TREG_ECX;
911 goto alloc_reg;
912 case 'd':
913 reg = TREG_EDX;
914 goto alloc_reg;
915 case 'S':
916 reg = 6;
917 goto alloc_reg;
918 case 'D':
919 reg = 7;
920 alloc_reg:
921 if (is_reg_allocated(reg))
922 goto try_next;
923 goto reg_found;
924 case 'q':
925 /* eax, ebx, ecx or edx */
926 for(reg = 0; reg < 4; reg++) {
927 if (!is_reg_allocated(reg))
928 goto reg_found;
929 }
930 goto try_next;
931 case 'r':
932 /* any general register */
933 for(reg = 0; reg < 8; reg++) {
934 if (!is_reg_allocated(reg))
935 goto reg_found;
936 }
937 goto try_next;
938 reg_found:
939 /* now we can reload in the register */
940 op->is_llong = 0;
941 op->reg = reg;
942 regs_allocated[reg] |= reg_mask;
943 break;
944 case 'i':
945 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
946 goto try_next;
947 break;
948 case 'I':
949 case 'N':
950 case 'M':
951 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
952 goto try_next;
953 break;
954 case 'm':
955 case 'g':
956 /* nothing special to do because the operand is already in
957 memory, except if the pointer itself is stored in a
958 memory variable (VT_LLOCAL case) */
959 /* XXX: fix constant case */
960 /* if it is a reference to a memory zone, it must lie
961 in a register, so we reserve the register in the
962 input registers and a load will be generated
963 later */
964 if (j < nb_outputs || c == 'm') {
965 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
966 /* any general register */
967 for(reg = 0; reg < 8; reg++) {
968 if (!(regs_allocated[reg] & REG_IN_MASK))
969 goto reg_found1;
970 }
971 goto try_next;
972 reg_found1:
973 /* now we can reload in the register */
974 regs_allocated[reg] |= REG_IN_MASK;
975 op->reg = reg;
976 op->is_memory = 1;
977 }
978 }
979 break;
980 default:
981 error("asm constraint %d ('%s') could not be satisfied",
982 j, op->constraint);
983 break;
984 }
985 /* if a reference is present for that operand, we assign it too */
986 if (op->input_index >= 0) {
987 operands[op->input_index].reg = op->reg;
988 operands[op->input_index].is_llong = op->is_llong;
989 }
990 }
991
992 /* compute out_reg. It is used to store outputs registers to memory
993 locations references by pointers (VT_LLOCAL case) */
994 *pout_reg = -1;
995 for(i=0;i<nb_operands;i++) {
996 op = &operands[i];
997 if (op->reg >= 0 &&
998 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
999 !op->is_memory) {
1000 for(reg = 0; reg < 8; reg++) {
1001 if (!(regs_allocated[reg] & REG_OUT_MASK))
1002 goto reg_found2;
1003 }
1004 error("could not find free output register for reloading");
1005 reg_found2:
1006 *pout_reg = reg;
1007 break;
1008 }
1009 }
1010
1011 /* print sorted constraints */
1012 #ifdef ASM_DEBUG
1013 for(i=0;i<nb_operands;i++) {
1014 j = sorted_op[i];
1015 op = &operands[j];
1016 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1017 j,
1018 op->id ? get_tok_str(op->id, NULL) : "",
1019 op->constraint,
1020 op->vt->r,
1021 op->reg);
1022 }
1023 if (*pout_reg >= 0)
1024 printf("out_reg=%d\n", *pout_reg);
1025 #endif
1026 }
1027
1028 static void subst_asm_operand(CString *add_str,
1029 SValue *sv, int modifier)
1030 {
1031 int r, reg, size, val;
1032 char buf[64];
1033
1034 r = sv->r;
1035 if ((r & VT_VALMASK) == VT_CONST) {
1036 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1037 cstr_ccat(add_str, '$');
1038 if (r & VT_SYM) {
1039 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1040 if (sv->c.i != 0) {
1041 cstr_ccat(add_str, '+');
1042 } else {
1043 return;
1044 }
1045 }
1046 val = sv->c.i;
1047 if (modifier == 'n')
1048 val = -val;
1049 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1050 cstr_cat(add_str, buf);
1051 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1052 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1053 cstr_cat(add_str, buf);
1054 } else if (r & VT_LVAL) {
1055 reg = r & VT_VALMASK;
1056 if (reg >= VT_CONST)
1057 error("internal compiler error");
1058 snprintf(buf, sizeof(buf), "(%%%s)",
1059 get_tok_str(TOK_ASM_eax + reg, NULL));
1060 cstr_cat(add_str, buf);
1061 } else {
1062 /* register case */
1063 reg = r & VT_VALMASK;
1064 if (reg >= VT_CONST)
1065 error("internal compiler error");
1066
1067 /* choose register operand size */
1068 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1069 size = 1;
1070 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1071 size = 2;
1072 else
1073 size = 4;
1074 if (size == 1 && reg >= 4)
1075 size = 4;
1076
1077 if (modifier == 'b') {
1078 if (reg >= 4)
1079 error("cannot use byte register");
1080 size = 1;
1081 } else if (modifier == 'h') {
1082 if (reg >= 4)
1083 error("cannot use byte register");
1084 size = -1;
1085 } else if (modifier == 'w') {
1086 size = 2;
1087 }
1088
1089 switch(size) {
1090 case -1:
1091 reg = TOK_ASM_ah + reg;
1092 break;
1093 case 1:
1094 reg = TOK_ASM_al + reg;
1095 break;
1096 case 2:
1097 reg = TOK_ASM_ax + reg;
1098 break;
1099 default:
1100 reg = TOK_ASM_eax + reg;
1101 break;
1102 }
1103 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1104 cstr_cat(add_str, buf);
1105 }
1106 }
1107
1108 /* generate prolog and epilog code for asm statment */
1109 static void asm_gen_code(ASMOperand *operands, int nb_operands,
1110 int nb_outputs, int is_output,
1111 uint8_t *clobber_regs,
1112 int out_reg)
1113 {
1114 uint8_t regs_allocated[NB_ASM_REGS];
1115 ASMOperand *op;
1116 int i, reg;
1117 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1118
1119 /* mark all used registers */
1120 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1121 for(i = 0; i < nb_operands;i++) {
1122 op = &operands[i];
1123 if (op->reg >= 0)
1124 regs_allocated[op->reg] = 1;
1125 }
1126 if (!is_output) {
1127 /* generate reg save code */
1128 for(i = 0; i < NB_SAVED_REGS; i++) {
1129 reg = reg_saved[i];
1130 if (regs_allocated[reg])
1131 g(0x50 + reg);
1132 }
1133
1134 /* generate load code */
1135 for(i = 0; i < nb_operands; i++) {
1136 op = &operands[i];
1137 if (op->reg >= 0) {
1138 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1139 op->is_memory) {
1140 /* memory reference case (for both input and
1141 output cases) */
1142 SValue sv;
1143 sv = *op->vt;
1144 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1145 load(op->reg, &sv);
1146 } else if (i >= nb_outputs || op->is_rw) {
1147 /* load value in register */
1148 load(op->reg, op->vt);
1149 if (op->is_llong) {
1150 SValue sv;
1151 sv = *op->vt;
1152 sv.c.ul += 4;
1153 load(TREG_EDX, &sv);
1154 }
1155 }
1156 }
1157 }
1158 } else {
1159 /* generate save code */
1160 for(i = 0 ; i < nb_outputs; i++) {
1161 op = &operands[i];
1162 if (op->reg >= 0) {
1163 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1164 if (!op->is_memory) {
1165 SValue sv;
1166 sv = *op->vt;
1167 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1168 load(out_reg, &sv);
1169
1170 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1171 store(op->reg, &sv);
1172 }
1173 } else {
1174 store(op->reg, op->vt);
1175 if (op->is_llong) {
1176 SValue sv;
1177 sv = *op->vt;
1178 sv.c.ul += 4;
1179 store(TREG_EDX, &sv);
1180 }
1181 }
1182 }
1183 }
1184 /* generate reg restore code */
1185 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1186 reg = reg_saved[i];
1187 if (regs_allocated[reg])
1188 g(0x58 + reg);
1189 }
1190 }
1191 }
1192
1193 static void asm_clobber(uint8_t *clobber_regs, const char *str)
1194 {
1195 int reg;
1196 TokenSym *ts;
1197
1198 if (!strcmp(str, "memory") ||
1199 !strcmp(str, "cc"))
1200 return;
1201 ts = tok_alloc(str, strlen(str));
1202 reg = ts->tok;
1203 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1204 reg -= TOK_ASM_eax;
1205 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1206 reg -= TOK_ASM_ax;
1207 } else {
1208 error("invalid clobber register '%s'", str);
1209 }
1210 clobber_regs[reg] = 1;
1211 }
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