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Use functions to get relocation info
[tinycc/jakubkaszycki.git] / i386-asm.c
bloba7563ab0a42fcde220a776248e6f3ff1f45bea3f
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "tcc.h"
23
24 /* #define NB_ASM_REGS 8 */
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
27
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30 #define TOK_ASM_alllast TOK_ASM_pxor
31
32 #define OPC_JMP 0x01 /* jmp operand */
33 #define OPC_B 0x02 /* only used with OPC_WL */
34 #define OPC_WL 0x04 /* accepts w, l or no suffix */
35 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
36 #define OPC_REG 0x08 /* register is added to opcode */
37 #define OPC_MODRM 0x10 /* modrm encoding */
38 #define OPC_FWAIT 0x20 /* add fwait opcode */
39 #define OPC_TEST 0x40 /* test opcodes */
40 #define OPC_SHIFT 0x80 /* shift opcodes */
41 #define OPC_D16 0x0100 /* generate data16 prefix */
42 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
43 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
44 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
45 #ifdef TCC_TARGET_X86_64
46 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
47 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
48 # define OPC_WLX OPC_WLQ
49 # define OPC_BWLX OPC_BWLQ
50 #else
51 # define OPC_WLX OPC_WL
52 # define OPC_BWLX OPC_BWL
53 #endif
54
55 #define OPC_GROUP_SHIFT 13
56
57 /* in order to compress the operand type, we use specific operands and
58 we or only with EA */
59 enum {
60 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
61 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
62 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
63 #ifdef TCC_TARGET_X86_64
64 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
65 #endif
66 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
67 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
70 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
71 OPT_SEG,
72 OPT_ST,
73 OPT_IM8,
74 OPT_IM8S,
75 OPT_IM16,
76 OPT_IM32,
77 #ifdef TCC_TARGET_X86_64
78 OPT_IM64,
79 #endif
80 OPT_EAX, /* %al, %ax, %eax or %rax register */
81 OPT_ST0, /* %st(0) register */
82 OPT_CL, /* %cl register */
83 OPT_DX, /* %dx register */
84 OPT_ADDR, /* OP_EA with only offset */
85 OPT_INDIR, /* *(expr) */
86 /* composite types */
87 OPT_COMPOSITE_FIRST,
88 OPT_IM, /* IM8 | IM16 | IM32 */
89 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
90 OPT_REGW, /* REG16 | REG32 | REG64 */
91 OPT_IMW, /* IM16 | IM32 */
92 /* can be ored with any OPT_xxx */
93 OPT_EA = 0x80
94 };
95
96 #define OP_REG8 (1 << OPT_REG8)
97 #define OP_REG16 (1 << OPT_REG16)
98 #define OP_REG32 (1 << OPT_REG32)
99 #define OP_MMX (1 << OPT_MMX)
100 #define OP_SSE (1 << OPT_SSE)
101 #define OP_CR (1 << OPT_CR)
102 #define OP_TR (1 << OPT_TR)
103 #define OP_DB (1 << OPT_DB)
104 #define OP_SEG (1 << OPT_SEG)
105 #define OP_ST (1 << OPT_ST)
106 #define OP_IM8 (1 << OPT_IM8)
107 #define OP_IM8S (1 << OPT_IM8S)
108 #define OP_IM16 (1 << OPT_IM16)
109 #define OP_IM32 (1 << OPT_IM32)
110 #define OP_EAX (1 << OPT_EAX)
111 #define OP_ST0 (1 << OPT_ST0)
112 #define OP_CL (1 << OPT_CL)
113 #define OP_DX (1 << OPT_DX)
114 #define OP_ADDR (1 << OPT_ADDR)
115 #define OP_INDIR (1 << OPT_INDIR)
116 #ifdef TCC_TARGET_X86_64
117 # define OP_REG64 (1 << OPT_REG64)
118 # define OP_IM64 (1 << OPT_IM64)
119 # define OP_EA32 (OP_EA << 1)
120 #else
121 # define OP_REG64 0
122 # define OP_IM64 0
123 # define OP_EA32 0
124 #endif
125
126 #define OP_EA 0x40000000
127 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
128
129 #ifdef TCC_TARGET_X86_64
130 # define TREG_XAX TREG_RAX
131 # define TREG_XCX TREG_RCX
132 # define TREG_XDX TREG_RDX
133 #else
134 # define TREG_XAX TREG_EAX
135 # define TREG_XCX TREG_ECX
136 # define TREG_XDX TREG_EDX
137 #endif
138
139 typedef struct ASMInstr {
140 uint16_t sym;
141 uint16_t opcode;
142 uint16_t instr_type;
143 uint8_t nb_ops;
144 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
145 } ASMInstr;
146
147 typedef struct Operand {
148 uint32_t type;
149 int8_t reg; /* register, -1 if none */
150 int8_t reg2; /* second register, -1 if none */
151 uint8_t shift;
152 ExprValue e;
153 } Operand;
154
155 static const uint8_t reg_to_size[9] = {
156 /*
157 [OP_REG8] = 0,
158 [OP_REG16] = 1,
159 [OP_REG32] = 2,
160 #ifdef TCC_TARGET_X86_64
161 [OP_REG64] = 3,
162 #endif
163 */
164 0, 0, 1, 0, 2, 0, 0, 0, 3
165 };
166
167 #define NB_TEST_OPCODES 30
168
169 static const uint8_t test_bits[NB_TEST_OPCODES] = {
170 0x00, /* o */
171 0x01, /* no */
172 0x02, /* b */
173 0x02, /* c */
174 0x02, /* nae */
175 0x03, /* nb */
176 0x03, /* nc */
177 0x03, /* ae */
178 0x04, /* e */
179 0x04, /* z */
180 0x05, /* ne */
181 0x05, /* nz */
182 0x06, /* be */
183 0x06, /* na */
184 0x07, /* nbe */
185 0x07, /* a */
186 0x08, /* s */
187 0x09, /* ns */
188 0x0a, /* p */
189 0x0a, /* pe */
190 0x0b, /* np */
191 0x0b, /* po */
192 0x0c, /* l */
193 0x0c, /* nge */
194 0x0d, /* nl */
195 0x0d, /* ge */
196 0x0e, /* le */
197 0x0e, /* ng */
198 0x0f, /* nle */
199 0x0f, /* g */
200 };
201
202 static const uint8_t segment_prefixes[] = {
203 0x26, /* es */
204 0x2e, /* cs */
205 0x36, /* ss */
206 0x3e, /* ds */
207 0x64, /* fs */
208 0x65 /* gs */
209 };
210
211 static const ASMInstr asm_instrs[] = {
212 #define ALT(x) x
213 #define DEF_ASM_OP0(name, opcode)
214 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
215 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
216 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
217 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
218 #ifdef TCC_TARGET_X86_64
219 # include "x86_64-asm.h"
220 #else
221 # include "i386-asm.h"
222 #endif
223 /* last operation */
224 { 0, },
225 };
226
227 static const uint16_t op0_codes[] = {
228 #define ALT(x)
229 #define DEF_ASM_OP0(x, opcode) opcode,
230 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
231 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
232 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
233 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
234 #ifdef TCC_TARGET_X86_64
235 # include "x86_64-asm.h"
236 #else
237 # include "i386-asm.h"
238 #endif
239 };
240
241 static inline int get_reg_shift(TCCState *s1)
242 {
243 int shift, v;
244 v = asm_int_expr(s1);
245 switch(v) {
246 case 1:
247 shift = 0;
248 break;
249 case 2:
250 shift = 1;
251 break;
252 case 4:
253 shift = 2;
254 break;
255 case 8:
256 shift = 3;
257 break;
258 default:
259 expect("1, 2, 4 or 8 constant");
260 shift = 0;
261 break;
262 }
263 return shift;
264 }
265
266 static int asm_parse_reg(int *type)
267 {
268 int reg = 0;
269 *type = 0;
270 if (tok != '%')
271 goto error_32;
272 next();
273 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
274 reg = tok - TOK_ASM_eax;
275 #ifdef TCC_TARGET_X86_64
276 *type = OP_EA32;
277 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
278 reg = tok - TOK_ASM_rax;
279 } else if (tok == TOK_ASM_rip) {
280 reg = 8;
281 #endif
282 } else {
283 error_32:
284 expect("register");
285 }
286 next();
287 return reg;
288 }
289
290 static void parse_operand(TCCState *s1, Operand *op)
291 {
292 ExprValue e;
293 int reg, indir;
294 const char *p;
295
296 indir = 0;
297 if (tok == '*') {
298 next();
299 indir = OP_INDIR;
300 }
301
302 if (tok == '%') {
303 next();
304 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
305 reg = tok - TOK_ASM_al;
306 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
307 op->reg = reg & 7;
308 if ((op->type & OP_REG) && op->reg == TREG_XAX)
309 op->type |= OP_EAX;
310 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
311 op->type |= OP_CL;
312 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
313 op->type |= OP_DX;
314 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
315 op->type = OP_DB;
316 op->reg = tok - TOK_ASM_dr0;
317 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
318 op->type = OP_SEG;
319 op->reg = tok - TOK_ASM_es;
320 } else if (tok == TOK_ASM_st) {
321 op->type = OP_ST;
322 op->reg = 0;
323 next();
324 if (tok == '(') {
325 next();
326 if (tok != TOK_PPNUM)
327 goto reg_error;
328 p = tokc.str.data;
329 reg = p[0] - '0';
330 if ((unsigned)reg >= 8 || p[1] != '\0')
331 goto reg_error;
332 op->reg = reg;
333 next();
334 skip(')');
335 }
336 if (op->reg == 0)
337 op->type |= OP_ST0;
338 goto no_skip;
339 } else {
340 reg_error:
341 tcc_error("unknown register");
342 }
343 next();
344 no_skip: ;
345 } else if (tok == '$') {
346 /* constant value */
347 next();
348 asm_expr(s1, &e);
349 op->type = OP_IM32;
350 op->e.v = e.v;
351 op->e.sym = e.sym;
352 if (!op->e.sym) {
353 if (op->e.v == (uint8_t)op->e.v)
354 op->type |= OP_IM8;
355 if (op->e.v == (int8_t)op->e.v)
356 op->type |= OP_IM8S;
357 if (op->e.v == (uint16_t)op->e.v)
358 op->type |= OP_IM16;
359 #ifdef TCC_TARGET_X86_64
360 if (op->e.v != (int32_t)op->e.v)
361 op->type = OP_IM64;
362 #endif
363 }
364 } else {
365 /* address(reg,reg2,shift) with all variants */
366 op->type = OP_EA;
367 op->reg = -1;
368 op->reg2 = -1;
369 op->shift = 0;
370 if (tok != '(') {
371 asm_expr(s1, &e);
372 op->e.v = e.v;
373 op->e.sym = e.sym;
374 } else {
375 next();
376 if (tok == '%') {
377 unget_tok('(');
378 op->e.v = 0;
379 op->e.sym = NULL;
380 } else {
381 /* bracketed offset expression */
382 asm_expr(s1, &e);
383 if (tok != ')')
384 expect(")");
385 next();
386 op->e.v = e.v;
387 op->e.sym = e.sym;
388 }
389 }
390 if (tok == '(') {
391 int type = 0;
392 next();
393 if (tok != ',') {
394 op->reg = asm_parse_reg(&type);
395 }
396 if (tok == ',') {
397 next();
398 if (tok != ',') {
399 op->reg2 = asm_parse_reg(&type);
400 }
401 if (tok == ',') {
402 next();
403 op->shift = get_reg_shift(s1);
404 }
405 }
406 if (type & OP_EA32)
407 op->type |= OP_EA32;
408 skip(')');
409 }
410 if (op->reg == -1 && op->reg2 == -1)
411 op->type |= OP_ADDR;
412 }
413 op->type |= indir;
414 }
415
416 /* XXX: unify with C code output ? */
417 ST_FUNC void gen_expr32(ExprValue *pe)
418 {
419 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
420 }
421
422 #ifdef TCC_TARGET_X86_64
423 static void gen_expr64(ExprValue *pe)
424 {
425 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
426 }
427 #endif
428
429 /* XXX: unify with C code output ? */
430 static void gen_disp32(ExprValue *pe)
431 {
432 Sym *sym = pe->sym;
433 if (sym && sym->r == cur_text_section->sh_num) {
434 /* same section: we can output an absolute value. Note
435 that the TCC compiler behaves differently here because
436 it always outputs a relocation to ease (future) code
437 elimination in the linker */
438 gen_le32(pe->v + sym->jnext - ind - 4);
439 } else {
440 if (sym && sym->type.t == VT_VOID) {
441 sym->type.t = VT_FUNC;
442 sym->type.ref = NULL;
443 }
444 gen_addrpc32(VT_SYM, sym, pe->v);
445 }
446 }
447
448 /* generate the modrm operand */
449 static inline int asm_modrm(int reg, Operand *op)
450 {
451 int mod, reg1, reg2, sib_reg1;
452
453 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
454 g(0xc0 + (reg << 3) + op->reg);
455 } else if (op->reg == -1 && op->reg2 == -1) {
456 /* displacement only */
457 #ifdef TCC_TARGET_X86_64
458 g(0x04 + (reg << 3));
459 g(0x25);
460 #else
461 g(0x05 + (reg << 3));
462 #endif
463 gen_expr32(&op->e);
464 #ifdef TCC_TARGET_X86_64
465 } else if (op->reg == 8) {
466 ExprValue *pe = &op->e;
467 g(0x05 + (reg << 3));
468 gen_addrpc32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
469 return ind;
470 #endif
471 } else {
472 sib_reg1 = op->reg;
473 /* fist compute displacement encoding */
474 if (sib_reg1 == -1) {
475 sib_reg1 = 5;
476 mod = 0x00;
477 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
478 mod = 0x00;
479 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
480 mod = 0x40;
481 } else {
482 mod = 0x80;
483 }
484 /* compute if sib byte needed */
485 reg1 = op->reg;
486 if (op->reg2 != -1)
487 reg1 = 4;
488 g(mod + (reg << 3) + reg1);
489 if (reg1 == 4) {
490 /* add sib byte */
491 reg2 = op->reg2;
492 if (reg2 == -1)
493 reg2 = 4; /* indicate no index */
494 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
495 }
496 /* add offset */
497 if (mod == 0x40) {
498 g(op->e.v);
499 } else if (mod == 0x80 || op->reg == -1) {
500 gen_expr32(&op->e);
501 }
502 }
503 return 0;
504 }
505
506 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
507 {
508 const ASMInstr *pa;
509 int i, modrm_index, reg, v, op1, seg_prefix, pc;
510 int nb_ops, s;
511 Operand ops[MAX_OPERANDS], *pop;
512 int op_type[3]; /* decoded op type */
513 int alltypes; /* OR of all operand types */
514 int autosize;
515
516 /* force synthetic ';' after prefix instruction, so we can handle */
517 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
518 if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
519 unget_tok(';');
520
521 /* get operands */
522 pop = ops;
523 nb_ops = 0;
524 seg_prefix = 0;
525 alltypes = 0;
526 for(;;) {
527 if (tok == ';' || tok == TOK_LINEFEED)
528 break;
529 if (nb_ops >= MAX_OPERANDS) {
530 tcc_error("incorrect number of operands");
531 }
532 parse_operand(s1, pop);
533 if (tok == ':') {
534 if (pop->type != OP_SEG || seg_prefix)
535 tcc_error("incorrect prefix");
536 seg_prefix = segment_prefixes[pop->reg];
537 next();
538 parse_operand(s1, pop);
539 if (!(pop->type & OP_EA)) {
540 tcc_error("segment prefix must be followed by memory reference");
541 }
542 }
543 pop++;
544 nb_ops++;
545 if (tok != ',')
546 break;
547 next();
548 }
549
550 s = 0; /* avoid warning */
551
552 /* optimize matching by using a lookup table (no hashing is needed
553 !) */
554 for(pa = asm_instrs; pa->sym != 0; pa++) {
555 s = 0;
556 if (pa->instr_type & OPC_FARITH) {
557 v = opcode - pa->sym;
558 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
559 continue;
560 } else if (pa->instr_type & OPC_ARITH) {
561 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
562 continue;
563 s = (opcode - pa->sym) % NBWLX;
564 if ((pa->instr_type & OPC_BWLX) == OPC_WLX)
565 {
566 /* We need to reject the xxxb opcodes that we accepted above.
567 Note that pa->sym for WLX opcodes is the 'w' token,
568 to get the 'b' token subtract one. */
569 if (((opcode - pa->sym + 1) % NBWLX) == 0)
570 continue;
571 s++;
572 }
573 } else if (pa->instr_type & OPC_SHIFT) {
574 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
575 continue;
576 s = (opcode - pa->sym) % NBWLX;
577 } else if (pa->instr_type & OPC_TEST) {
578 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
579 continue;
580 /* cmovxx is a test opcode but accepts multiple sizes.
581 TCC doesn't accept the suffixed mnemonic, instead we
582 simply force size autodetection always. */
583 if (pa->instr_type & OPC_WLX)
584 s = NBWLX - 1;
585 } else if (pa->instr_type & OPC_B) {
586 #ifdef TCC_TARGET_X86_64
587 /* Some instructions don't have the full size but only
588 bwl form. insb e.g. */
589 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
590 && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
591 continue;
592 #endif
593 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
594 continue;
595 s = opcode - pa->sym;
596 } else if (pa->instr_type & OPC_WLX) {
597 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
598 continue;
599 s = opcode - pa->sym + 1;
600 } else {
601 if (pa->sym != opcode)
602 continue;
603 }
604 if (pa->nb_ops != nb_ops)
605 continue;
606 #ifdef TCC_TARGET_X86_64
607 /* Special case for moves. Selecting the IM64->REG64 form
608 should only be done if we really have an >32bit imm64, and that
609 is hardcoded. Ignore it here. */
610 if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
611 && ops[1].type == OP_REG64)
612 continue;
613 #endif
614 /* now decode and check each operand */
615 alltypes = 0;
616 for(i = 0; i < nb_ops; i++) {
617 int op1, op2;
618 op1 = pa->op_type[i];
619 op2 = op1 & 0x1f;
620 switch(op2) {
621 case OPT_IM:
622 v = OP_IM8 | OP_IM16 | OP_IM32;
623 break;
624 case OPT_REG:
625 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
626 break;
627 case OPT_REGW:
628 v = OP_REG16 | OP_REG32 | OP_REG64;
629 break;
630 case OPT_IMW:
631 v = OP_IM16 | OP_IM32;
632 break;
633 default:
634 v = 1 << op2;
635 break;
636 }
637 if (op1 & OPT_EA)
638 v |= OP_EA;
639 op_type[i] = v;
640 if ((ops[i].type & v) == 0)
641 goto next;
642 alltypes |= ops[i].type;
643 }
644 /* all is matching ! */
645 break;
646 next: ;
647 }
648 if (pa->sym == 0) {
649 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
650 int b;
651 b = op0_codes[opcode - TOK_ASM_first];
652 if (b & 0xff00)
653 g(b >> 8);
654 g(b);
655 return;
656 } else if (opcode <= TOK_ASM_alllast) {
657 tcc_error("bad operand with opcode '%s'",
658 get_tok_str(opcode, NULL));
659 } else {
660 tcc_error("unknown opcode '%s'",
661 get_tok_str(opcode, NULL));
662 }
663 }
664 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
665 autosize = NBWLX-1;
666 #ifdef TCC_TARGET_X86_64
667 /* XXX the autosize should rather be zero, to not have to adjust this
668 all the time. */
669 if ((pa->instr_type & OPC_BWLQ) == OPC_B)
670 autosize = NBWLX-2;
671 #endif
672 if (s == autosize) {
673 for(i = 0; s == autosize && i < nb_ops; i++) {
674 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
675 s = reg_to_size[ops[i].type & OP_REG];
676 }
677 if (s == autosize) {
678 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
679 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
680 s = 2;
681 else
682 tcc_error("cannot infer opcode suffix");
683 }
684 }
685
686 #ifdef TCC_TARGET_X86_64
687 /* Generate addr32 prefix if needed */
688 for(i = 0; i < nb_ops; i++) {
689 if (ops[i].type & OP_EA32) {
690 g(0x67);
691 break;
692 }
693 }
694 #endif
695 /* generate data16 prefix if needed */
696 if (s == 1 || (pa->instr_type & OPC_D16))
697 g(0x66);
698 #ifdef TCC_TARGET_X86_64
699 if (s == 3 || (alltypes & OP_REG64)) {
700 /* generate REX prefix */
701 int default64 = 0;
702 for(i = 0; i < nb_ops; i++) {
703 if (op_type[i] == OP_REG64) {
704 /* If only 64bit regs are accepted in one operand
705 this is a default64 instruction without need for
706 REX prefixes. */
707 default64 = 1;
708 break;
709 }
710 }
711 /* XXX find better encoding for the default64 instructions. */
712 if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
713 && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
714 && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
715 && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
716 && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
717 && !default64)
718 g(0x48);
719 }
720 #endif
721
722 /* now generates the operation */
723 if (pa->instr_type & OPC_FWAIT)
724 g(0x9b);
725 if (seg_prefix)
726 g(seg_prefix);
727
728 v = pa->opcode;
729 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
730 /* kludge for imul $im, %reg */
731 nb_ops = 3;
732 ops[2] = ops[1];
733 op_type[2] = op_type[1];
734 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
735 v--; /* int $3 case */
736 nb_ops = 0;
737 } else if ((v == 0x06 || v == 0x07)) {
738 if (ops[0].reg >= 4) {
739 /* push/pop %fs or %gs */
740 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
741 } else {
742 v += ops[0].reg << 3;
743 }
744 nb_ops = 0;
745 } else if (v <= 0x05) {
746 /* arith case */
747 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
748 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
749 /* fpu arith case */
750 v += ((opcode - pa->sym) / 6) << 3;
751 }
752 if (pa->instr_type & OPC_REG) {
753 for(i = 0; i < nb_ops; i++) {
754 if (op_type[i] & (OP_REG | OP_ST)) {
755 v += ops[i].reg;
756 break;
757 }
758 }
759 /* mov $im, %reg case */
760 if (pa->opcode == 0xb0 && s >= 1)
761 v += 7;
762 }
763 if (pa->instr_type & OPC_B)
764 v += s >= 1;
765 if (pa->instr_type & OPC_TEST)
766 v += test_bits[opcode - pa->sym];
767 if (pa->instr_type & OPC_SHORTJMP) {
768 Sym *sym;
769 int jmp_disp;
770
771 /* see if we can really generate the jump with a byte offset */
772 sym = ops[0].e.sym;
773 if (!sym)
774 goto no_short_jump;
775 if (sym->r != cur_text_section->sh_num)
776 goto no_short_jump;
777 jmp_disp = ops[0].e.v + sym->jnext - ind - 2 - (v >= 0xff);
778 if (jmp_disp == (int8_t)jmp_disp) {
779 /* OK to generate jump */
780 ops[0].e.sym = 0;
781 ops[0].e.v = jmp_disp;
782 op_type[0] = OP_IM8S;
783 } else {
784 no_short_jump:
785 if (pa->instr_type & OPC_JMP) {
786 /* long jump will be allowed. need to modify the
787 opcode slightly */
788 if (v == 0xeb)
789 v = 0xe9;
790 else
791 v += 0x0f10;
792 } else {
793 tcc_error("invalid displacement");
794 }
795 }
796 }
797 op1 = v >> 8;
798 if (op1)
799 g(op1);
800 g(v);
801
802 /* search which operand will used for modrm */
803 modrm_index = 0;
804 if (pa->instr_type & OPC_SHIFT) {
805 reg = (opcode - pa->sym) / NBWLX;
806 if (reg == 6)
807 reg = 7;
808 } else if (pa->instr_type & OPC_ARITH) {
809 reg = (opcode - pa->sym) / NBWLX;
810 } else if (pa->instr_type & OPC_FARITH) {
811 reg = (opcode - pa->sym) / 6;
812 } else {
813 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
814 }
815
816 pc = 0;
817 if (pa->instr_type & OPC_MODRM) {
818 /* first look for an ea operand */
819 for(i = 0;i < nb_ops; i++) {
820 if (op_type[i] & OP_EA)
821 goto modrm_found;
822 }
823 /* then if not found, a register or indirection (shift instructions) */
824 for(i = 0;i < nb_ops; i++) {
825 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
826 goto modrm_found;
827 }
828 #ifdef ASM_DEBUG
829 tcc_error("bad op table");
830 #endif
831 modrm_found:
832 modrm_index = i;
833 /* if a register is used in another operand then it is
834 used instead of group */
835 for(i = 0;i < nb_ops; i++) {
836 v = op_type[i];
837 if (i != modrm_index &&
838 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
839 reg = ops[i].reg;
840 break;
841 }
842 }
843 pc = asm_modrm(reg, &ops[modrm_index]);
844 }
845
846 /* emit constants */
847 #ifndef TCC_TARGET_X86_64
848 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
849 /* ljmp or lcall kludge */
850 gen_expr32(&ops[1].e);
851 if (ops[0].e.sym)
852 tcc_error("cannot relocate");
853 gen_le16(ops[0].e.v);
854 return;
855 }
856 #endif
857 for(i = 0;i < nb_ops; i++) {
858 v = op_type[i];
859 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
860 /* if multiple sizes are given it means we must look
861 at the op size */
862 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
863 if (s == 0)
864 v = OP_IM8;
865 else if (s == 1)
866 v = OP_IM16;
867 else if (s == 2 || (v & OP_IM64) == 0)
868 v = OP_IM32;
869 else
870 v = OP_IM64;
871 }
872
873 if ((v & (OP_IM8 | OP_IM8S | OP_IM16)) && ops[i].e.sym)
874 tcc_error("cannot relocate");
875
876 if (v & (OP_IM8 | OP_IM8S)) {
877 g(ops[i].e.v);
878 } else if (v & OP_IM16) {
879 gen_le16(ops[i].e.v);
880 #ifdef TCC_TARGET_X86_64
881 } else if (v & OP_IM64) {
882 gen_expr64(&ops[i].e);
883 #endif
884 } else if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
885 gen_disp32(&ops[i].e);
886 } else {
887 gen_expr32(&ops[i].e);
888 }
889 }
890 }
891
892 /* after immediate operands, adjust pc-relative address */
893 if (pc)
894 add32le(text_section->data + pc - 4, pc - ind);
895 }
896
897 /* return the constraint priority (we allocate first the lowest
898 numbered constraints) */
899 static inline int constraint_priority(const char *str)
900 {
901 int priority, c, pr;
902
903 /* we take the lowest priority */
904 priority = 0;
905 for(;;) {
906 c = *str;
907 if (c == '\0')
908 break;
909 str++;
910 switch(c) {
911 case 'A':
912 pr = 0;
913 break;
914 case 'a':
915 case 'b':
916 case 'c':
917 case 'd':
918 case 'S':
919 case 'D':
920 pr = 1;
921 break;
922 case 'q':
923 pr = 2;
924 break;
925 case 'r':
926 pr = 3;
927 break;
928 case 'N':
929 case 'M':
930 case 'I':
931 case 'i':
932 case 'm':
933 case 'g':
934 pr = 4;
935 break;
936 default:
937 tcc_error("unknown constraint '%c'", c);
938 pr = 0;
939 }
940 if (pr > priority)
941 priority = pr;
942 }
943 return priority;
944 }
945
946 static const char *skip_constraint_modifiers(const char *p)
947 {
948 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
949 p++;
950 return p;
951 }
952
953 #define REG_OUT_MASK 0x01
954 #define REG_IN_MASK 0x02
955
956 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
957
958 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
959 int nb_operands, int nb_outputs,
960 const uint8_t *clobber_regs,
961 int *pout_reg)
962 {
963 ASMOperand *op;
964 int sorted_op[MAX_ASM_OPERANDS];
965 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
966 const char *str;
967 uint8_t regs_allocated[NB_ASM_REGS];
968
969 /* init fields */
970 for(i=0;i<nb_operands;i++) {
971 op = &operands[i];
972 op->input_index = -1;
973 op->ref_index = -1;
974 op->reg = -1;
975 op->is_memory = 0;
976 op->is_rw = 0;
977 }
978 /* compute constraint priority and evaluate references to output
979 constraints if input constraints */
980 for(i=0;i<nb_operands;i++) {
981 op = &operands[i];
982 str = op->constraint;
983 str = skip_constraint_modifiers(str);
984 if (isnum(*str) || *str == '[') {
985 /* this is a reference to another constraint */
986 k = find_constraint(operands, nb_operands, str, NULL);
987 if ((unsigned)k >= i || i < nb_outputs)
988 tcc_error("invalid reference in constraint %d ('%s')",
989 i, str);
990 op->ref_index = k;
991 if (operands[k].input_index >= 0)
992 tcc_error("cannot reference twice the same operand");
993 operands[k].input_index = i;
994 op->priority = 5;
995 } else {
996 op->priority = constraint_priority(str);
997 }
998 }
999
1000 /* sort operands according to their priority */
1001 for(i=0;i<nb_operands;i++)
1002 sorted_op[i] = i;
1003 for(i=0;i<nb_operands - 1;i++) {
1004 for(j=i+1;j<nb_operands;j++) {
1005 p1 = operands[sorted_op[i]].priority;
1006 p2 = operands[sorted_op[j]].priority;
1007 if (p2 < p1) {
1008 tmp = sorted_op[i];
1009 sorted_op[i] = sorted_op[j];
1010 sorted_op[j] = tmp;
1011 }
1012 }
1013 }
1014
1015 for(i = 0;i < NB_ASM_REGS; i++) {
1016 if (clobber_regs[i])
1017 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1018 else
1019 regs_allocated[i] = 0;
1020 }
1021 /* esp cannot be used */
1022 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1023 /* ebp cannot be used yet */
1024 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1025
1026 /* allocate registers and generate corresponding asm moves */
1027 for(i=0;i<nb_operands;i++) {
1028 j = sorted_op[i];
1029 op = &operands[j];
1030 str = op->constraint;
1031 /* no need to allocate references */
1032 if (op->ref_index >= 0)
1033 continue;
1034 /* select if register is used for output, input or both */
1035 if (op->input_index >= 0) {
1036 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1037 } else if (j < nb_outputs) {
1038 reg_mask = REG_OUT_MASK;
1039 } else {
1040 reg_mask = REG_IN_MASK;
1041 }
1042 try_next:
1043 c = *str++;
1044 switch(c) {
1045 case '=':
1046 goto try_next;
1047 case '+':
1048 op->is_rw = 1;
1049 /* FALL THRU */
1050 case '&':
1051 if (j >= nb_outputs)
1052 tcc_error("'%c' modifier can only be applied to outputs", c);
1053 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1054 goto try_next;
1055 case 'A':
1056 /* allocate both eax and edx */
1057 if (is_reg_allocated(TREG_XAX) ||
1058 is_reg_allocated(TREG_XDX))
1059 goto try_next;
1060 op->is_llong = 1;
1061 op->reg = TREG_XAX;
1062 regs_allocated[TREG_XAX] |= reg_mask;
1063 regs_allocated[TREG_XDX] |= reg_mask;
1064 break;
1065 case 'a':
1066 reg = TREG_XAX;
1067 goto alloc_reg;
1068 case 'b':
1069 reg = 3;
1070 goto alloc_reg;
1071 case 'c':
1072 reg = TREG_XCX;
1073 goto alloc_reg;
1074 case 'd':
1075 reg = TREG_XDX;
1076 goto alloc_reg;
1077 case 'S':
1078 reg = 6;
1079 goto alloc_reg;
1080 case 'D':
1081 reg = 7;
1082 alloc_reg:
1083 if (is_reg_allocated(reg))
1084 goto try_next;
1085 goto reg_found;
1086 case 'q':
1087 /* eax, ebx, ecx or edx */
1088 for(reg = 0; reg < 4; reg++) {
1089 if (!is_reg_allocated(reg))
1090 goto reg_found;
1091 }
1092 goto try_next;
1093 case 'r':
1094 /* any general register */
1095 for(reg = 0; reg < 8; reg++) {
1096 if (!is_reg_allocated(reg))
1097 goto reg_found;
1098 }
1099 goto try_next;
1100 reg_found:
1101 /* now we can reload in the register */
1102 op->is_llong = 0;
1103 op->reg = reg;
1104 regs_allocated[reg] |= reg_mask;
1105 break;
1106 case 'i':
1107 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1108 goto try_next;
1109 break;
1110 case 'I':
1111 case 'N':
1112 case 'M':
1113 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1114 goto try_next;
1115 break;
1116 case 'm':
1117 case 'g':
1118 /* nothing special to do because the operand is already in
1119 memory, except if the pointer itself is stored in a
1120 memory variable (VT_LLOCAL case) */
1121 /* XXX: fix constant case */
1122 /* if it is a reference to a memory zone, it must lie
1123 in a register, so we reserve the register in the
1124 input registers and a load will be generated
1125 later */
1126 if (j < nb_outputs || c == 'm') {
1127 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1128 /* any general register */
1129 for(reg = 0; reg < 8; reg++) {
1130 if (!(regs_allocated[reg] & REG_IN_MASK))
1131 goto reg_found1;
1132 }
1133 goto try_next;
1134 reg_found1:
1135 /* now we can reload in the register */
1136 regs_allocated[reg] |= REG_IN_MASK;
1137 op->reg = reg;
1138 op->is_memory = 1;
1139 }
1140 }
1141 break;
1142 default:
1143 tcc_error("asm constraint %d ('%s') could not be satisfied",
1144 j, op->constraint);
1145 break;
1146 }
1147 /* if a reference is present for that operand, we assign it too */
1148 if (op->input_index >= 0) {
1149 operands[op->input_index].reg = op->reg;
1150 operands[op->input_index].is_llong = op->is_llong;
1151 }
1152 }
1153
1154 /* compute out_reg. It is used to store outputs registers to memory
1155 locations references by pointers (VT_LLOCAL case) */
1156 *pout_reg = -1;
1157 for(i=0;i<nb_operands;i++) {
1158 op = &operands[i];
1159 if (op->reg >= 0 &&
1160 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1161 !op->is_memory) {
1162 for(reg = 0; reg < 8; reg++) {
1163 if (!(regs_allocated[reg] & REG_OUT_MASK))
1164 goto reg_found2;
1165 }
1166 tcc_error("could not find free output register for reloading");
1167 reg_found2:
1168 *pout_reg = reg;
1169 break;
1170 }
1171 }
1172
1173 /* print sorted constraints */
1174 #ifdef ASM_DEBUG
1175 for(i=0;i<nb_operands;i++) {
1176 j = sorted_op[i];
1177 op = &operands[j];
1178 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1179 j,
1180 op->id ? get_tok_str(op->id, NULL) : "",
1181 op->constraint,
1182 op->vt->r,
1183 op->reg);
1184 }
1185 if (*pout_reg >= 0)
1186 printf("out_reg=%d\n", *pout_reg);
1187 #endif
1188 }
1189
1190 ST_FUNC void subst_asm_operand(CString *add_str,
1191 SValue *sv, int modifier)
1192 {
1193 int r, reg, size, val;
1194 char buf[64];
1195
1196 r = sv->r;
1197 if ((r & VT_VALMASK) == VT_CONST) {
1198 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1199 cstr_ccat(add_str, '$');
1200 if (r & VT_SYM) {
1201 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL), -1);
1202 if ((uint32_t)sv->c.i == 0)
1203 goto no_offset;
1204 cstr_ccat(add_str, '+');
1205 }
1206 val = sv->c.i;
1207 if (modifier == 'n')
1208 val = -val;
1209 snprintf(buf, sizeof(buf), "%d", (int)sv->c.i);
1210 cstr_cat(add_str, buf, -1);
1211 no_offset:;
1212 #ifdef TCC_TARGET_X86_64
1213 if (r & VT_LVAL)
1214 cstr_cat(add_str, "(%rip)", -1);
1215 #endif
1216 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1217 #ifdef TCC_TARGET_X86_64
1218 snprintf(buf, sizeof(buf), "%d(%%rbp)", (int)sv->c.i);
1219 #else
1220 snprintf(buf, sizeof(buf), "%d(%%ebp)", (int)sv->c.i);
1221 #endif
1222 cstr_cat(add_str, buf, -1);
1223 } else if (r & VT_LVAL) {
1224 reg = r & VT_VALMASK;
1225 if (reg >= VT_CONST)
1226 tcc_error("internal compiler error");
1227 snprintf(buf, sizeof(buf), "(%%%s)",
1228 #ifdef TCC_TARGET_X86_64
1229 get_tok_str(TOK_ASM_rax + reg, NULL)
1230 #else
1231 get_tok_str(TOK_ASM_eax + reg, NULL)
1232 #endif
1233 );
1234 cstr_cat(add_str, buf, -1);
1235 } else {
1236 /* register case */
1237 reg = r & VT_VALMASK;
1238 if (reg >= VT_CONST)
1239 tcc_error("internal compiler error");
1240
1241 /* choose register operand size */
1242 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1243 size = 1;
1244 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1245 size = 2;
1246 #ifdef TCC_TARGET_X86_64
1247 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1248 size = 8;
1249 #endif
1250 else
1251 size = 4;
1252 if (size == 1 && reg >= 4)
1253 size = 4;
1254
1255 if (modifier == 'b') {
1256 if (reg >= 4)
1257 tcc_error("cannot use byte register");
1258 size = 1;
1259 } else if (modifier == 'h') {
1260 if (reg >= 4)
1261 tcc_error("cannot use byte register");
1262 size = -1;
1263 } else if (modifier == 'w') {
1264 size = 2;
1265 } else if (modifier == 'k') {
1266 size = 4;
1267 #ifdef TCC_TARGET_X86_64
1268 } else if (modifier == 'q') {
1269 size = 8;
1270 #endif
1271 }
1272
1273 switch(size) {
1274 case -1:
1275 reg = TOK_ASM_ah + reg;
1276 break;
1277 case 1:
1278 reg = TOK_ASM_al + reg;
1279 break;
1280 case 2:
1281 reg = TOK_ASM_ax + reg;
1282 break;
1283 default:
1284 reg = TOK_ASM_eax + reg;
1285 break;
1286 #ifdef TCC_TARGET_X86_64
1287 case 8:
1288 reg = TOK_ASM_rax + reg;
1289 break;
1290 #endif
1291 }
1292 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1293 cstr_cat(add_str, buf, -1);
1294 }
1295 }
1296
1297 /* generate prolog and epilog code for asm statement */
1298 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1299 int nb_outputs, int is_output,
1300 uint8_t *clobber_regs,
1301 int out_reg)
1302 {
1303 uint8_t regs_allocated[NB_ASM_REGS];
1304 ASMOperand *op;
1305 int i, reg;
1306 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1307
1308 /* mark all used registers */
1309 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1310 for(i = 0; i < nb_operands;i++) {
1311 op = &operands[i];
1312 if (op->reg >= 0)
1313 regs_allocated[op->reg] = 1;
1314 }
1315 if (!is_output) {
1316 /* generate reg save code */
1317 for(i = 0; i < NB_SAVED_REGS; i++) {
1318 reg = reg_saved[i];
1319 if (regs_allocated[reg]) {
1320 g(0x50 + reg);
1321 }
1322 }
1323
1324 /* generate load code */
1325 for(i = 0; i < nb_operands; i++) {
1326 op = &operands[i];
1327 if (op->reg >= 0) {
1328 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1329 op->is_memory) {
1330 /* memory reference case (for both input and
1331 output cases) */
1332 SValue sv;
1333 sv = *op->vt;
1334 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL;
1335 sv.type.t = VT_PTR;
1336 load(op->reg, &sv);
1337 } else if (i >= nb_outputs || op->is_rw) {
1338 /* load value in register */
1339 load(op->reg, op->vt);
1340 if (op->is_llong) {
1341 SValue sv;
1342 sv = *op->vt;
1343 sv.c.i += 4;
1344 load(TREG_XDX, &sv);
1345 }
1346 }
1347 }
1348 }
1349 } else {
1350 /* generate save code */
1351 for(i = 0 ; i < nb_outputs; i++) {
1352 op = &operands[i];
1353 if (op->reg >= 0) {
1354 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1355 if (!op->is_memory) {
1356 SValue sv;
1357 sv = *op->vt;
1358 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1359 load(out_reg, &sv);
1360
1361 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1362 store(op->reg, &sv);
1363 }
1364 } else {
1365 store(op->reg, op->vt);
1366 if (op->is_llong) {
1367 SValue sv;
1368 sv = *op->vt;
1369 sv.c.i += 4;
1370 store(TREG_XDX, &sv);
1371 }
1372 }
1373 }
1374 }
1375 /* generate reg restore code */
1376 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1377 reg = reg_saved[i];
1378 if (regs_allocated[reg]) {
1379 g(0x58 + reg);
1380 }
1381 }
1382 }
1383 }
1384
1385 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1386 {
1387 int reg;
1388 TokenSym *ts;
1389
1390 if (!strcmp(str, "memory") ||
1391 !strcmp(str, "cc"))
1392 return;
1393 ts = tok_alloc(str, strlen(str));
1394 reg = ts->tok;
1395 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1396 reg -= TOK_ASM_eax;
1397 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1398 reg -= TOK_ASM_ax;
1399 #ifdef TCC_TARGET_X86_64
1400 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1401 reg -= TOK_ASM_rax;
1402 #endif
1403 } else {
1404 tcc_error("invalid clobber register '%s'", str);
1405 }
1406 clobber_regs[reg] = 1;
1407 }
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