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selinux: correct ftruncate, fix bus error in tcc -run
[tinycc.git] / i386-asm.c
blob075d2eabb738f9aa98b7e3fb2cc1930a82b771b4
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "tcc.h"
23
24 // #define NB_ASM_REGS 8
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
27
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30
31 #define OPC_JMP 0x01 /* jmp operand */
32 #define OPC_B 0x02 /* only used with OPC_WL */
33 #define OPC_WL 0x04 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x08 /* register is added to opcode */
36 #define OPC_MODRM 0x10 /* modrm encoding */
37 #define OPC_FWAIT 0x20 /* add fwait opcode */
38 #define OPC_TEST 0x40 /* test opcodes */
39 #define OPC_SHIFT 0x80 /* shift opcodes */
40 #define OPC_D16 0x0100 /* generate data16 prefix */
41 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
42 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
43 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
44 #ifdef TCC_TARGET_X86_64
45 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
46 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
47 # define OPC_WLX OPC_WLQ
48 #else
49 # define OPC_WLX OPC_WL
50 #endif
51
52 #define OPC_GROUP_SHIFT 13
53
54 /* in order to compress the operand type, we use specific operands and
55 we or only with EA */
56 enum {
57 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
58 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
59 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
60 #ifdef TCC_TARGET_X86_64
61 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
62 #endif
63 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
65 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
66 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
67 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_SEG,
69 OPT_ST,
70 OPT_IM8,
71 OPT_IM8S,
72 OPT_IM16,
73 OPT_IM32,
74 #ifdef TCC_TARGET_X86_64
75 OPT_IM64,
76 #endif
77 OPT_EAX, /* %al, %ax, %eax or %rax register */
78 OPT_ST0, /* %st(0) register */
79 OPT_CL, /* %cl register */
80 OPT_DX, /* %dx register */
81 OPT_ADDR, /* OP_EA with only offset */
82 OPT_INDIR, /* *(expr) */
83 /* composite types */
84 OPT_COMPOSITE_FIRST,
85 OPT_IM, /* IM8 | IM16 | IM32 | IM64 */
86 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
87 OPT_REGW, /* REG16 | REG32 | REG64 */
88 OPT_IMW, /* IM16 | IM32 | IM64 */
89 #ifdef TCC_TARGET_X86_64
90 OPT_IMNO64, /* IM16 | IM32 */
91 #endif
92 /* can be ored with any OPT_xxx */
93 OPT_EA = 0x80
94 };
95
96 #define OP_REG8 (1 << OPT_REG8)
97 #define OP_REG16 (1 << OPT_REG16)
98 #define OP_REG32 (1 << OPT_REG32)
99 #define OP_MMX (1 << OPT_MMX)
100 #define OP_SSE (1 << OPT_SSE)
101 #define OP_CR (1 << OPT_CR)
102 #define OP_TR (1 << OPT_TR)
103 #define OP_DB (1 << OPT_DB)
104 #define OP_SEG (1 << OPT_SEG)
105 #define OP_ST (1 << OPT_ST)
106 #define OP_IM8 (1 << OPT_IM8)
107 #define OP_IM8S (1 << OPT_IM8S)
108 #define OP_IM16 (1 << OPT_IM16)
109 #define OP_IM32 (1 << OPT_IM32)
110 #define OP_EAX (1 << OPT_EAX)
111 #define OP_ST0 (1 << OPT_ST0)
112 #define OP_CL (1 << OPT_CL)
113 #define OP_DX (1 << OPT_DX)
114 #define OP_ADDR (1 << OPT_ADDR)
115 #define OP_INDIR (1 << OPT_INDIR)
116 #ifdef TCC_TARGET_X86_64
117 # define OP_REG64 (1 << OPT_REG64)
118 # define OP_IM64 (1 << OPT_IM64)
119 #else
120 # define OP_REG64 0
121 # define OP_IM64 0
122 #endif
123
124 #define OP_EA 0x40000000
125 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
126
127 #ifdef TCC_TARGET_X86_64
128 # define OP_IM OP_IM64
129 # define TREG_XAX TREG_RAX
130 # define TREG_XCX TREG_RCX
131 # define TREG_XDX TREG_RDX
132 #else
133 # define OP_IM OP_IM32
134 # define TREG_XAX TREG_EAX
135 # define TREG_XCX TREG_ECX
136 # define TREG_XDX TREG_EDX
137 #endif
138
139 typedef struct ASMInstr {
140 uint16_t sym;
141 uint16_t opcode;
142 uint16_t instr_type;
143 uint8_t nb_ops;
144 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
145 } ASMInstr;
146
147 typedef struct Operand {
148 uint32_t type;
149 int8_t reg; /* register, -1 if none */
150 int8_t reg2; /* second register, -1 if none */
151 uint8_t shift;
152 ExprValue e;
153 } Operand;
154
155 static const uint8_t reg_to_size[9] = {
156 /*
157 [OP_REG8] = 0,
158 [OP_REG16] = 1,
159 [OP_REG32] = 2,
160 #ifdef TCC_TARGET_X86_64
161 [OP_REG64] = 3,
162 #endif
163 */
164 0, 0, 1, 0, 2, 0, 0, 0, 3
165 };
166
167 #define NB_TEST_OPCODES 30
168
169 static const uint8_t test_bits[NB_TEST_OPCODES] = {
170 0x00, /* o */
171 0x01, /* no */
172 0x02, /* b */
173 0x02, /* c */
174 0x02, /* nae */
175 0x03, /* nb */
176 0x03, /* nc */
177 0x03, /* ae */
178 0x04, /* e */
179 0x04, /* z */
180 0x05, /* ne */
181 0x05, /* nz */
182 0x06, /* be */
183 0x06, /* na */
184 0x07, /* nbe */
185 0x07, /* a */
186 0x08, /* s */
187 0x09, /* ns */
188 0x0a, /* p */
189 0x0a, /* pe */
190 0x0b, /* np */
191 0x0b, /* po */
192 0x0c, /* l */
193 0x0c, /* nge */
194 0x0d, /* nl */
195 0x0d, /* ge */
196 0x0e, /* le */
197 0x0e, /* ng */
198 0x0f, /* nle */
199 0x0f, /* g */
200 };
201
202 static const uint8_t segment_prefixes[] = {
203 0x26, /* es */
204 0x2e, /* cs */
205 0x36, /* ss */
206 0x3e, /* ds */
207 0x64, /* fs */
208 0x65 /* gs */
209 };
210
211 static const ASMInstr asm_instrs[] = {
212 #define ALT(x) x
213 #define DEF_ASM_OP0(name, opcode)
214 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
215 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
216 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
217 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
218 #ifdef TCC_TARGET_X86_64
219 # include "x86_64-asm.h"
220 #else
221 # include "i386-asm.h"
222 #endif
223 /* last operation */
224 { 0, },
225 };
226
227 static const uint16_t op0_codes[] = {
228 #define ALT(x)
229 #define DEF_ASM_OP0(x, opcode) opcode,
230 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
231 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
232 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
233 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
234 #ifdef TCC_TARGET_X86_64
235 # include "x86_64-asm.h"
236 #else
237 # include "i386-asm.h"
238 #endif
239 };
240
241 static inline int get_reg_shift(TCCState *s1)
242 {
243 int shift, v;
244 #ifdef I386_ASM_16
245 if (s1->seg_size == 16)
246 error("invalid effective address");
247 #endif
248 v = asm_int_expr(s1);
249 switch(v) {
250 case 1:
251 shift = 0;
252 break;
253 case 2:
254 shift = 1;
255 break;
256 case 4:
257 shift = 2;
258 break;
259 case 8:
260 shift = 3;
261 break;
262 default:
263 expect("1, 2, 4 or 8 constant");
264 shift = 0;
265 break;
266 }
267 return shift;
268 }
269
270 static int asm_parse_reg(void)
271 {
272 int reg = 0;
273 if (tok != '%')
274 goto error_32;
275 next();
276 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
277 reg = tok - TOK_ASM_eax;
278 #ifdef TCC_TARGET_X86_64
279 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
280 reg = tok - TOK_ASM_rax;
281 #endif
282 #ifdef I386_ASM_16
283 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
284 reg = tok - TOK_ASM_ax;
285 #endif
286 } else {
287 error_32:
288 expect("register");
289 }
290 next();
291 return reg;
292 }
293
294 static void parse_operand(TCCState *s1, Operand *op)
295 {
296 ExprValue e;
297 int reg, indir;
298 const char *p;
299
300 indir = 0;
301 if (tok == '*') {
302 next();
303 indir = OP_INDIR;
304 }
305
306 if (tok == '%') {
307 next();
308 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
309 reg = tok - TOK_ASM_al;
310 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
311 op->reg = reg & 7;
312 if ((op->type & OP_REG) && op->reg == TREG_XAX)
313 op->type |= OP_EAX;
314 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
315 op->type |= OP_CL;
316 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
317 op->type |= OP_DX;
318 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
319 op->type = OP_DB;
320 op->reg = tok - TOK_ASM_dr0;
321 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
322 op->type = OP_SEG;
323 op->reg = tok - TOK_ASM_es;
324 } else if (tok == TOK_ASM_st) {
325 op->type = OP_ST;
326 op->reg = 0;
327 next();
328 if (tok == '(') {
329 next();
330 if (tok != TOK_PPNUM)
331 goto reg_error;
332 p = tokc.cstr->data;
333 reg = p[0] - '0';
334 if ((unsigned)reg >= 8 || p[1] != '\0')
335 goto reg_error;
336 op->reg = reg;
337 next();
338 skip(')');
339 }
340 if (op->reg == 0)
341 op->type |= OP_ST0;
342 goto no_skip;
343 } else {
344 reg_error:
345 error("unknown register");
346 }
347 next();
348 no_skip: ;
349 } else if (tok == '$') {
350 /* constant value */
351 next();
352 asm_expr(s1, &e);
353 op->type = OP_IM;
354 op->e.v = e.v;
355 op->e.sym = e.sym;
356 if (!op->e.sym) {
357 if (op->e.v == (uint8_t)op->e.v)
358 op->type |= OP_IM8;
359 if (op->e.v == (int8_t)op->e.v)
360 op->type |= OP_IM8S;
361 if (op->e.v == (uint16_t)op->e.v)
362 op->type |= OP_IM16;
363 #ifdef TCC_TARGET_X86_64
364 if (op->e.v == (uint32_t)op->e.v)
365 op->type |= OP_IM32;
366 #endif
367 }
368 } else {
369 /* address(reg,reg2,shift) with all variants */
370 op->type = OP_EA;
371 op->reg = -1;
372 op->reg2 = -1;
373 op->shift = 0;
374 if (tok != '(') {
375 asm_expr(s1, &e);
376 op->e.v = e.v;
377 op->e.sym = e.sym;
378 } else {
379 op->e.v = 0;
380 op->e.sym = NULL;
381 }
382 if (tok == '(') {
383 next();
384 if (tok != ',') {
385 op->reg = asm_parse_reg();
386 }
387 if (tok == ',') {
388 next();
389 if (tok != ',') {
390 op->reg2 = asm_parse_reg();
391 }
392 if (tok == ',') {
393 next();
394 op->shift = get_reg_shift(s1);
395 }
396 }
397 skip(')');
398 }
399 if (op->reg == -1 && op->reg2 == -1)
400 op->type |= OP_ADDR;
401 }
402 op->type |= indir;
403 }
404
405 /* XXX: unify with C code output ? */
406 ST_FUNC void gen_expr32(ExprValue *pe)
407 {
408 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
409 }
410
411 #ifdef TCC_TARGET_X86_64
412 static void gen_expr64(ExprValue *pe)
413 {
414 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
415 }
416 #endif
417
418 /* XXX: unify with C code output ? */
419 static void gen_disp32(ExprValue *pe)
420 {
421 Sym *sym = pe->sym;
422 if (sym && sym->r == cur_text_section->sh_num) {
423 /* same section: we can output an absolute value. Note
424 that the TCC compiler behaves differently here because
425 it always outputs a relocation to ease (future) code
426 elimination in the linker */
427 gen_le32(pe->v + sym->jnext - ind - 4);
428 } else {
429 if (sym && sym->type.t == VT_VOID) {
430 sym->type.t = VT_FUNC;
431 sym->type.ref = NULL;
432 }
433 gen_addrpc32(VT_SYM, sym, pe->v);
434 }
435 }
436
437 #ifdef I386_ASM_16
438 static void gen_expr16(ExprValue *pe)
439 {
440 if (pe->sym)
441 greloc(cur_text_section, pe->sym, ind, R_386_16);
442 gen_le16(pe->v);
443 }
444 static void gen_disp16(ExprValue *pe)
445 {
446 Sym *sym;
447 sym = pe->sym;
448 if (sym) {
449 if (sym->r == cur_text_section->sh_num) {
450 /* same section: we can output an absolute value. Note
451 that the TCC compiler behaves differently here because
452 it always outputs a relocation to ease (future) code
453 elimination in the linker */
454 gen_le16(pe->v + sym->jnext - ind - 2);
455 } else {
456 greloc(cur_text_section, sym, ind, R_386_PC16);
457 gen_le16(pe->v - 2);
458 }
459 } else {
460 /* put an empty PC32 relocation */
461 put_elf_reloc(symtab_section, cur_text_section,
462 ind, R_386_PC16, 0);
463 gen_le16(pe->v - 2);
464 }
465 }
466 #endif
467
468 /* generate the modrm operand */
469 static inline void asm_modrm(int reg, Operand *op)
470 {
471 int mod, reg1, reg2, sib_reg1;
472
473 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
474 g(0xc0 + (reg << 3) + op->reg);
475 } else if (op->reg == -1 && op->reg2 == -1) {
476 /* displacement only */
477 #ifdef I386_ASM_16
478 if (tcc_state->seg_size == 16) {
479 g(0x06 + (reg << 3));
480 gen_expr16(&op->e);
481 } else if (tcc_state->seg_size == 32)
482 #endif
483 {
484 g(0x05 + (reg << 3));
485 gen_expr32(&op->e);
486 }
487 } else {
488 sib_reg1 = op->reg;
489 /* fist compute displacement encoding */
490 if (sib_reg1 == -1) {
491 sib_reg1 = 5;
492 mod = 0x00;
493 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
494 mod = 0x00;
495 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
496 mod = 0x40;
497 } else {
498 mod = 0x80;
499 }
500 /* compute if sib byte needed */
501 reg1 = op->reg;
502 if (op->reg2 != -1)
503 reg1 = 4;
504 #ifdef I386_ASM_16
505 if (tcc_state->seg_size == 32) {
506 #endif
507 g(mod + (reg << 3) + reg1);
508 if (reg1 == 4) {
509 /* add sib byte */
510 reg2 = op->reg2;
511 if (reg2 == -1)
512 reg2 = 4; /* indicate no index */
513 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
514 }
515 #ifdef I386_ASM_16
516 } else if (tcc_state->seg_size == 16) {
517 /* edi = 7, esi = 6 --> di = 5, si = 4 */
518 if ((reg1 == 6) || (reg1 == 7)) {
519 reg1 -= 2;
520 /* ebx = 3 --> bx = 7 */
521 } else if (reg1 == 3) {
522 reg1 = 7;
523 /* o32 = 5 --> o16 = 6 */
524 } else if (reg1 == 5) {
525 reg1 = 6;
526 /* sib not valid in 16-bit mode */
527 } else if (reg1 == 4) {
528 reg2 = op->reg2;
529 /* bp + si + offset */
530 if ((sib_reg1 == 5) && (reg2 == 6)) {
531 reg1 = 2;
532 /* bp + di + offset */
533 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
534 reg1 = 3;
535 /* bx + si + offset */
536 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
537 reg1 = 0;
538 /* bx + di + offset */
539 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
540 reg1 = 1;
541 } else {
542 error("invalid effective address");
543 }
544 if (op->e.v == 0)
545 mod = 0;
546 } else {
547 error("invalid register");
548 }
549 g(mod + (reg << 3) + reg1);
550 }
551 #endif
552 /* add offset */
553 if (mod == 0x40) {
554 g(op->e.v);
555 } else if (mod == 0x80 || op->reg == -1) {
556 #ifdef I386_ASM_16
557 if (tcc_state->seg_size == 16)
558 gen_expr16(&op->e);
559 else if (tcc_state->seg_size == 32)
560 #endif
561 gen_expr32(&op->e);
562 }
563 }
564 }
565
566 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
567 {
568 const ASMInstr *pa;
569 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
570 int nb_ops, s;
571 Operand ops[MAX_OPERANDS], *pop;
572 int op_type[3]; /* decoded op type */
573 #ifdef I386_ASM_16
574 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
575 #endif
576
577 /* get operands */
578 pop = ops;
579 nb_ops = 0;
580 seg_prefix = 0;
581 for(;;) {
582 if (tok == ';' || tok == TOK_LINEFEED)
583 break;
584 if (nb_ops >= MAX_OPERANDS) {
585 error("incorrect number of operands");
586 }
587 parse_operand(s1, pop);
588 if (tok == ':') {
589 if (pop->type != OP_SEG || seg_prefix)
590 error("incorrect prefix");
591 seg_prefix = segment_prefixes[pop->reg];
592 next();
593 parse_operand(s1, pop);
594 #ifndef I386_ASM_16
595 if (!(pop->type & OP_EA)) {
596 error("segment prefix must be followed by memory reference");
597 }
598 #endif
599 }
600 pop++;
601 nb_ops++;
602 if (tok != ',')
603 break;
604 next();
605 }
606
607 is_short_jmp = 0;
608 s = 0; /* avoid warning */
609
610 /* optimize matching by using a lookup table (no hashing is needed
611 !) */
612 for(pa = asm_instrs; pa->sym != 0; pa++) {
613 s = 0;
614 if (pa->instr_type & OPC_FARITH) {
615 v = opcode - pa->sym;
616 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
617 continue;
618 } else if (pa->instr_type & OPC_ARITH) {
619 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
620 continue;
621 s = (opcode - pa->sym) % NBWLX;
622 } else if (pa->instr_type & OPC_SHIFT) {
623 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
624 continue;
625 s = (opcode - pa->sym) % NBWLX;
626 } else if (pa->instr_type & OPC_TEST) {
627 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
628 continue;
629 } else if (pa->instr_type & OPC_B) {
630 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
631 continue;
632 s = opcode - pa->sym;
633 } else if (pa->instr_type & OPC_WLX) {
634 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
635 continue;
636 s = opcode - pa->sym + 1;
637 } else {
638 if (pa->sym != opcode)
639 continue;
640 }
641 if (pa->nb_ops != nb_ops)
642 continue;
643 /* now decode and check each operand */
644 for(i = 0; i < nb_ops; i++) {
645 int op1, op2;
646 op1 = pa->op_type[i];
647 op2 = op1 & 0x1f;
648 switch(op2) {
649 case OPT_IM:
650 v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
651 break;
652 case OPT_REG:
653 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
654 break;
655 case OPT_REGW:
656 v = OP_REG16 | OP_REG32 | OP_REG64;
657 break;
658 case OPT_IMW:
659 v = OP_IM16 | OP_IM32 | OP_IM64;
660 break;
661 #ifdef TCC_TARGET_X86_64
662 case OPT_IMNO64:
663 v = OP_IM16 | OP_IM32;
664 break;
665 #endif
666 default:
667 v = 1 << op2;
668 break;
669 }
670 if (op1 & OPT_EA)
671 v |= OP_EA;
672 op_type[i] = v;
673 if ((ops[i].type & v) == 0)
674 goto next;
675 }
676 /* all is matching ! */
677 break;
678 next: ;
679 }
680 if (pa->sym == 0) {
681 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
682 int b;
683 b = op0_codes[opcode - TOK_ASM_first];
684 #ifdef I386_ASM_16
685 if (opcode == TOK_ASM_o32) {
686 if (s1->seg_size == 32)
687 error("incorrect prefix");
688 else
689 o32 = data32 = 1;
690 } else if (opcode == TOK_ASM_a32) {
691 if (s1->seg_size == 32)
692 error("incorrect prefix");
693 else
694 a32 = addr32 = 1;
695 }
696 #endif
697 if (b & 0xff00)
698 g(b >> 8);
699 g(b);
700 return;
701 } else {
702 error("unknown opcode '%s'",
703 get_tok_str(opcode, NULL));
704 }
705 }
706 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
707 if (s == NBWLX-1) {
708 for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {
709 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
710 s = reg_to_size[ops[i].type & OP_REG];
711 }
712 if (s == NBWLX-1) {
713 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
714 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
715 s = 2;
716 else
717 error("cannot infer opcode suffix");
718 }
719 }
720
721 #ifdef I386_ASM_16
722 for(i = 0; i < nb_ops; i++) {
723 if (ops[i].type & OP_REG32) {
724 if (s1->seg_size == 16)
725 o32 = 1;
726 } else if (!(ops[i].type & OP_REG32)) {
727 if (s1->seg_size == 32)
728 o32 = 1;
729 }
730 }
731
732
733 if (s == 1 || (pa->instr_type & OPC_D16)) {
734 if (s1->seg_size == 32)
735 o32 = 1;
736 } else if (s == 2) {
737 if (s1->seg_size == 16) {
738 if (!(pa->instr_type & OPC_D16))
739 o32 = 1;
740 }
741 }
742
743 /* generate a16/a32 prefix if needed */
744 if ((a32 == 1) && (addr32 == 0))
745 g(0x67);
746 /* generate o16/o32 prefix if needed */
747 if ((o32 == 1) && (data32 == 0))
748 g(0x66);
749
750 addr32 = data32 = 0;
751 #else
752 /* generate data16 prefix if needed */
753 if (s == 1 || (pa->instr_type & OPC_D16))
754 g(0x66);
755 #ifdef TCC_TARGET_X86_64
756 else if (s == 3) {
757 /* generate REX prefix */
758 if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)
759 || !(ops[0].type & OP_REG64))
760 g(0x48);
761 }
762 #endif
763 #endif
764
765 /* now generates the operation */
766 if (pa->instr_type & OPC_FWAIT)
767 g(0x9b);
768 if (seg_prefix)
769 g(seg_prefix);
770
771 v = pa->opcode;
772 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
773 /* kludge for imul $im, %reg */
774 nb_ops = 3;
775 ops[2] = ops[1];
776 op_type[2] = op_type[1];
777 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
778 v--; /* int $3 case */
779 nb_ops = 0;
780 } else if ((v == 0x06 || v == 0x07)) {
781 if (ops[0].reg >= 4) {
782 /* push/pop %fs or %gs */
783 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
784 } else {
785 v += ops[0].reg << 3;
786 }
787 nb_ops = 0;
788 } else if (v <= 0x05) {
789 /* arith case */
790 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
791 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
792 /* fpu arith case */
793 v += ((opcode - pa->sym) / 6) << 3;
794 }
795 if (pa->instr_type & OPC_REG) {
796 for(i = 0; i < nb_ops; i++) {
797 if (op_type[i] & (OP_REG | OP_ST)) {
798 v += ops[i].reg;
799 break;
800 }
801 }
802 /* mov $im, %reg case */
803 if (pa->opcode == 0xb0 && s >= 1)
804 v += 7;
805 }
806 if (pa->instr_type & OPC_B)
807 v += s >= 1;
808 if (pa->instr_type & OPC_TEST)
809 v += test_bits[opcode - pa->sym];
810 if (pa->instr_type & OPC_SHORTJMP) {
811 Sym *sym;
812 int jmp_disp;
813
814 /* see if we can really generate the jump with a byte offset */
815 sym = ops[0].e.sym;
816 if (!sym)
817 goto no_short_jump;
818 if (sym->r != cur_text_section->sh_num)
819 goto no_short_jump;
820 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
821 if (jmp_disp == (int8_t)jmp_disp) {
822 /* OK to generate jump */
823 is_short_jmp = 1;
824 ops[0].e.v = jmp_disp;
825 } else {
826 no_short_jump:
827 if (pa->instr_type & OPC_JMP) {
828 /* long jump will be allowed. need to modify the
829 opcode slightly */
830 if (v == 0xeb)
831 v = 0xe9;
832 else
833 v += 0x0f10;
834 } else {
835 error("invalid displacement");
836 }
837 }
838 }
839 op1 = v >> 8;
840 if (op1)
841 g(op1);
842 g(v);
843
844 /* search which operand will used for modrm */
845 modrm_index = 0;
846 if (pa->instr_type & OPC_SHIFT) {
847 reg = (opcode - pa->sym) / NBWLX;
848 if (reg == 6)
849 reg = 7;
850 } else if (pa->instr_type & OPC_ARITH) {
851 reg = (opcode - pa->sym) / NBWLX;
852 } else if (pa->instr_type & OPC_FARITH) {
853 reg = (opcode - pa->sym) / 6;
854 } else {
855 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
856 }
857 if (pa->instr_type & OPC_MODRM) {
858 /* first look for an ea operand */
859 for(i = 0;i < nb_ops; i++) {
860 if (op_type[i] & OP_EA)
861 goto modrm_found;
862 }
863 /* then if not found, a register or indirection (shift instructions) */
864 for(i = 0;i < nb_ops; i++) {
865 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
866 goto modrm_found;
867 }
868 #ifdef ASM_DEBUG
869 error("bad op table");
870 #endif
871 modrm_found:
872 modrm_index = i;
873 /* if a register is used in another operand then it is
874 used instead of group */
875 for(i = 0;i < nb_ops; i++) {
876 v = op_type[i];
877 if (i != modrm_index &&
878 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
879 reg = ops[i].reg;
880 break;
881 }
882 }
883
884 asm_modrm(reg, &ops[modrm_index]);
885 }
886
887 /* emit constants */
888 #ifndef TCC_TARGET_X86_64
889 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
890 /* ljmp or lcall kludge */
891 #ifdef I386_ASM_16
892 if (s1->seg_size == 16 && o32 == 0)
893 gen_expr16(&ops[1].e);
894 else
895 #endif
896 gen_expr32(&ops[1].e);
897 if (ops[0].e.sym)
898 error("cannot relocate");
899 gen_le16(ops[0].e.v);
900 return;
901 }
902 #endif
903 for(i = 0;i < nb_ops; i++) {
904 v = op_type[i];
905 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
906 /* if multiple sizes are given it means we must look
907 at the op size */
908 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
909 if (s == 0)
910 v = OP_IM8;
911 else if (s == 1)
912 v = OP_IM16;
913 else if (s == 2 || (v & OP_IM64) == 0)
914 v = OP_IM32;
915 else
916 v = OP_IM64;
917 }
918 if (v & (OP_IM8 | OP_IM8S)) {
919 if (ops[i].e.sym)
920 goto error_relocate;
921 g(ops[i].e.v);
922 } else if (v & OP_IM16) {
923 #ifdef I386_ASM_16
924 if (s1->seg_size == 16)
925 gen_expr16(&ops[i].e);
926 else
927 #endif
928 if (ops[i].e.sym)
929 error_relocate:
930 error("cannot relocate");
931 else
932 gen_le16(ops[i].e.v);
933 } else {
934 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
935 if (is_short_jmp)
936 g(ops[i].e.v);
937 #ifdef I386_ASM_16
938 else if (s1->seg_size == 16)
939 gen_disp16(&ops[i].e);
940 #endif
941 else
942 gen_disp32(&ops[i].e);
943 } else {
944 #ifdef I386_ASM_16
945 if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32)))
946 gen_expr16(&ops[i].e);
947 else
948 #endif
949 #ifdef TCC_TARGET_X86_64
950 if (v & OP_IM64)
951 gen_expr64(&ops[i].e);
952 else
953 #endif
954 gen_expr32(&ops[i].e);
955 }
956 }
957 #ifdef I386_ASM_16
958 } else if (v & (OP_REG16 | OP_REG32)) {
959 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
960 /* jmp $r */
961 g(0xE0 + ops[i].reg);
962 }
963 #endif
964 #ifdef TCC_TARGET_X86_64
965 } else if (v & (OP_REG32 | OP_REG64)) {
966 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
967 /* jmp $r */
968 g(0xE0 + ops[i].reg);
969 }
970 #endif
971 }
972 }
973 #ifdef I386_ASM_16
974 a32 = o32 = 0;
975 #endif
976 }
977
978 /* return the constraint priority (we allocate first the lowest
979 numbered constraints) */
980 static inline int constraint_priority(const char *str)
981 {
982 int priority, c, pr;
983
984 /* we take the lowest priority */
985 priority = 0;
986 for(;;) {
987 c = *str;
988 if (c == '\0')
989 break;
990 str++;
991 switch(c) {
992 case 'A':
993 pr = 0;
994 break;
995 case 'a':
996 case 'b':
997 case 'c':
998 case 'd':
999 case 'S':
1000 case 'D':
1001 pr = 1;
1002 break;
1003 case 'q':
1004 pr = 2;
1005 break;
1006 case 'r':
1007 pr = 3;
1008 break;
1009 case 'N':
1010 case 'M':
1011 case 'I':
1012 case 'i':
1013 case 'm':
1014 case 'g':
1015 pr = 4;
1016 break;
1017 default:
1018 error("unknown constraint '%c'", c);
1019 pr = 0;
1020 }
1021 if (pr > priority)
1022 priority = pr;
1023 }
1024 return priority;
1025 }
1026
1027 static const char *skip_constraint_modifiers(const char *p)
1028 {
1029 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1030 p++;
1031 return p;
1032 }
1033
1034 #define REG_OUT_MASK 0x01
1035 #define REG_IN_MASK 0x02
1036
1037 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1038
1039 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1040 int nb_operands, int nb_outputs,
1041 const uint8_t *clobber_regs,
1042 int *pout_reg)
1043 {
1044 ASMOperand *op;
1045 int sorted_op[MAX_ASM_OPERANDS];
1046 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1047 const char *str;
1048 uint8_t regs_allocated[NB_ASM_REGS];
1049
1050 /* init fields */
1051 for(i=0;i<nb_operands;i++) {
1052 op = &operands[i];
1053 op->input_index = -1;
1054 op->ref_index = -1;
1055 op->reg = -1;
1056 op->is_memory = 0;
1057 op->is_rw = 0;
1058 }
1059 /* compute constraint priority and evaluate references to output
1060 constraints if input constraints */
1061 for(i=0;i<nb_operands;i++) {
1062 op = &operands[i];
1063 str = op->constraint;
1064 str = skip_constraint_modifiers(str);
1065 if (isnum(*str) || *str == '[') {
1066 /* this is a reference to another constraint */
1067 k = find_constraint(operands, nb_operands, str, NULL);
1068 if ((unsigned)k >= i || i < nb_outputs)
1069 error("invalid reference in constraint %d ('%s')",
1070 i, str);
1071 op->ref_index = k;
1072 if (operands[k].input_index >= 0)
1073 error("cannot reference twice the same operand");
1074 operands[k].input_index = i;
1075 op->priority = 5;
1076 } else {
1077 op->priority = constraint_priority(str);
1078 }
1079 }
1080
1081 /* sort operands according to their priority */
1082 for(i=0;i<nb_operands;i++)
1083 sorted_op[i] = i;
1084 for(i=0;i<nb_operands - 1;i++) {
1085 for(j=i+1;j<nb_operands;j++) {
1086 p1 = operands[sorted_op[i]].priority;
1087 p2 = operands[sorted_op[j]].priority;
1088 if (p2 < p1) {
1089 tmp = sorted_op[i];
1090 sorted_op[i] = sorted_op[j];
1091 sorted_op[j] = tmp;
1092 }
1093 }
1094 }
1095
1096 for(i = 0;i < NB_ASM_REGS; i++) {
1097 if (clobber_regs[i])
1098 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1099 else
1100 regs_allocated[i] = 0;
1101 }
1102 /* esp cannot be used */
1103 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1104 /* ebp cannot be used yet */
1105 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1106
1107 /* allocate registers and generate corresponding asm moves */
1108 for(i=0;i<nb_operands;i++) {
1109 j = sorted_op[i];
1110 op = &operands[j];
1111 str = op->constraint;
1112 /* no need to allocate references */
1113 if (op->ref_index >= 0)
1114 continue;
1115 /* select if register is used for output, input or both */
1116 if (op->input_index >= 0) {
1117 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1118 } else if (j < nb_outputs) {
1119 reg_mask = REG_OUT_MASK;
1120 } else {
1121 reg_mask = REG_IN_MASK;
1122 }
1123 try_next:
1124 c = *str++;
1125 switch(c) {
1126 case '=':
1127 goto try_next;
1128 case '+':
1129 op->is_rw = 1;
1130 /* FALL THRU */
1131 case '&':
1132 if (j >= nb_outputs)
1133 error("'%c' modifier can only be applied to outputs", c);
1134 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1135 goto try_next;
1136 case 'A':
1137 /* allocate both eax and edx */
1138 if (is_reg_allocated(TREG_XAX) ||
1139 is_reg_allocated(TREG_XDX))
1140 goto try_next;
1141 op->is_llong = 1;
1142 op->reg = TREG_XAX;
1143 regs_allocated[TREG_XAX] |= reg_mask;
1144 regs_allocated[TREG_XDX] |= reg_mask;
1145 break;
1146 case 'a':
1147 reg = TREG_XAX;
1148 goto alloc_reg;
1149 case 'b':
1150 reg = 3;
1151 goto alloc_reg;
1152 case 'c':
1153 reg = TREG_XCX;
1154 goto alloc_reg;
1155 case 'd':
1156 reg = TREG_XDX;
1157 goto alloc_reg;
1158 case 'S':
1159 reg = 6;
1160 goto alloc_reg;
1161 case 'D':
1162 reg = 7;
1163 alloc_reg:
1164 if (is_reg_allocated(reg))
1165 goto try_next;
1166 goto reg_found;
1167 case 'q':
1168 /* eax, ebx, ecx or edx */
1169 for(reg = 0; reg < 4; reg++) {
1170 if (!is_reg_allocated(reg))
1171 goto reg_found;
1172 }
1173 goto try_next;
1174 case 'r':
1175 /* any general register */
1176 for(reg = 0; reg < 8; reg++) {
1177 if (!is_reg_allocated(reg))
1178 goto reg_found;
1179 }
1180 goto try_next;
1181 reg_found:
1182 /* now we can reload in the register */
1183 op->is_llong = 0;
1184 op->reg = reg;
1185 regs_allocated[reg] |= reg_mask;
1186 break;
1187 case 'i':
1188 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1189 goto try_next;
1190 break;
1191 case 'I':
1192 case 'N':
1193 case 'M':
1194 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1195 goto try_next;
1196 break;
1197 case 'm':
1198 case 'g':
1199 /* nothing special to do because the operand is already in
1200 memory, except if the pointer itself is stored in a
1201 memory variable (VT_LLOCAL case) */
1202 /* XXX: fix constant case */
1203 /* if it is a reference to a memory zone, it must lie
1204 in a register, so we reserve the register in the
1205 input registers and a load will be generated
1206 later */
1207 if (j < nb_outputs || c == 'm') {
1208 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1209 /* any general register */
1210 for(reg = 0; reg < 8; reg++) {
1211 if (!(regs_allocated[reg] & REG_IN_MASK))
1212 goto reg_found1;
1213 }
1214 goto try_next;
1215 reg_found1:
1216 /* now we can reload in the register */
1217 regs_allocated[reg] |= REG_IN_MASK;
1218 op->reg = reg;
1219 op->is_memory = 1;
1220 }
1221 }
1222 break;
1223 default:
1224 error("asm constraint %d ('%s') could not be satisfied",
1225 j, op->constraint);
1226 break;
1227 }
1228 /* if a reference is present for that operand, we assign it too */
1229 if (op->input_index >= 0) {
1230 operands[op->input_index].reg = op->reg;
1231 operands[op->input_index].is_llong = op->is_llong;
1232 }
1233 }
1234
1235 /* compute out_reg. It is used to store outputs registers to memory
1236 locations references by pointers (VT_LLOCAL case) */
1237 *pout_reg = -1;
1238 for(i=0;i<nb_operands;i++) {
1239 op = &operands[i];
1240 if (op->reg >= 0 &&
1241 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1242 !op->is_memory) {
1243 for(reg = 0; reg < 8; reg++) {
1244 if (!(regs_allocated[reg] & REG_OUT_MASK))
1245 goto reg_found2;
1246 }
1247 error("could not find free output register for reloading");
1248 reg_found2:
1249 *pout_reg = reg;
1250 break;
1251 }
1252 }
1253
1254 /* print sorted constraints */
1255 #ifdef ASM_DEBUG
1256 for(i=0;i<nb_operands;i++) {
1257 j = sorted_op[i];
1258 op = &operands[j];
1259 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1260 j,
1261 op->id ? get_tok_str(op->id, NULL) : "",
1262 op->constraint,
1263 op->vt->r,
1264 op->reg);
1265 }
1266 if (*pout_reg >= 0)
1267 printf("out_reg=%d\n", *pout_reg);
1268 #endif
1269 }
1270
1271 ST_FUNC void subst_asm_operand(CString *add_str,
1272 SValue *sv, int modifier)
1273 {
1274 int r, reg, size, val;
1275 char buf[64];
1276
1277 r = sv->r;
1278 if ((r & VT_VALMASK) == VT_CONST) {
1279 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1280 cstr_ccat(add_str, '$');
1281 if (r & VT_SYM) {
1282 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1283 if (sv->c.i != 0) {
1284 cstr_ccat(add_str, '+');
1285 } else {
1286 return;
1287 }
1288 }
1289 val = sv->c.i;
1290 if (modifier == 'n')
1291 val = -val;
1292 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1293 cstr_cat(add_str, buf);
1294 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1295 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1296 cstr_cat(add_str, buf);
1297 } else if (r & VT_LVAL) {
1298 reg = r & VT_VALMASK;
1299 if (reg >= VT_CONST)
1300 error("internal compiler error");
1301 snprintf(buf, sizeof(buf), "(%%%s)",
1302 get_tok_str(TOK_ASM_eax + reg, NULL));
1303 cstr_cat(add_str, buf);
1304 } else {
1305 /* register case */
1306 reg = r & VT_VALMASK;
1307 if (reg >= VT_CONST)
1308 error("internal compiler error");
1309
1310 /* choose register operand size */
1311 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1312 size = 1;
1313 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1314 size = 2;
1315 #ifdef TCC_TARGET_X86_64
1316 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1317 size = 8;
1318 #endif
1319 else
1320 size = 4;
1321 if (size == 1 && reg >= 4)
1322 size = 4;
1323
1324 if (modifier == 'b') {
1325 if (reg >= 4)
1326 error("cannot use byte register");
1327 size = 1;
1328 } else if (modifier == 'h') {
1329 if (reg >= 4)
1330 error("cannot use byte register");
1331 size = -1;
1332 } else if (modifier == 'w') {
1333 size = 2;
1334 #ifdef TCC_TARGET_X86_64
1335 } else if (modifier == 'q') {
1336 size = 8;
1337 #endif
1338 }
1339
1340 switch(size) {
1341 case -1:
1342 reg = TOK_ASM_ah + reg;
1343 break;
1344 case 1:
1345 reg = TOK_ASM_al + reg;
1346 break;
1347 case 2:
1348 reg = TOK_ASM_ax + reg;
1349 break;
1350 default:
1351 reg = TOK_ASM_eax + reg;
1352 break;
1353 #ifdef TCC_TARGET_X86_64
1354 case 8:
1355 reg = TOK_ASM_rax + reg;
1356 break;
1357 #endif
1358 }
1359 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1360 cstr_cat(add_str, buf);
1361 }
1362 }
1363
1364 /* generate prolog and epilog code for asm statment */
1365 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1366 int nb_outputs, int is_output,
1367 uint8_t *clobber_regs,
1368 int out_reg)
1369 {
1370 uint8_t regs_allocated[NB_ASM_REGS];
1371 ASMOperand *op;
1372 int i, reg;
1373 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1374
1375 /* mark all used registers */
1376 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1377 for(i = 0; i < nb_operands;i++) {
1378 op = &operands[i];
1379 if (op->reg >= 0)
1380 regs_allocated[op->reg] = 1;
1381 }
1382 if (!is_output) {
1383 /* generate reg save code */
1384 for(i = 0; i < NB_SAVED_REGS; i++) {
1385 reg = reg_saved[i];
1386 if (regs_allocated[reg]) {
1387 #ifdef I386_ASM_16
1388 if (tcc_state->seg_size == 16)
1389 g(0x66);
1390 #endif
1391 g(0x50 + reg);
1392 }
1393 }
1394
1395 /* generate load code */
1396 for(i = 0; i < nb_operands; i++) {
1397 op = &operands[i];
1398 if (op->reg >= 0) {
1399 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1400 op->is_memory) {
1401 /* memory reference case (for both input and
1402 output cases) */
1403 SValue sv;
1404 sv = *op->vt;
1405 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1406 load(op->reg, &sv);
1407 } else if (i >= nb_outputs || op->is_rw) {
1408 /* load value in register */
1409 load(op->reg, op->vt);
1410 if (op->is_llong) {
1411 SValue sv;
1412 sv = *op->vt;
1413 sv.c.ul += 4;
1414 load(TREG_XDX, &sv);
1415 }
1416 }
1417 }
1418 }
1419 } else {
1420 /* generate save code */
1421 for(i = 0 ; i < nb_outputs; i++) {
1422 op = &operands[i];
1423 if (op->reg >= 0) {
1424 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1425 if (!op->is_memory) {
1426 SValue sv;
1427 sv = *op->vt;
1428 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1429 load(out_reg, &sv);
1430
1431 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1432 store(op->reg, &sv);
1433 }
1434 } else {
1435 store(op->reg, op->vt);
1436 if (op->is_llong) {
1437 SValue sv;
1438 sv = *op->vt;
1439 sv.c.ul += 4;
1440 store(TREG_XDX, &sv);
1441 }
1442 }
1443 }
1444 }
1445 /* generate reg restore code */
1446 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1447 reg = reg_saved[i];
1448 if (regs_allocated[reg]) {
1449 #ifdef I386_ASM_16
1450 if (tcc_state->seg_size == 16)
1451 g(0x66);
1452 #endif
1453 g(0x58 + reg);
1454 }
1455 }
1456 }
1457 }
1458
1459 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1460 {
1461 int reg;
1462 TokenSym *ts;
1463
1464 if (!strcmp(str, "memory") ||
1465 !strcmp(str, "cc"))
1466 return;
1467 ts = tok_alloc(str, strlen(str));
1468 reg = ts->tok;
1469 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1470 reg -= TOK_ASM_eax;
1471 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1472 reg -= TOK_ASM_ax;
1473 #ifdef TCC_TARGET_X86_64
1474 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1475 reg -= TOK_ASM_rax;
1476 #endif
1477 } else {
1478 error("invalid clobber register '%s'", str);
1479 }
1480 clobber_regs[reg] = 1;
1481 }
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