1 #ifdef TARGET_DEFS_ONLY
3 // Number of registers available to allocator:
4 #define NB_REGS 19 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7, xxx, ra, sp
6 #define TREG_R(x) (x) // x = 0..7
7 #define TREG_F(x) (x + 8) // x = 0..7
9 // Register classes sorted from more general to more precise:
10 #define RC_INT (1 << 0)
11 #define RC_FLOAT (1 << 1)
12 #define RC_R(x) (1 << (2 + (x))) // x = 0..7
13 #define RC_F(x) (1 << (10 + (x))) // x = 0..7
15 #define RC_IRET (RC_R(0)) // int return register class
16 #define RC_FRET (RC_F(0)) // float return register class
18 #define REG_IRET (TREG_R(0)) // int return register number
19 #define REG_FRET (TREG_F(0)) // float return register number
23 #define LDOUBLE_SIZE 16
24 #define LDOUBLE_ALIGN 16
28 #define CHAR_IS_UNSIGNED
39 ST_DATA
const int reg_classes
[NB_REGS
] = {
61 static int ireg(int r
)
67 assert(r
>= 0 && r
< 8);
68 return r
+ 10; // tccrX --> aX == x(10+X)
71 static int is_ireg(int r
)
73 return (unsigned)r
< 8 || r
== TREG_RA
|| r
== TREG_SP
;
76 static int freg(int r
)
78 assert(r
>= 8 && r
< 16);
79 return r
- 8 + 10; // tccfX --> faX == f(10+X)
82 static int is_freg(int r
)
84 return r
>= 8 && r
< 16;
87 ST_FUNC
void o(unsigned int c
)
92 if (ind1
> cur_text_section
->data_allocated
)
93 section_realloc(cur_text_section
, ind1
);
94 write32le(cur_text_section
->data
+ ind
, c
);
98 static void EIu(uint32_t opcode
, uint32_t func3
,
99 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
101 o(opcode
| (func3
<< 12) | (rd
<< 7) | (rs1
<< 15) | (imm
<< 20));
104 static void EI(uint32_t opcode
, uint32_t func3
,
105 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
107 assert(! ((imm
+ (1 << 11)) >> 12));
108 EIu(opcode
, func3
, rd
, rs1
, imm
);
111 static void ES(uint32_t opcode
, uint32_t func3
,
112 uint32_t rs1
, uint32_t rs2
, uint32_t imm
)
114 assert(! ((imm
+ (1 << 11)) >> 12));
115 o(opcode
| (func3
<< 12) | ((imm
& 0x1f) << 7) | (rs1
<< 15)
116 | (rs2
<< 20) | ((imm
>> 5) << 25));
119 // Patch all branches in list pointed to by t to branch to a:
120 ST_FUNC
void gsym_addr(int t_
, int a_
)
125 unsigned char *ptr
= cur_text_section
->data
+ t
;
126 uint32_t next
= read32le(ptr
);
127 uint32_t r
= a
- t
, imm
;
128 if ((r
+ (1 << 21)) & ~((1U << 22) - 2))
129 tcc_error("out-of-range branch chain");
130 imm
= (((r
>> 12) & 0xff) << 12)
131 | (((r
>> 11) & 1) << 20)
132 | (((r
>> 1) & 0x3ff) << 21)
133 | (((r
>> 20) & 1) << 31);
134 write32le(ptr
, r
== 4 ? 0x33 : 0x6f | imm
); // nop || j imm
139 static int load_symofs(int r
, SValue
*sv
, int forstore
)
143 int fc
= sv
->c
.i
, v
= sv
->r
& VT_VALMASK
;
144 if (sv
->r
& VT_SYM
) {
145 assert(v
== VT_CONST
);
146 if (sv
->sym
->type
.t
& VT_STATIC
) { // XXX do this per linker relax
147 greloca(cur_text_section
, sv
->sym
, ind
,
148 R_RISCV_PCREL_HI20
, sv
->c
.i
);
151 if (((unsigned)fc
+ (1 << 11)) >> 12)
152 tcc_error("unimp: large addend for global address (0x%llx)", sv
->c
.i
);
153 greloca(cur_text_section
, sv
->sym
, ind
,
154 R_RISCV_GOT_HI20
, 0);
158 label
.v
= tok_alloc(".L0 ", 4)->tok
;
159 label
.type
.t
= VT_VOID
| VT_STATIC
;
161 label
.c
= 0; /* force new local ELF symbol */
162 put_extern_sym(&label
, cur_text_section
, ind
, 0);
163 rr
= is_ireg(r
) ? ireg(r
) : 5;
164 o(0x17 | (rr
<< 7)); // auipc RR, 0 %pcrel_hi(sym)+addend
165 greloca(cur_text_section
, &label
, ind
,
167 ? R_RISCV_PCREL_LO12_I
: R_RISCV_PCREL_LO12_S
, 0);
169 EI(0x03, 3, rr
, rr
, 0); // ld RR, 0(RR)
171 } else if (v
== VT_LOCAL
|| v
== VT_LLOCAL
) {
174 tcc_error("unimp: store(giant local off) (0x%llx)", (long long)sv
->c
.i
);
175 if (((unsigned)fc
+ (1 << 11)) >> 12) {
176 rr
= is_ireg(r
) ? ireg(r
) : 5; // t0
177 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui RR, upper(fc)
178 o(0x33 | (rr
<< 7) | (rr
<< 15) | (8 << 20)); // add RR, RR, s0
179 sv
->c
.i
= fc
<< 20 >> 20;
186 ST_FUNC
void load(int r
, SValue
*sv
)
189 int v
= fr
& VT_VALMASK
;
190 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
192 int bt
= sv
->type
.t
& VT_BTYPE
;
193 int align
, size
= type_size(&sv
->type
, &align
);
195 int func3
, opcode
= is_freg(r
) ? 0x07 : 0x03, br
;
196 assert (!is_freg(r
) || bt
== VT_FLOAT
|| bt
== VT_DOUBLE
);
197 if (bt
== VT_FUNC
) /* XXX should be done in generic code */
199 func3
= size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3;
200 if (size
< 4 && !is_float(sv
->type
.t
) && (sv
->type
.t
& VT_UNSIGNED
))
202 if (v
== VT_LOCAL
|| (fr
& VT_SYM
)) {
203 br
= load_symofs(r
, sv
, 0);
205 } else if (v
< VT_CONST
) {
207 /*if (((unsigned)fc + (1 << 11)) >> 12)
208 tcc_error("unimp: load(large addend) (0x%x)", fc);*/
209 fc
= 0; // XXX store ofs in LVAL(reg)
210 } else if (v
== VT_LLOCAL
) {
211 br
= load_symofs(r
, sv
, 0);
213 EI(0x03, 3, rr
, br
, fc
); // ld RR, fc(BR)
217 tcc_error("unimp: load(non-local lval)");
219 EI(opcode
, func3
, rr
, br
, fc
); // l[bhwd][u] / fl[wd] RR, fc(BR)
220 } else if (v
== VT_CONST
) {
221 int rb
= 0, do32bit
= 8, zext
= 0;
222 assert((!is_float(sv
->type
.t
) && is_ireg(r
)) || bt
== VT_LDOUBLE
);
224 rb
= load_symofs(r
, sv
, 0);
228 if (is_float(sv
->type
.t
) && bt
!= VT_LDOUBLE
)
229 tcc_error("unimp: load(float)");
231 int64_t si
= sv
->c
.i
;
238 o(0x37 | (rr
<< 7) | (((pi
+ 0x800) & 0xfffff000))); // lui RR, up(up(fc))
239 EI(0x13, 0, rr
, rr
, (int)pi
<< 20 >> 20); // addi RR, RR, lo(up(fc))
240 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
241 EI(0x13, 0, rr
, rr
, (fc
+ (1 << 19)) >> 20); // addi RR, RR, up(lo(fc))
242 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
244 EI(0x13, 0, rr
, rr
, fc
>> 8); // addi RR, RR, lo1(lo(fc))
245 EI(0x13, 1, rr
, rr
, 8); // slli RR, RR, 8
249 } else if (bt
== VT_LLONG
) {
250 /* A 32bit unsigned constant for a 64bit type.
251 lui always sign extends, so we need to do an explicit zext.*/
255 if (((unsigned)fc
+ (1 << 11)) >> 12)
256 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)), rb
= rr
; //lui RR, upper(fc)
257 if (fc
|| (rr
!= rb
) || do32bit
|| (fr
& VT_SYM
))
258 EI(0x13 | do32bit
, 0, rr
, rb
, fc
<< 20 >> 20); // addi[w] R, x0|R, FC
260 EI(0x13, 1, rr
, rr
, 32); // slli RR, RR, 32
261 EI(0x13, 5, rr
, rr
, 32); // srli RR, RR, 32
263 } else if (v
== VT_LOCAL
) {
264 int br
= load_symofs(r
, sv
, 0);
267 EI(0x13, 0, rr
, br
, fc
); // addi R, s0, FC
268 } else if (v
< VT_CONST
) { /* reg-reg */
269 //assert(!fc); XXX support offseted regs
270 if (is_freg(r
) && is_freg(v
))
271 o(0x53 | (rr
<< 7) | (freg(v
) << 15) | (freg(v
) << 20) | ((bt
== VT_DOUBLE
? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
272 else if (is_ireg(r
) && is_ireg(v
))
273 EI(0x13, 0, rr
, ireg(v
), 0); // addi RR, V, 0 == mv RR, V
275 int func7
= is_ireg(r
) ? 0x70 : 0x78;
278 assert(size
== 4 || size
== 8);
279 o(0x53 | (rr
<< 7) | ((is_freg(v
) ? freg(v
) : ireg(v
)) << 15)
280 | (func7
<< 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
282 } else if (v
== VT_CMP
) { // we rely on cmp_r to be the correct result
283 EI(0x13, 0, rr
, vtop
->cmp_r
, 0); // mv RR, CMP_R
284 } else if ((v
& ~1) == VT_JMP
) {
287 EI(0x13, 0, rr
, 0, t
); // addi RR, x0, t
290 EI(0x13, 0, rr
, 0, t
^ 1); // addi RR, x0, !t
292 tcc_error("unimp: load(non-const)");
295 ST_FUNC
void store(int r
, SValue
*sv
)
297 int fr
= sv
->r
& VT_VALMASK
;
298 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
), ptrreg
;
300 int bt
= sv
->type
.t
& VT_BTYPE
;
301 int align
, size
= type_size(&sv
->type
, &align
);
302 assert(!is_float(bt
) || is_freg(r
) || bt
== VT_LDOUBLE
);
303 /* long doubles are in two integer registers, but the load/store
304 primitives only deal with one, so do as if it's one reg. */
305 if (bt
== VT_LDOUBLE
)
308 tcc_error("unimp: store(struct)");
310 tcc_error("unimp: large sized store");
311 assert(sv
->r
& VT_LVAL
);
312 if (fr
== VT_LOCAL
|| (sv
->r
& VT_SYM
)) {
313 ptrreg
= load_symofs(-1, sv
, 1);
315 } else if (fr
< VT_CONST
) {
317 /*if (((unsigned)fc + (1 << 11)) >> 12)
318 tcc_error("unimp: store(large addend) (0x%x)", fc);*/
319 fc
= 0; // XXX support offsets regs
321 tcc_error("implement me: %s(!local)", __FUNCTION__
);
322 ES(is_freg(r
) ? 0x27 : 0x23, // fs... | s...
323 size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3, // ... [wd] | [bhwd]
324 ptrreg
, rr
, fc
); // RR, fc(base)
327 static void gcall_or_jmp(int docall
)
329 int tr
= docall
? 1 : 5; // ra or t0
330 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&&
331 ((vtop
->r
& VT_SYM
) && vtop
->c
.i
== (int)vtop
->c
.i
)) {
332 /* constant symbolic case -> simple relocation */
333 greloca(cur_text_section
, vtop
->sym
, ind
,
334 R_RISCV_CALL_PLT
, (int)vtop
->c
.i
);
335 o(0x17 | (tr
<< 7)); // auipc TR, 0 %call(func)
336 EI(0x67, 0, tr
, tr
, 0);// jalr TR, r(TR)
337 } else if (vtop
->r
< VT_CONST
) {
338 int r
= ireg(vtop
->r
);
339 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
344 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
348 static void reg_pass_rec(CType
*type
, int *rc
, int *fieldofs
, int ofs
)
350 if ((type
->t
& VT_BTYPE
) == VT_STRUCT
) {
352 if (type
->ref
->type
.t
== VT_UNION
)
354 else for (f
= type
->ref
->next
; f
; f
= f
->next
)
355 reg_pass_rec(&f
->type
, rc
, fieldofs
, ofs
+ f
->c
);
356 } else if (type
->t
& VT_ARRAY
) {
357 if (type
->ref
->c
< 0 || type
->ref
->c
> 2)
360 int a
, sz
= type_size(&type
->ref
->type
, &a
);
361 reg_pass_rec(&type
->ref
->type
, rc
, fieldofs
, ofs
);
362 if (rc
[0] > 2 || (rc
[0] == 2 && type
->ref
->c
> 1))
364 else if (type
->ref
->c
== 2 && rc
[0] && rc
[1] == RC_FLOAT
) {
365 rc
[++rc
[0]] = RC_FLOAT
;
366 fieldofs
[rc
[0]] = ((ofs
+ sz
) << 4)
367 | (type
->ref
->type
.t
& VT_BTYPE
);
368 } else if (type
->ref
->c
== 2)
371 } else if (rc
[0] == 2 || rc
[0] < 0 || (type
->t
& VT_BTYPE
) == VT_LDOUBLE
)
373 else if (!rc
[0] || rc
[1] == RC_FLOAT
|| is_float(type
->t
)) {
374 rc
[++rc
[0]] = is_float(type
->t
) ? RC_FLOAT
: RC_INT
;
375 fieldofs
[rc
[0]] = (ofs
<< 4) | (type
->t
& VT_BTYPE
);
380 static void reg_pass(CType
*type
, int *prc
, int *fieldofs
, int named
)
383 reg_pass_rec(type
, prc
, fieldofs
, 0);
384 if (prc
[0] <= 0 || !named
) {
385 int align
, size
= type_size(type
, &align
);
386 prc
[0] = (size
+ 7) >> 3;
387 prc
[1] = prc
[2] = RC_INT
;
388 fieldofs
[1] = (0 << 4) | (size
<= 1 ? VT_BYTE
: size
<= 2 ? VT_SHORT
: size
<= 4 ? VT_INT
: VT_LLONG
);
389 fieldofs
[2] = (8 << 4) | (size
<= 9 ? VT_BYTE
: size
<= 10 ? VT_SHORT
: size
<= 12 ? VT_INT
: VT_LLONG
);
393 ST_FUNC
void gfunc_call(int nb_args
)
395 int i
, align
, size
, areg
[2];
396 int info
[nb_args
? nb_args
: 1];
397 int stack_adj
= 0, tempspace
= 0, ofs
, splitofs
= 0;
400 areg
[0] = 0; /* int arg regs */
401 areg
[1] = 8; /* float arg regs */
402 sa
= vtop
[-nb_args
].type
.ref
->next
;
403 for (i
= 0; i
< nb_args
; i
++) {
404 int nregs
, byref
= 0, tempofs
;
405 int prc
[3], fieldofs
[3];
406 sv
= &vtop
[1 + i
- nb_args
];
407 sv
->type
.t
&= ~VT_ARRAY
; // XXX this should be done in tccgen.c
408 size
= type_size(&sv
->type
, &align
);
412 tempspace
= (tempspace
+ align
- 1) & -align
;
416 byref
= 64 | (tempofs
<< 7);
418 reg_pass(&sv
->type
, prc
, fieldofs
, sa
!= 0);
419 if (!sa
&& align
== 2*XLEN
&& size
<= 2*XLEN
)
420 areg
[0] = (areg
[0] + 1) & ~1;
422 if ((prc
[1] == RC_INT
&& areg
[0] >= 8)
423 || (prc
[1] == RC_FLOAT
&& areg
[1] >= 16)
424 || (nregs
== 2 && prc
[1] == RC_FLOAT
&& prc
[2] == RC_FLOAT
426 || (nregs
== 2 && prc
[1] != prc
[2]
427 && (areg
[1] >= 16 || areg
[0] >= 8))) {
431 stack_adj
+= (size
+ align
- 1) & -align
;
432 if (!sa
) /* one vararg on stack forces the rest on stack */
433 areg
[0] = 8, areg
[1] = 16;
435 info
[i
] = areg
[prc
[1] - 1]++;
437 info
[i
] |= (fieldofs
[1] & VT_BTYPE
) << 12;
438 assert(!(fieldofs
[1] >> 4));
440 if (prc
[2] == RC_FLOAT
|| areg
[0] < 8)
441 info
[i
] |= (1 + areg
[prc
[2] - 1]++) << 7;
447 assert((fieldofs
[2] >> 4) < 2048);
448 info
[i
] |= fieldofs
[2] << (12 + 4); // includes offset
456 stack_adj
= (stack_adj
+ 15) & -16;
457 tempspace
= (tempspace
+ 15) & -16;
458 if (stack_adj
+ tempspace
) {
459 EI(0x13, 0, 2, 2, -(stack_adj
+ tempspace
)); // addi sp, sp, -adj
460 for (i
= ofs
= 0; i
< nb_args
; i
++) {
461 if (info
[i
] & (64 | 32)) {
463 size
= type_size(&vtop
->type
, &align
);
465 vset(&char_pointer_type
, TREG_SP
, 0);
466 vpushi(stack_adj
+ (info
[i
] >> 7));
468 vpushv(vtop
); // this replaces the old argument
471 vtop
->type
= vtop
[-1].type
;
480 /* Once we support offseted regs we can do this:
481 vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
482 to construct the lvalue for the outgoing stack slot,
483 until then we have to jump through hoops. */
484 vset(&char_pointer_type
, TREG_SP
, 0);
485 ofs
= (ofs
+ align
- 1) & -align
;
489 vtop
->type
= vtop
[-1].type
;
492 vtop
->r
= vtop
->r2
= VT_CONST
; // this arg is done
496 } else if (info
[i
] & 16) {
503 for (i
= 0; i
< nb_args
; i
++) {
504 int ii
= info
[nb_args
- 1 - i
], r
= ii
, r2
= r
;
509 r2
= r2
& 64 ? 0 : (r2
>> 7) & 31;
512 origtype
= vtop
->type
;
513 size
= type_size(&vtop
->type
, &align
);
514 loadt
= vtop
->type
.t
& VT_BTYPE
;
515 if (loadt
== VT_STRUCT
) {
516 loadt
= (ii
>> 12) & VT_BTYPE
;
518 if (info
[nb_args
- 1 - i
] & 16) {
522 if (loadt
== VT_LDOUBLE
) {
529 vtop
->type
.t
= loadt
;
530 gv(r
< 8 ? RC_R(r
) : RC_F(r
- 8));
531 vtop
->type
= origtype
;
533 if (r2
&& loadt
!= VT_LDOUBLE
) {
535 assert(r2
< 16 || r2
== TREG_RA
);
538 vtop
->type
= char_pointer_type
;
542 vtop
->type
= origtype
;
543 loadt
= vtop
->type
.t
& VT_BTYPE
;
544 if (loadt
== VT_STRUCT
) {
545 loadt
= (ii
>> 16) & VT_BTYPE
;
547 save_reg_upstack(r2
, 1);
548 vtop
->type
.t
= loadt
;
550 assert(r2
< VT_CONST
);
554 if (info
[nb_args
- 1 - i
] & 16) {
555 ES(0x23, 3, 2, ireg(vtop
->r2
), splitofs
); // sd t0, ofs(sp)
557 } else if (loadt
== VT_LDOUBLE
&& vtop
->r2
!= r2
) {
558 assert(vtop
->r2
<= 7 && r2
<= 7);
559 /* XXX we'd like to have 'gv' move directly into
560 the right class instead of us fixing it up. */
561 EI(0x13, 0, ireg(r2
), ireg(vtop
->r2
), 0); // mv Ra+1, RR2
568 save_regs(nb_args
+ 1);
571 if (stack_adj
+ tempspace
)
572 EI(0x13, 0, 2, 2, stack_adj
+ tempspace
); // addi sp, sp, adj
575 static int func_sub_sp_offset
, num_va_regs
, func_va_list_ofs
;
577 ST_FUNC
void gfunc_prolog(CType
*func_type
)
579 int i
, addr
, align
, size
;
585 sym
= func_type
->ref
;
587 loc
= -16; // for ra and s0
588 func_sub_sp_offset
= ind
;
591 areg
[0] = 0, areg
[1] = 0;
593 /* if the function returns by reference, then add an
594 implicit pointer parameter */
595 size
= type_size(&func_vt
, &align
);
596 if (size
> 2 * XLEN
) {
599 ES(0x23, 3, 8, 10 + areg
[0]++, loc
); // sd a0, loc(s0)
601 /* define parameters */
602 while ((sym
= sym
->next
) != NULL
) {
605 int prc
[3], fieldofs
[3];
607 size
= type_size(type
, &align
);
608 if (size
> 2 * XLEN
) {
609 type
= &char_pointer_type
;
610 size
= align
= byref
= 8;
612 reg_pass(type
, prc
, fieldofs
, 1);
614 if (areg
[prc
[1] - 1] >= 8
616 && ((prc
[1] == RC_FLOAT
&& prc
[2] == RC_FLOAT
&& areg
[1] >= 7)
617 || (prc
[1] != prc
[2] && (areg
[1] >= 8 || areg
[0] >= 8))))) {
620 addr
= (addr
+ align
- 1) & -align
;
624 loc
-= regcount
* 8; // XXX could reserve only 'size' bytes
626 for (i
= 0; i
< regcount
; i
++) {
627 if (areg
[prc
[1+i
] - 1] >= 8) {
628 assert(i
== 1 && regcount
== 2 && !(addr
& 7));
629 EI(0x03, 3, 5, 8, addr
); // ld t0, addr(s0)
631 ES(0x23, 3, 8, 5, loc
+ i
*8); // sd t0, loc(s0)
632 } else if (prc
[1+i
] == RC_FLOAT
) {
633 ES(0x27, (size
/ regcount
) == 4 ? 2 : 3, 8, 10 + areg
[1]++, loc
+ (fieldofs
[i
+1] >> 4)); // fs[wd] FAi, loc(s0)
635 ES(0x23, 3, 8, 10 + areg
[0]++, loc
+ i
*8); // sd aX, loc(s0) // XXX
639 sym_push(sym
->v
& ~SYM_FIELD
, &sym
->type
,
640 (byref
? VT_LLOCAL
: VT_LOCAL
) | lvalue_type(sym
->type
.t
),
643 func_va_list_ofs
= addr
;
645 if (func_type
->ref
->f
.func_type
== FUNC_ELLIPSIS
) {
646 for (; areg
[0] < 8; areg
[0]++) {
648 ES(0x23, 3, 8, 10 + areg
[0], -8 + num_va_regs
* 8); // sd aX, loc(s0)
653 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
654 int *ret_align
, int *regsize
)
656 int align
, size
= type_size(vt
, &align
), nregs
;
657 int prc
[3], fieldofs
[3];
662 reg_pass(vt
, prc
, fieldofs
, 1);
664 if (nregs
== 2 && prc
[1] != prc
[2])
665 return -1; /* generic code can't deal with this case */
666 if (prc
[1] == RC_FLOAT
) {
667 *regsize
= size
/ nregs
;
669 ret
->t
= fieldofs
[1] & VT_BTYPE
;
673 ST_FUNC
void arch_transfer_ret_regs(int aftercall
)
675 int prc
[3], fieldofs
[3];
676 reg_pass(&vtop
->type
, prc
, fieldofs
, 1);
677 assert(prc
[0] == 2 && prc
[1] != prc
[2] && !(fieldofs
[1] >> 4));
678 assert(vtop
->r
== (VT_LOCAL
| VT_LVAL
));
680 vtop
->type
.t
= fieldofs
[1] & VT_BTYPE
;
681 (aftercall
? store
: load
)(prc
[1] == RC_INT
? REG_IRET
: REG_FRET
, vtop
);
682 vtop
->c
.i
+= fieldofs
[2] >> 4;
683 vtop
->type
.t
= fieldofs
[2] & VT_BTYPE
;
684 (aftercall
? store
: load
)(prc
[2] == RC_INT
? REG_IRET
: REG_FRET
, vtop
);
688 ST_FUNC
void gfunc_epilog(void)
690 int v
, saved_ind
, d
, large_ofs_ind
;
692 loc
= (loc
- num_va_regs
* 8);
693 d
= v
= (-loc
+ 15) & -16;
695 if (v
>= (1 << 11)) {
697 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
698 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
699 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20)); //add sp, sp, t0
701 EI(0x03, 3, 1, 2, d
- 8 - num_va_regs
* 8); // ld ra, v-8(sp)
702 EI(0x03, 3, 8, 2, d
- 16 - num_va_regs
* 8); // ld s0, v-16(sp)
703 EI(0x13, 0, 2, 2, d
); // addi sp, sp, v
704 EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
705 if (v
>= (1 << 11)) {
707 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
708 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
709 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
710 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20) | (0x20 << 25)); //sub sp, sp, t0
711 gjmp_addr(func_sub_sp_offset
+ 5*4);
715 ind
= func_sub_sp_offset
;
716 EI(0x13, 0, 2, 2, -d
); // addi sp, sp, -d
717 ES(0x23, 3, 2, 1, d
- 8 - num_va_regs
* 8); // sd ra, d-8(sp)
718 ES(0x23, 3, 2, 8, d
- 16 - num_va_regs
* 8); // sd s0, d-16(sp)
720 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
722 gjmp_addr(large_ofs_ind
);
723 if ((ind
- func_sub_sp_offset
) != 5*4)
724 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
728 ST_FUNC
void gen_va_start(void)
731 vset(&char_pointer_type
, VT_LOCAL
, func_va_list_ofs
);
734 ST_FUNC
void gen_fill_nops(int bytes
)
737 tcc_error("alignment of code section not multiple of 4");
739 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
744 // Generate forward branch to label:
745 ST_FUNC
int gjmp(int t
)
753 // Generate branch to known address:
754 ST_FUNC
void gjmp_addr(int a
)
756 uint32_t r
= a
- ind
, imm
;
757 if ((r
+ (1 << 21)) & ~((1U << 22) - 2)) {
758 o(0x17 | (5 << 7) | (((r
+ 0x800) & 0xfffff000))); // lui RR, up(r)
759 r
= (int)r
<< 20 >> 20;
760 EI(0x67, 0, 0, 5, r
); // jalr x0, r(t0)
762 imm
= (((r
>> 12) & 0xff) << 12)
763 | (((r
>> 11) & 1) << 20)
764 | (((r
>> 1) & 0x3ff) << 21)
765 | (((r
>> 20) & 1) << 31);
766 o(0x6f | imm
); // jal x0, imm == j imm
770 ST_FUNC
int gjmp_cond(int op
, int t
)
773 assert(op
== TOK_EQ
|| op
== TOK_NE
);
774 assert(vtop
->cmp_r
>= 10 && vtop
->cmp_r
< 18);
775 o(0x63 | (!inv
<< 12) | (vtop
->cmp_r
<< 15) | (8 << 7)); // bne/beq x0,r,+4
779 ST_FUNC
int gjmp_append(int n
, int t
)
782 /* insert jump list n into t */
785 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
793 static void gen_opil(int op
, int ll
)
797 int func3
= 0, func7
= 0;
798 /* XXX We could special-case some constant args. */
800 a
= ireg(vtop
[-1].r
);
810 tcc_error("implement me: %s(%s)", __FUNCTION__
, get_tok_str(op
, NULL
));
813 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20)); // add d, a, b
816 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x20 << 25)); //sub d, a, b
819 o(0x33 | ll
| (d
<< 7) | (a
<< 15) | (b
<< 20) | (5 << 12) | (1 << 30)); //sra d, a, b
822 o(0x33 | ll
| (d
<< 7) | (a
<< 15) | (b
<< 20) | (5 << 12)); //srl d, a, b
825 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (1 << 12)); //sll d, a, b
828 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25)); //mul d, a, b
831 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (4 << 12)); //div d, a, b
834 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (7 << 12)); // and d, a, b
837 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (4 << 12)); // xor d, a, b
840 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (6 << 12)); // or d, a, b
843 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (6 << 12)); //rem d, a, b
846 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (7 << 12)); //remu d, a, b
850 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (5 << 12)); //divu d, a, b
861 if (op
& 1) { // remove [U]GE,GT
865 if ((op
& 7) == 6) { // [U]LE
866 int t
= a
; a
= b
; b
= t
;
869 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (((op
> TOK_UGT
) ? 2 : 3) << 12)); // slt[u] d, a, b
871 EI(0x13, 4, d
, d
, 1); // xori d, d, 1
877 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x20 << 25)); // sub d, a, b
879 o(0x33 | (3 << 12) | (d
<< 7) | (0 << 15) | (d
<< 20)); // sltu d, x0, d == snez d,d
881 EI(0x13, 3, d
, d
, 1); // sltiu d, d, 1 == seqz d,d
888 ST_FUNC
void gen_opi(int op
)
893 ST_FUNC
void gen_opl(int op
)
898 ST_FUNC
void gen_opf(int op
)
900 int rs1
, rs2
, rd
, dbl
, invert
;
901 if (vtop
[0].type
.t
== VT_LDOUBLE
) {
902 CType type
= vtop
[0].type
;
906 case '*': func
= TOK___multf3
; break;
907 case '+': func
= TOK___addtf3
; break;
908 case '-': func
= TOK___subtf3
; break;
909 case '/': func
= TOK___divtf3
; break;
910 case TOK_EQ
: func
= TOK___eqtf2
; cond
= 1; break;
911 case TOK_NE
: func
= TOK___netf2
; cond
= 0; break;
912 case TOK_LT
: func
= TOK___lttf2
; cond
= 10; break;
913 case TOK_GE
: func
= TOK___getf2
; cond
= 11; break;
914 case TOK_LE
: func
= TOK___letf2
; cond
= 12; break;
915 case TOK_GT
: func
= TOK___gttf2
; cond
= 13; break;
916 default: assert(0); break;
918 vpush_global_sym(&func_old_type
, func
);
923 vtop
->r2
= cond
< 0 ? TREG_R(1) : VT_CONST
;
933 gv2(RC_FLOAT
, RC_FLOAT
);
934 assert(vtop
->type
.t
== VT_DOUBLE
|| vtop
->type
.t
== VT_FLOAT
);
935 dbl
= vtop
->type
.t
== VT_DOUBLE
;
936 rs1
= freg(vtop
[-1].r
);
946 rd
= get_reg(RC_FLOAT
);
949 o(0x53 | (rd
<< 7) | (rs1
<< 15) | (rs2
<< 20) | (7 << 12) | (dbl
<< 25) | (op
<< 27)); // fop.[sd] RD, RS1, RS2 (dyn rm)
963 rd
= get_reg(RC_INT
);
966 o(0x53 | (rd
<< 7) | (rs1
<< 15) | (rs2
<< 20) | (op
<< 12) | (dbl
<< 25) | (0x14 << 27)); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
968 EI(0x13, 4, rd
, rd
, 1); // xori RD, 1
982 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
986 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
991 ST_FUNC
void gen_cvt_sxtw(void)
993 /* XXX on risc-v the registers are usually sign-extended already.
994 Let's try to not do anything here. */
997 ST_FUNC
void gen_cvt_itof(int t
)
999 int rr
= ireg(gv(RC_INT
)), dr
;
1000 int u
= vtop
->type
.t
& VT_UNSIGNED
;
1001 int l
= (vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
;
1002 if (t
== VT_LDOUBLE
) {
1004 (u
? TOK___floatunditf
: TOK___floatditf
) :
1005 (u
? TOK___floatunsitf
: TOK___floatsitf
);
1006 vpush_global_sym(&func_old_type
, func
);
1012 vtop
->r2
= TREG_R(1);
1015 dr
= get_reg(RC_FLOAT
);
1019 EIu(0x53, 7, dr
, rr
, ((0x68 | (t
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[sd].[wl][u]
1023 ST_FUNC
void gen_cvt_ftoi(int t
)
1025 int ft
= vtop
->type
.t
& VT_BTYPE
;
1026 int l
= (t
& VT_BTYPE
) == VT_LLONG
;
1027 int u
= t
& VT_UNSIGNED
;
1028 if (ft
== VT_LDOUBLE
) {
1030 (u
? TOK___fixunstfdi
: TOK___fixtfdi
) :
1031 (u
? TOK___fixunstfsi
: TOK___fixtfsi
);
1032 vpush_global_sym(&func_old_type
, func
);
1039 int rr
= freg(gv(RC_FLOAT
)), dr
;
1041 dr
= get_reg(RC_INT
);
1045 EIu(0x53, 1, dr
, rr
, ((0x60 | (ft
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[wl][u].[sd] rtz
1049 ST_FUNC
void gen_cvt_ftof(int dt
)
1051 int st
= vtop
->type
.t
& VT_BTYPE
, rs
, rd
;
1055 if (dt
== VT_LDOUBLE
|| st
== VT_LDOUBLE
) {
1056 int func
= (dt
== VT_LDOUBLE
) ?
1057 (st
== VT_FLOAT
? TOK___extendsftf2
: TOK___extenddftf2
) :
1058 (dt
== VT_FLOAT
? TOK___trunctfsf2
: TOK___trunctfdf2
);
1059 /* We can't use gfunc_call, as func_old_type works like vararg
1060 functions, and on riscv unnamed float args are passed like
1061 integers. But we really need them in the float argument registers
1062 for extendsftf2/extenddftf2. So, do it explicitely. */
1064 if (dt
== VT_LDOUBLE
)
1068 assert(vtop
->r2
< 7);
1069 if (vtop
->r2
!= 1 + vtop
->r
) {
1070 EI(0x13, 0, ireg(vtop
->r
) + 1, ireg(vtop
->r2
), 0); // mv Ra+1, RR2
1071 vtop
->r2
= 1 + vtop
->r
;
1074 vpush_global_sym(&func_old_type
, func
);
1079 if (dt
== VT_LDOUBLE
)
1080 vtop
->r
= REG_IRET
, vtop
->r2
= REG_IRET
+1;
1084 assert (dt
== VT_FLOAT
|| dt
== VT_DOUBLE
);
1085 assert (st
== VT_FLOAT
|| st
== VT_DOUBLE
);
1087 rd
= get_reg(RC_FLOAT
);
1088 if (dt
== VT_DOUBLE
)
1089 EI(0x53, 7, freg(rd
), freg(rs
), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm)
1091 EI(0x53, 7, freg(rd
), freg(rs
), (0x20 << 5) | 1); // fcvt.s.d RD, RS
1096 ST_FUNC
void ggoto(void)
1102 ST_FUNC
void gen_vla_sp_save(int addr
)
1104 ES(0x23, 3, 8, 2, addr
); // sd sp, fc(s0)
1107 ST_FUNC
void gen_vla_sp_restore(int addr
)
1109 EI(0x03, 3, 2, 8, addr
); // ld sp, fc(s0)
1112 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
)
1114 int rr
= ireg(gv(RC_INT
));
1115 EI(0x13, 0, rr
, rr
, 15); // addi RR, RR, 15
1116 EI(0x13, 7, rr
, rr
, -16); // andi, RR, RR, -16
1117 o(0x33 | (2 << 7) | (2 << 15) | (rr
<< 20) | (0x20 << 25)); //sub sp, sp, rr