2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 /* #define NB_ASM_REGS 8 */
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30 #define TOK_ASM_alllast TOK_ASM_subps
32 #define OPC_B 0x01 /* only used with OPC_WL */
33 #define OPC_WL 0x02 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x04 /* register is added to opcode */
36 #define OPC_MODRM 0x08 /* modrm encoding */
38 #define OPCT_MASK 0x70
39 #define OPC_FWAIT 0x10 /* add fwait opcode */
40 #define OPC_SHIFT 0x20 /* shift opcodes */
41 #define OPC_ARITH 0x30 /* arithmetic opcodes */
42 #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
43 #define OPC_TEST 0x50 /* test opcodes */
44 #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
46 #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
47 #ifdef TCC_TARGET_X86_64
48 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
49 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
50 # define OPC_WLX OPC_WLQ
51 # define OPC_BWLX OPC_BWLQ
53 # define OPC_WLX OPC_WL
54 # define OPC_BWLX OPC_BWL
57 #define OPC_GROUP_SHIFT 13
59 /* in order to compress the operand type, we use specific operands and
62 OPT_REG8
=0, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_REG16
, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_REG32
, /* warning: value is hardcoded from TOK_ASM_xxx */
65 #ifdef TCC_TARGET_X86_64
66 OPT_REG64
, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_MMX
, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_SSE
, /* warning: value is hardcoded from TOK_ASM_xxx */
70 OPT_CR
, /* warning: value is hardcoded from TOK_ASM_xxx */
71 OPT_TR
, /* warning: value is hardcoded from TOK_ASM_xxx */
72 OPT_DB
, /* warning: value is hardcoded from TOK_ASM_xxx */
75 #ifdef TCC_TARGET_X86_64
76 OPT_REG8_LOW
, /* %spl,%bpl,%sil,%dil, encoded like ah,ch,dh,bh, but
77 with REX prefix, not used in insn templates */
83 #ifdef TCC_TARGET_X86_64
86 OPT_EAX
, /* %al, %ax, %eax or %rax register */
87 OPT_ST0
, /* %st(0) register */
88 OPT_CL
, /* %cl register */
89 OPT_DX
, /* %dx register */
90 OPT_ADDR
, /* OP_EA with only offset */
91 OPT_INDIR
, /* *(expr) */
94 OPT_IM
, /* IM8 | IM16 | IM32 */
95 OPT_REG
, /* REG8 | REG16 | REG32 | REG64 */
96 OPT_REGW
, /* REG16 | REG32 | REG64 */
97 OPT_IMW
, /* IM16 | IM32 */
98 OPT_MMXSSE
, /* MMX | SSE */
99 OPT_DISP
, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
100 OPT_DISP8
, /* Like OPT_ADDR, but only 8bit (short jumps) */
101 /* can be ored with any OPT_xxx */
105 #define OP_REG8 (1 << OPT_REG8)
106 #define OP_REG16 (1 << OPT_REG16)
107 #define OP_REG32 (1 << OPT_REG32)
108 #define OP_MMX (1 << OPT_MMX)
109 #define OP_SSE (1 << OPT_SSE)
110 #define OP_CR (1 << OPT_CR)
111 #define OP_TR (1 << OPT_TR)
112 #define OP_DB (1 << OPT_DB)
113 #define OP_SEG (1 << OPT_SEG)
114 #define OP_ST (1 << OPT_ST)
115 #define OP_IM8 (1 << OPT_IM8)
116 #define OP_IM8S (1 << OPT_IM8S)
117 #define OP_IM16 (1 << OPT_IM16)
118 #define OP_IM32 (1 << OPT_IM32)
119 #define OP_EAX (1 << OPT_EAX)
120 #define OP_ST0 (1 << OPT_ST0)
121 #define OP_CL (1 << OPT_CL)
122 #define OP_DX (1 << OPT_DX)
123 #define OP_ADDR (1 << OPT_ADDR)
124 #define OP_INDIR (1 << OPT_INDIR)
125 #ifdef TCC_TARGET_X86_64
126 # define OP_REG64 (1 << OPT_REG64)
127 # define OP_REG8_LOW (1 << OPT_REG8_LOW)
128 # define OP_IM64 (1 << OPT_IM64)
129 # define OP_EA32 (OP_EA << 1)
132 # define OP_REG8_LOW 0
137 #define OP_EA 0x40000000
138 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
140 #ifdef TCC_TARGET_X86_64
141 # define TREG_XAX TREG_RAX
142 # define TREG_XCX TREG_RCX
143 # define TREG_XDX TREG_RDX
145 # define TREG_XAX TREG_EAX
146 # define TREG_XCX TREG_ECX
147 # define TREG_XDX TREG_EDX
150 typedef struct ASMInstr
{
155 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
158 typedef struct Operand
{
160 int8_t reg
; /* register, -1 if none */
161 int8_t reg2
; /* second register, -1 if none */
166 static const uint8_t reg_to_size
[9] = {
171 #ifdef TCC_TARGET_X86_64
175 0, 0, 1, 0, 2, 0, 0, 0, 3
178 #define NB_TEST_OPCODES 30
180 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
213 static const uint8_t segment_prefixes
[] = {
222 static const ASMInstr asm_instrs
[] = {
224 /* This removes a 0x0f in the second byte */
225 #define O(o) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o))
226 /* This constructs instr_type from opcode, type and group. */
227 #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
228 #define DEF_ASM_OP0(name, opcode)
229 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0 },
230 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
231 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
232 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
233 #ifdef TCC_TARGET_X86_64
234 # include "x86_64-asm.h"
236 # include "i386-asm.h"
242 static const uint16_t op0_codes
[] = {
244 #define DEF_ASM_OP0(x, opcode) opcode,
245 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
246 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
247 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
248 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
249 #ifdef TCC_TARGET_X86_64
250 # include "x86_64-asm.h"
252 # include "i386-asm.h"
256 static inline int get_reg_shift(TCCState
*s1
)
259 v
= asm_int_expr(s1
);
274 expect("1, 2, 4 or 8 constant");
281 #ifdef TCC_TARGET_X86_64
282 static int asm_parse_numeric_reg(int *type
)
285 if (tok
>= TOK_IDENT
&& tok
< tok_ident
) {
286 const char *s
= table_ident
[tok
- TOK_IDENT
]->str
;
295 /* Don't allow leading '0'. */
296 if ((c
= *s
++) >= '1' && c
<= '9')
300 if ((c
= *s
) >= '0' && c
<= '5')
301 s
++, reg
= reg
* 10 + c
- '0';
306 else if (*type
!= OP_REG64
)
308 else if (c
== 'b' && !s
[1])
310 else if (c
== 'w' && !s
[1])
312 else if (c
== 'd' && !s
[1])
321 static int asm_parse_reg(int *type
)
328 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
329 reg
= tok
- TOK_ASM_eax
;
331 #ifdef TCC_TARGET_X86_64
332 } else if (tok
>= TOK_ASM_rax
&& tok
<= TOK_ASM_rdi
) {
333 reg
= tok
- TOK_ASM_rax
;
335 } else if (tok
== TOK_ASM_rip
) {
336 reg
= -2; /* Probably should use different escape code. */
338 } else if ((reg
= asm_parse_numeric_reg(type
)) >= 0
339 && (*type
== OP_REG32
|| *type
== OP_REG64
)) {
350 static void parse_operand(TCCState
*s1
, Operand
*op
)
364 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
365 reg
= tok
- TOK_ASM_al
;
366 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
368 if ((op
->type
& OP_REG
) && op
->reg
== TREG_XAX
)
370 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_XCX
)
372 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_XDX
)
374 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
376 op
->reg
= tok
- TOK_ASM_dr0
;
377 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
379 op
->reg
= tok
- TOK_ASM_es
;
380 } else if (tok
== TOK_ASM_st
) {
386 if (tok
!= TOK_PPNUM
)
390 if ((unsigned)reg
>= 8 || p
[1] != '\0')
399 #ifdef TCC_TARGET_X86_64
400 } else if (tok
>= TOK_ASM_spl
&& tok
<= TOK_ASM_dil
) {
401 op
->type
= OP_REG8
| OP_REG8_LOW
;
402 op
->reg
= 4 + tok
- TOK_ASM_spl
;
403 } else if ((op
->reg
= asm_parse_numeric_reg(&op
->type
)) >= 0) {
408 tcc_error("unknown register %%%s", get_tok_str(tok
, &tokc
));
412 } else if (tok
== '$') {
419 if (op
->e
.v
== (uint8_t)op
->e
.v
)
421 if (op
->e
.v
== (int8_t)op
->e
.v
)
423 if (op
->e
.v
== (uint16_t)op
->e
.v
)
425 #ifdef TCC_TARGET_X86_64
426 if (op
->e
.v
!= (int32_t)op
->e
.v
&& op
->e
.v
!= (uint32_t)op
->e
.v
)
431 /* address(reg,reg2,shift) with all variants */
446 /* bracketed offset expression */
460 op
->reg
= asm_parse_reg(&type
);
465 op
->reg2
= asm_parse_reg(&type
);
469 op
->shift
= get_reg_shift(s1
);
476 if (op
->reg
== -1 && op
->reg2
== -1)
482 /* XXX: unify with C code output ? */
483 ST_FUNC
void gen_expr32(ExprValue
*pe
)
486 /* If PC-relative, always set VT_SYM, even without symbol,
487 so as to force a relocation to be emitted. */
488 gen_addrpc32(VT_SYM
, pe
->sym
, pe
->v
);
490 gen_addr32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
493 #ifdef TCC_TARGET_X86_64
494 ST_FUNC
void gen_expr64(ExprValue
*pe
)
496 gen_addr64(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
500 /* XXX: unify with C code output ? */
501 static void gen_disp32(ExprValue
*pe
)
504 if (sym
&& sym
->r
== cur_text_section
->sh_num
) {
505 /* same section: we can output an absolute value. Note
506 that the TCC compiler behaves differently here because
507 it always outputs a relocation to ease (future) code
508 elimination in the linker */
509 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
511 if (sym
&& sym
->type
.t
== VT_VOID
) {
512 sym
->type
.t
= VT_FUNC
;
513 sym
->type
.ref
= NULL
;
515 gen_addrpc32(VT_SYM
, sym
, pe
->v
);
519 /* generate the modrm operand */
520 static inline int asm_modrm(int reg
, Operand
*op
)
522 int mod
, reg1
, reg2
, sib_reg1
;
524 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
525 g(0xc0 + (reg
<< 3) + op
->reg
);
526 } else if (op
->reg
== -1 && op
->reg2
== -1) {
527 /* displacement only */
528 #ifdef TCC_TARGET_X86_64
529 g(0x04 + (reg
<< 3));
532 g(0x05 + (reg
<< 3));
535 #ifdef TCC_TARGET_X86_64
536 } else if (op
->reg
== -2) {
537 ExprValue
*pe
= &op
->e
;
538 g(0x05 + (reg
<< 3));
539 gen_addrpc32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
544 /* fist compute displacement encoding */
545 if (sib_reg1
== -1) {
548 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
550 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
555 /* compute if sib byte needed */
559 g(mod
+ (reg
<< 3) + reg1
);
564 reg2
= 4; /* indicate no index */
565 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
570 } else if (mod
== 0x80 || op
->reg
== -1) {
577 #ifdef TCC_TARGET_X86_64
583 static void asm_rex(int width64
, Operand
*ops
, int nb_ops
, int *op_type
,
586 unsigned char rex
= width64
? 0x48 : 0;
587 int saw_high_8bit
= 0;
590 /* No mod/rm byte, but we might have a register op nevertheless
591 (we will add it to the opcode later). */
592 for(i
= 0; i
< nb_ops
; i
++) {
593 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
594 if (ops
[i
].reg
>= 8) {
597 } else if (ops
[i
].type
& OP_REG8_LOW
)
599 else if (ops
[i
].type
& OP_REG8
&& ops
[i
].reg
>= 4)
600 /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
601 saw_high_8bit
= ops
[i
].reg
;
607 if (ops
[regi
].reg
>= 8) {
610 } else if (ops
[regi
].type
& OP_REG8_LOW
)
612 else if (ops
[regi
].type
& OP_REG8
&& ops
[regi
].reg
>= 4)
613 /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
614 saw_high_8bit
= ops
[regi
].reg
;
616 if (ops
[rmi
].type
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_EA
)) {
617 if (ops
[rmi
].reg
>= 8) {
620 } else if (ops
[rmi
].type
& OP_REG8_LOW
)
622 else if (ops
[rmi
].type
& OP_REG8
&& ops
[rmi
].reg
>= 4)
623 /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
624 saw_high_8bit
= ops
[rmi
].reg
;
626 if (ops
[rmi
].type
& OP_EA
&& ops
[rmi
].reg2
>= 8) {
633 tcc_error("can't encode register %%%ch when REX prefix is required",
634 "acdb"[saw_high_8bit
-4]);
640 static void maybe_print_stats (void)
642 static int already
= 1;
644 /* print stats about opcodes */
646 const struct ASMInstr
*pa
;
649 int nb_op_vals
, i
, j
;
653 memset(freq
, 0, sizeof(freq
));
654 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
656 //for(i=0;i<pa->nb_ops;i++) {
657 for(j
=0;j
<nb_op_vals
;j
++) {
658 //if (pa->op_type[i] == op_vals[j])
659 if (pa
->instr_type
== op_vals
[j
])
662 //op_vals[nb_op_vals++] = pa->op_type[i];
663 op_vals
[nb_op_vals
++] = pa
->instr_type
;
667 for(i
=0;i
<nb_op_vals
;i
++) {
669 //if ((v & (v - 1)) != 0)
670 printf("%3d: %08x\n", i
, v
);
672 printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
673 (int)sizeof(asm_instrs
),
674 (int)sizeof(asm_instrs
) / (int)sizeof(ASMInstr
),
675 freq
[0], freq
[1], freq
[2], freq
[3]);
679 ST_FUNC
void asm_opcode(TCCState
*s1
, int opcode
)
682 int i
, modrm_index
, modreg_index
, reg
, v
, op1
, seg_prefix
, pc
;
684 Operand ops
[MAX_OPERANDS
], *pop
;
685 int op_type
[3]; /* decoded op type */
686 int alltypes
; /* OR of all operand types */
689 #ifdef TCC_TARGET_X86_64
694 /* force synthetic ';' after prefix instruction, so we can handle */
695 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
696 if (opcode
>= TOK_ASM_wait
&& opcode
<= TOK_ASM_repnz
)
705 if (tok
== ';' || tok
== TOK_LINEFEED
)
707 if (nb_ops
>= MAX_OPERANDS
) {
708 tcc_error("incorrect number of operands");
710 parse_operand(s1
, pop
);
712 if (pop
->type
!= OP_SEG
|| seg_prefix
)
713 tcc_error("incorrect prefix");
714 seg_prefix
= segment_prefixes
[pop
->reg
];
716 parse_operand(s1
, pop
);
717 if (!(pop
->type
& OP_EA
)) {
718 tcc_error("segment prefix must be followed by memory reference");
728 s
= 0; /* avoid warning */
730 /* optimize matching by using a lookup table (no hashing is needed
732 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
733 int it
= pa
->instr_type
& OPCT_MASK
;
735 if (it
== OPC_FARITH
) {
736 v
= opcode
- pa
->sym
;
737 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
739 } else if (it
== OPC_ARITH
) {
740 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8*NBWLX
))
742 s
= (opcode
- pa
->sym
) % NBWLX
;
743 if ((pa
->instr_type
& OPC_BWLX
) == OPC_WLX
)
745 /* We need to reject the xxxb opcodes that we accepted above.
746 Note that pa->sym for WLX opcodes is the 'w' token,
747 to get the 'b' token subtract one. */
748 if (((opcode
- pa
->sym
+ 1) % NBWLX
) == 0)
752 } else if (it
== OPC_SHIFT
) {
753 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7*NBWLX
))
755 s
= (opcode
- pa
->sym
) % NBWLX
;
756 } else if (it
== OPC_TEST
) {
757 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
759 /* cmovxx is a test opcode but accepts multiple sizes.
760 TCC doesn't accept the suffixed mnemonic, instead we
761 simply force size autodetection always. */
762 if (pa
->instr_type
& OPC_WLX
)
764 } else if (pa
->instr_type
& OPC_B
) {
765 #ifdef TCC_TARGET_X86_64
766 /* Some instructions don't have the full size but only
767 bwl form. insb e.g. */
768 if ((pa
->instr_type
& OPC_WLQ
) != OPC_WLQ
769 && !(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
772 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
))
774 s
= opcode
- pa
->sym
;
775 } else if (pa
->instr_type
& OPC_WLX
) {
776 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
778 s
= opcode
- pa
->sym
+ 1;
780 if (pa
->sym
!= opcode
)
783 if (pa
->nb_ops
!= nb_ops
)
785 #ifdef TCC_TARGET_X86_64
786 /* Special case for moves. Selecting the IM64->REG64 form
787 should only be done if we really have an >32bit imm64, and that
788 is hardcoded. Ignore it here. */
789 if (pa
->opcode
== 0xb0 && ops
[0].type
!= OP_IM64
790 && ops
[1].type
== OP_REG64
791 && !(pa
->instr_type
& OPC_0F
))
794 /* now decode and check each operand */
796 for(i
= 0; i
< nb_ops
; i
++) {
798 op1
= pa
->op_type
[i
];
802 v
= OP_IM8
| OP_IM16
| OP_IM32
;
805 v
= OP_REG8
| OP_REG16
| OP_REG32
| OP_REG64
;
808 v
= OP_REG16
| OP_REG32
| OP_REG64
;
811 v
= OP_IM16
| OP_IM32
;
827 if ((ops
[i
].type
& v
) == 0)
829 alltypes
|= ops
[i
].type
;
831 /* all is matching ! */
836 if (opcode
>= TOK_ASM_first
&& opcode
<= TOK_ASM_last
) {
838 b
= op0_codes
[opcode
- TOK_ASM_first
];
843 } else if (opcode
<= TOK_ASM_alllast
) {
844 tcc_error("bad operand with opcode '%s'",
845 get_tok_str(opcode
, NULL
));
847 tcc_error("unknown opcode '%s'",
848 get_tok_str(opcode
, NULL
));
851 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
853 #ifdef TCC_TARGET_X86_64
854 /* XXX the autosize should rather be zero, to not have to adjust this
856 if ((pa
->instr_type
& OPC_BWLQ
) == OPC_B
)
860 /* Check for register operands providing hints about the size.
861 Start from the end, i.e. destination operands. This matters
862 only for opcodes accepting different sized registers, lar and lsl
864 for(i
= nb_ops
- 1; s
== autosize
&& i
>= 0; i
--) {
865 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
866 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
869 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
870 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
)))
872 else if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
873 (ops
[0].type
& OP_EA
))
876 tcc_error("cannot infer opcode suffix");
880 #ifdef TCC_TARGET_X86_64
881 /* Generate addr32 prefix if needed */
882 for(i
= 0; i
< nb_ops
; i
++) {
883 if (ops
[i
].type
& OP_EA32
) {
889 /* generate data16 prefix if needed */
894 /* accepting mmx+sse in all operands --> needs 0x66 to
895 switch to sse mode. Accepting only sse in an operand --> is
896 already SSE insn and needs 0x66/f2/f3 handling. */
897 for (i
= 0; i
< nb_ops
; i
++)
898 if ((op_type
[i
] & (OP_MMX
| OP_SSE
)) == (OP_MMX
| OP_SSE
)
899 && ops
[i
].type
& OP_SSE
)
904 #ifdef TCC_TARGET_X86_64
906 if (s
== 3 || (alltypes
& OP_REG64
)) {
907 /* generate REX prefix */
909 for(i
= 0; i
< nb_ops
; i
++) {
910 if (op_type
[i
] == OP_REG64
) {
911 /* If only 64bit regs are accepted in one operand
912 this is a default64 instruction without need for
918 /* XXX find better encoding for the default64 instructions. */
919 if (((opcode
!= TOK_ASM_push
&& opcode
!= TOK_ASM_pop
920 && opcode
!= TOK_ASM_pushw
&& opcode
!= TOK_ASM_pushl
921 && opcode
!= TOK_ASM_pushq
&& opcode
!= TOK_ASM_popw
922 && opcode
!= TOK_ASM_popl
&& opcode
!= TOK_ASM_popq
923 && opcode
!= TOK_ASM_call
&& opcode
!= TOK_ASM_jmp
))
929 /* now generates the operation */
930 if (OPCT_IS(pa
->instr_type
, OPC_FWAIT
))
936 if (pa
->instr_type
& OPC_0F
)
937 v
= ((v
& ~0xff) << 8) | 0x0f00 | (v
& 0xff);
938 if ((v
== 0x69 || v
== 0x6b) && nb_ops
== 2) {
939 /* kludge for imul $im, %reg */
942 op_type
[2] = op_type
[1];
943 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
944 v
--; /* int $3 case */
946 } else if ((v
== 0x06 || v
== 0x07)) {
947 if (ops
[0].reg
>= 4) {
948 /* push/pop %fs or %gs */
949 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
951 v
+= ops
[0].reg
<< 3;
954 } else if (v
<= 0x05) {
956 v
+= ((opcode
- TOK_ASM_addb
) / NBWLX
) << 3;
957 } else if ((pa
->instr_type
& (OPCT_MASK
| OPC_MODRM
)) == OPC_FARITH
) {
959 v
+= ((opcode
- pa
->sym
) / 6) << 3;
962 /* search which operand will be used for modrm */
965 if (pa
->instr_type
& OPC_MODRM
) {
967 /* A modrm opcode without operands is a special case (e.g. mfence).
968 It has a group and acts as if there's an register operand 0
971 ops
[i
].type
= OP_REG
;
975 /* first look for an ea operand */
976 for(i
= 0;i
< nb_ops
; i
++) {
977 if (op_type
[i
] & OP_EA
)
980 /* then if not found, a register or indirection (shift instructions) */
981 for(i
= 0;i
< nb_ops
; i
++) {
982 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
986 tcc_error("bad op table");
990 /* if a register is used in another operand then it is
991 used instead of group */
992 for(i
= 0;i
< nb_ops
; i
++) {
994 if (i
!= modrm_index
&&
995 (t
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
1001 #ifdef TCC_TARGET_X86_64
1002 asm_rex (rex64
, ops
, nb_ops
, op_type
, modreg_index
, modrm_index
);
1005 if (pa
->instr_type
& OPC_REG
) {
1006 /* mov $im, %reg case */
1007 if (v
== 0xb0 && s
>= 1)
1009 for(i
= 0; i
< nb_ops
; i
++) {
1010 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
1016 if (pa
->instr_type
& OPC_B
)
1018 if (nb_ops
== 1 && pa
->op_type
[0] == OPT_DISP8
) {
1022 /* see if we can really generate the jump with a byte offset */
1026 if (sym
->r
!= cur_text_section
->sh_num
)
1028 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2 - (v
>= 0xff);
1029 if (jmp_disp
== (int8_t)jmp_disp
) {
1030 /* OK to generate jump */
1032 ops
[0].e
.v
= jmp_disp
;
1033 op_type
[0] = OP_IM8S
;
1036 /* long jump will be allowed. need to modify the
1038 if (v
== 0xeb) /* jmp */
1040 else if (v
== 0x70) /* jcc */
1043 tcc_error("invalid displacement");
1046 if (OPCT_IS(pa
->instr_type
, OPC_TEST
))
1047 v
+= test_bits
[opcode
- pa
->sym
];
1051 op1
= (v
>> 8) & 0xff;
1056 if (OPCT_IS(pa
->instr_type
, OPC_SHIFT
)) {
1057 reg
= (opcode
- pa
->sym
) / NBWLX
;
1060 } else if (OPCT_IS(pa
->instr_type
, OPC_ARITH
)) {
1061 reg
= (opcode
- pa
->sym
) / NBWLX
;
1062 } else if (OPCT_IS(pa
->instr_type
, OPC_FARITH
)) {
1063 reg
= (opcode
- pa
->sym
) / 6;
1065 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
1069 if (pa
->instr_type
& OPC_MODRM
) {
1070 /* if a register is used in another operand then it is
1071 used instead of group */
1072 if (modreg_index
>= 0)
1073 reg
= ops
[modreg_index
].reg
;
1074 pc
= asm_modrm(reg
, &ops
[modrm_index
]);
1077 /* emit constants */
1078 #ifndef TCC_TARGET_X86_64
1079 if (!(pa
->instr_type
& OPC_0F
)
1080 && (pa
->opcode
== 0x9a || pa
->opcode
== 0xea)) {
1081 /* ljmp or lcall kludge */
1082 gen_expr32(&ops
[1].e
);
1084 tcc_error("cannot relocate");
1085 gen_le16(ops
[0].e
.v
);
1089 for(i
= 0;i
< nb_ops
; i
++) {
1091 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
| OP_IM8S
| OP_ADDR
)) {
1092 /* if multiple sizes are given it means we must look
1094 if ((v
| OP_IM8
| OP_IM64
) == (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
)) {
1099 else if (s
== 2 || (v
& OP_IM64
) == 0)
1105 if ((v
& (OP_IM8
| OP_IM8S
| OP_IM16
)) && ops
[i
].e
.sym
)
1106 tcc_error("cannot relocate");
1108 if (v
& (OP_IM8
| OP_IM8S
)) {
1110 } else if (v
& OP_IM16
) {
1111 gen_le16(ops
[i
].e
.v
);
1112 #ifdef TCC_TARGET_X86_64
1113 } else if (v
& OP_IM64
) {
1114 gen_expr64(&ops
[i
].e
);
1116 } else if (pa
->op_type
[i
] == OPT_DISP
|| pa
->op_type
[i
] == OPT_DISP8
) {
1117 gen_disp32(&ops
[i
].e
);
1119 gen_expr32(&ops
[i
].e
);
1124 /* after immediate operands, adjust pc-relative address */
1126 add32le(text_section
->data
+ pc
- 4, pc
- ind
);
1129 /* return the constraint priority (we allocate first the lowest
1130 numbered constraints) */
1131 static inline int constraint_priority(const char *str
)
1133 int priority
, c
, pr
;
1135 /* we take the lowest priority */
1172 tcc_error("unknown constraint '%c'", c
);
1181 static const char *skip_constraint_modifiers(const char *p
)
1183 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1188 #define REG_OUT_MASK 0x01
1189 #define REG_IN_MASK 0x02
1191 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1193 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
,
1194 int nb_operands
, int nb_outputs
,
1195 const uint8_t *clobber_regs
,
1199 int sorted_op
[MAX_ASM_OPERANDS
];
1200 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1202 uint8_t regs_allocated
[NB_ASM_REGS
];
1205 for(i
=0;i
<nb_operands
;i
++) {
1207 op
->input_index
= -1;
1213 /* compute constraint priority and evaluate references to output
1214 constraints if input constraints */
1215 for(i
=0;i
<nb_operands
;i
++) {
1217 str
= op
->constraint
;
1218 str
= skip_constraint_modifiers(str
);
1219 if (isnum(*str
) || *str
== '[') {
1220 /* this is a reference to another constraint */
1221 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1222 if ((unsigned)k
>= i
|| i
< nb_outputs
)
1223 tcc_error("invalid reference in constraint %d ('%s')",
1226 if (operands
[k
].input_index
>= 0)
1227 tcc_error("cannot reference twice the same operand");
1228 operands
[k
].input_index
= i
;
1231 op
->priority
= constraint_priority(str
);
1235 /* sort operands according to their priority */
1236 for(i
=0;i
<nb_operands
;i
++)
1238 for(i
=0;i
<nb_operands
- 1;i
++) {
1239 for(j
=i
+1;j
<nb_operands
;j
++) {
1240 p1
= operands
[sorted_op
[i
]].priority
;
1241 p2
= operands
[sorted_op
[j
]].priority
;
1244 sorted_op
[i
] = sorted_op
[j
];
1250 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
1251 if (clobber_regs
[i
])
1252 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1254 regs_allocated
[i
] = 0;
1256 /* esp cannot be used */
1257 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
1258 /* ebp cannot be used yet */
1259 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1261 /* allocate registers and generate corresponding asm moves */
1262 for(i
=0;i
<nb_operands
;i
++) {
1265 str
= op
->constraint
;
1266 /* no need to allocate references */
1267 if (op
->ref_index
>= 0)
1269 /* select if register is used for output, input or both */
1270 if (op
->input_index
>= 0) {
1271 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1272 } else if (j
< nb_outputs
) {
1273 reg_mask
= REG_OUT_MASK
;
1275 reg_mask
= REG_IN_MASK
;
1286 if (j
>= nb_outputs
)
1287 tcc_error("'%c' modifier can only be applied to outputs", c
);
1288 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1291 /* allocate both eax and edx */
1292 if (is_reg_allocated(TREG_XAX
) ||
1293 is_reg_allocated(TREG_XDX
))
1297 regs_allocated
[TREG_XAX
] |= reg_mask
;
1298 regs_allocated
[TREG_XDX
] |= reg_mask
;
1318 if (is_reg_allocated(reg
))
1322 /* eax, ebx, ecx or edx */
1323 for(reg
= 0; reg
< 4; reg
++) {
1324 if (!is_reg_allocated(reg
))
1330 case 'p': /* A general address, for x86(64) any register is acceptable*/
1331 /* any general register */
1332 for(reg
= 0; reg
< 8; reg
++) {
1333 if (!is_reg_allocated(reg
))
1338 /* now we can reload in the register */
1341 regs_allocated
[reg
] |= reg_mask
;
1345 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1351 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1356 /* nothing special to do because the operand is already in
1357 memory, except if the pointer itself is stored in a
1358 memory variable (VT_LLOCAL case) */
1359 /* XXX: fix constant case */
1360 /* if it is a reference to a memory zone, it must lie
1361 in a register, so we reserve the register in the
1362 input registers and a load will be generated
1364 if (j
< nb_outputs
|| c
== 'm') {
1365 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1366 /* any general register */
1367 for(reg
= 0; reg
< 8; reg
++) {
1368 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1373 /* now we can reload in the register */
1374 regs_allocated
[reg
] |= REG_IN_MASK
;
1381 tcc_error("asm constraint %d ('%s') could not be satisfied",
1385 /* if a reference is present for that operand, we assign it too */
1386 if (op
->input_index
>= 0) {
1387 operands
[op
->input_index
].reg
= op
->reg
;
1388 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1392 /* compute out_reg. It is used to store outputs registers to memory
1393 locations references by pointers (VT_LLOCAL case) */
1395 for(i
=0;i
<nb_operands
;i
++) {
1398 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1400 for(reg
= 0; reg
< 8; reg
++) {
1401 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1404 tcc_error("could not find free output register for reloading");
1411 /* print sorted constraints */
1413 for(i
=0;i
<nb_operands
;i
++) {
1416 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1418 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1424 printf("out_reg=%d\n", *pout_reg
);
1428 ST_FUNC
void subst_asm_operand(CString
*add_str
,
1429 SValue
*sv
, int modifier
)
1431 int r
, reg
, size
, val
;
1435 if ((r
& VT_VALMASK
) == VT_CONST
) {
1436 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n' &&
1438 cstr_ccat(add_str
, '$');
1440 const char *name
= get_tok_str(sv
->sym
->v
, NULL
);
1441 if (sv
->sym
->v
>= SYM_FIRST_ANOM
) {
1442 /* In case of anonymuous symbols ("L.42", used
1443 for static data labels) we can't find them
1444 in the C symbol table when later looking up
1445 this name. So enter them now into the asm label
1446 list when we still know the symbol. */
1447 get_asm_sym(tok_alloc(name
, strlen(name
))->tok
, sv
->sym
);
1449 cstr_cat(add_str
, name
, -1);
1450 if ((uint32_t)sv
->c
.i
== 0)
1452 cstr_ccat(add_str
, '+');
1455 if (modifier
== 'n')
1457 snprintf(buf
, sizeof(buf
), "%d", (int)sv
->c
.i
);
1458 cstr_cat(add_str
, buf
, -1);
1460 #ifdef TCC_TARGET_X86_64
1462 cstr_cat(add_str
, "(%rip)", -1);
1464 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1465 #ifdef TCC_TARGET_X86_64
1466 snprintf(buf
, sizeof(buf
), "%d(%%rbp)", (int)sv
->c
.i
);
1468 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", (int)sv
->c
.i
);
1470 cstr_cat(add_str
, buf
, -1);
1471 } else if (r
& VT_LVAL
) {
1472 reg
= r
& VT_VALMASK
;
1473 if (reg
>= VT_CONST
)
1474 tcc_error("internal compiler error");
1475 snprintf(buf
, sizeof(buf
), "(%%%s)",
1476 #ifdef TCC_TARGET_X86_64
1477 get_tok_str(TOK_ASM_rax
+ reg
, NULL
)
1479 get_tok_str(TOK_ASM_eax
+ reg
, NULL
)
1482 cstr_cat(add_str
, buf
, -1);
1485 reg
= r
& VT_VALMASK
;
1486 if (reg
>= VT_CONST
)
1487 tcc_error("internal compiler error");
1489 /* choose register operand size */
1490 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
||
1491 (sv
->type
.t
& VT_BTYPE
) == VT_BOOL
)
1493 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1495 #ifdef TCC_TARGET_X86_64
1496 else if ((sv
->type
.t
& VT_BTYPE
) == VT_LLONG
)
1501 if (size
== 1 && reg
>= 4)
1504 if (modifier
== 'b') {
1506 tcc_error("cannot use byte register");
1508 } else if (modifier
== 'h') {
1510 tcc_error("cannot use byte register");
1512 } else if (modifier
== 'w') {
1514 } else if (modifier
== 'k') {
1516 #ifdef TCC_TARGET_X86_64
1517 } else if (modifier
== 'q') {
1524 reg
= TOK_ASM_ah
+ reg
;
1527 reg
= TOK_ASM_al
+ reg
;
1530 reg
= TOK_ASM_ax
+ reg
;
1533 reg
= TOK_ASM_eax
+ reg
;
1535 #ifdef TCC_TARGET_X86_64
1537 reg
= TOK_ASM_rax
+ reg
;
1541 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1542 cstr_cat(add_str
, buf
, -1);
1546 /* generate prolog and epilog code for asm statement */
1547 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1548 int nb_outputs
, int is_output
,
1549 uint8_t *clobber_regs
,
1552 uint8_t regs_allocated
[NB_ASM_REGS
];
1555 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1557 /* mark all used registers */
1558 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1559 for(i
= 0; i
< nb_operands
;i
++) {
1562 regs_allocated
[op
->reg
] = 1;
1565 /* generate reg save code */
1566 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1568 if (regs_allocated
[reg
]) {
1573 /* generate load code */
1574 for(i
= 0; i
< nb_operands
; i
++) {
1577 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1579 /* memory reference case (for both input and
1583 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
| VT_LVAL
;
1586 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1587 /* load value in register */
1588 load(op
->reg
, op
->vt
);
1593 load(TREG_XDX
, &sv
);
1599 /* generate save code */
1600 for(i
= 0 ; i
< nb_outputs
; i
++) {
1603 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1604 if (!op
->is_memory
) {
1607 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1610 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1611 store(op
->reg
, &sv
);
1614 store(op
->reg
, op
->vt
);
1619 store(TREG_XDX
, &sv
);
1624 /* generate reg restore code */
1625 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1627 if (regs_allocated
[reg
]) {
1634 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1639 if (!strcmp(str
, "memory") ||
1640 !strcmp(str
, "cc") ||
1641 !strcmp(str
, "flags"))
1643 ts
= tok_alloc(str
, strlen(str
));
1645 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1647 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1649 #ifdef TCC_TARGET_X86_64
1650 } else if (reg
>= TOK_ASM_rax
&& reg
<= TOK_ASM_rdi
) {
1652 } else if (1 && str
[0] == 'r' &&
1653 (((str
[1] == '8' || str
[1] == '9') && str
[2] == 0) ||
1654 (str
[1] == '1' && str
[2] >= '0' && str
[2] <= '5' &&
1656 /* Do nothing for now. We can't parse the high registers. */
1660 tcc_error("invalid clobber register '%s'", str
);
1662 clobber_regs
[reg
] = 1;