2 * ARMv4 code generator for TCC
4 * Copyright (c) 2003 Daniel Glöckner
5 * Copyright (c) 2012 Thomas Preud'homme
7 * Based on i386-gen.c by Fabrice Bellard
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifdef TARGET_DEFS_ONLY
26 #if defined(TCC_ARM_EABI) && !defined(TCC_ARM_VFP)
27 #error "Currently TinyCC only supports float computation with VFP instructions"
30 /* number of available registers */
37 #ifndef TCC_CPU_VERSION
38 # define TCC_CPU_VERSION 5
41 /* a register can belong to several classes. The classes must be
42 sorted from more general to more precise (see gv2() code which does
43 assumptions on it). */
44 #define RC_INT 0x0001 /* generic integer register */
45 #define RC_FLOAT 0x0002 /* generic float register */
61 #define RC_IRET RC_R0 /* function return: integer register */
62 #define RC_IRE2 RC_R1 /* function return: second integer register */
63 #define RC_FRET RC_F0 /* function return: float register */
65 /* pretty names for the registers */
87 #define T2CPR(t) (((t) & VT_BTYPE) != VT_FLOAT ? 0x100 : 0)
90 /* return registers for function */
91 #define REG_IRET TREG_R0 /* single word int return register */
92 #define REG_IRE2 TREG_R1 /* second word return register (for long long) */
93 #define REG_FRET TREG_F0 /* float return register */
96 #define TOK___divdi3 TOK___aeabi_ldivmod
97 #define TOK___moddi3 TOK___aeabi_ldivmod
98 #define TOK___udivdi3 TOK___aeabi_uldivmod
99 #define TOK___umoddi3 TOK___aeabi_uldivmod
102 /* defined if function parameters must be evaluated in reverse order */
103 #define INVERT_FUNC_PARAMS
105 /* defined if structures are passed as pointers. Otherwise structures
106 are directly pushed on stack. */
107 /* #define FUNC_STRUCT_PARAM_AS_PTR */
109 /* pointer size, in bytes */
112 /* long double size and alignment, in bytes */
114 #define LDOUBLE_SIZE 8
118 #define LDOUBLE_SIZE 8
122 #define LDOUBLE_ALIGN 8
124 #define LDOUBLE_ALIGN 4
127 /* maximum alignment (for aligned attribute support) */
130 #define CHAR_IS_UNSIGNED
132 /******************************************************/
133 #else /* ! TARGET_DEFS_ONLY */
134 /******************************************************/
135 #define USING_GLOBALS
138 enum float_abi float_abi
;
140 ST_DATA
const int reg_classes
[NB_REGS
] = {
141 /* r0 */ RC_INT
| RC_R0
,
142 /* r1 */ RC_INT
| RC_R1
,
143 /* r2 */ RC_INT
| RC_R2
,
144 /* r3 */ RC_INT
| RC_R3
,
145 /* r12 */ RC_INT
| RC_R12
,
146 /* f0 */ RC_FLOAT
| RC_F0
,
147 /* f1 */ RC_FLOAT
| RC_F1
,
148 /* f2 */ RC_FLOAT
| RC_F2
,
149 /* f3 */ RC_FLOAT
| RC_F3
,
151 /* d4/s8 */ RC_FLOAT
| RC_F4
,
152 /* d5/s10 */ RC_FLOAT
| RC_F5
,
153 /* d6/s12 */ RC_FLOAT
| RC_F6
,
154 /* d7/s14 */ RC_FLOAT
| RC_F7
,
158 static int func_sub_sp_offset
, last_itod_magic
;
161 #if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
162 static CType float_type
, double_type
, func_float_type
, func_double_type
;
163 ST_FUNC
void arm_init(struct TCCState
*s
)
165 float_type
.t
= VT_FLOAT
;
166 double_type
.t
= VT_DOUBLE
;
167 func_float_type
.t
= VT_FUNC
;
168 func_float_type
.ref
= sym_push(SYM_FIELD
, &float_type
, FUNC_CDECL
, FUNC_OLD
);
169 func_double_type
.t
= VT_FUNC
;
170 func_double_type
.ref
= sym_push(SYM_FIELD
, &double_type
, FUNC_CDECL
, FUNC_OLD
);
172 float_abi
= s
->float_abi
;
173 #ifndef TCC_ARM_HARDFLOAT
174 tcc_warning("soft float ABI currently not supported: default to softfp");
178 #define func_float_type func_old_type
179 #define func_double_type func_old_type
180 #define func_ldouble_type func_old_type
181 ST_FUNC
void arm_init(struct TCCState
*s
)
184 #if !defined (TCC_ARM_VFP)
185 tcc_warning("Support for FPA is deprecated and will be removed in next"
188 #if !defined (TCC_ARM_EABI)
189 tcc_warning("Support for OABI is deprecated and will be removed in next"
196 static int two2mask(int a
,int b
) {
197 return (reg_classes
[a
]|reg_classes
[b
])&~(RC_INT
|RC_FLOAT
);
200 static int regmask(int r
) {
201 return reg_classes
[r
]&~(RC_INT
|RC_FLOAT
);
204 /******************************************************/
206 #if defined(TCC_ARM_EABI) && !defined(CONFIG_TCC_ELFINTERP)
207 const char *default_elfinterp(struct TCCState
*s
)
209 if (s
->float_abi
== ARM_HARD_FLOAT
)
210 return "/lib/ld-linux-armhf.so.3";
212 return "/lib/ld-linux.so.3";
218 /* this is a good place to start adding big-endian support*/
223 if (!cur_text_section
)
224 tcc_error("compiler error! This happens f.ex. if the compiler\n"
225 "can't evaluate constant expressions outside of a function.");
226 if (ind1
> cur_text_section
->data_allocated
)
227 section_realloc(cur_text_section
, ind1
);
228 cur_text_section
->data
[ind
++] = i
&255;
230 cur_text_section
->data
[ind
++] = i
&255;
232 cur_text_section
->data
[ind
++] = i
&255;
234 cur_text_section
->data
[ind
++] = i
;
237 static uint32_t stuff_const(uint32_t op
, uint32_t c
)
240 uint32_t nc
= 0, negop
= 0;
250 case 0x1A00000: //mov
251 case 0x1E00000: //mvn
258 return (op
&0xF010F000)|((op
>>16)&0xF)|0x1E00000;
262 return (op
&0xF010F000)|((op
>>16)&0xF)|0x1A00000;
263 case 0x1C00000: //bic
268 case 0x1800000: //orr
270 return (op
&0xFFF0FFFF)|0x1E00000;
276 if(c
<256) /* catch undefined <<32 */
279 m
=(0xff>>i
)|(0xff<<(32-i
));
281 return op
|(i
<<7)|(c
<<i
)|(c
>>(32-i
));
291 void stuff_const_harder(uint32_t op
, uint32_t v
) {
297 uint32_t a
[16], nv
, no
, o2
, n2
;
300 o2
=(op
&0xfff0ffff)|((op
&0xf000)<<4);;
302 a
[i
]=(a
[i
-1]>>2)|(a
[i
-1]<<30);
304 for(j
=i
<4?i
+12:15;j
>=i
+4;j
--)
305 if((v
&(a
[i
]|a
[j
]))==v
) {
306 o(stuff_const(op
,v
&a
[i
]));
307 o(stuff_const(o2
,v
&a
[j
]));
314 for(j
=i
<4?i
+12:15;j
>=i
+4;j
--)
315 if((nv
&(a
[i
]|a
[j
]))==nv
) {
316 o(stuff_const(no
,nv
&a
[i
]));
317 o(stuff_const(n2
,nv
&a
[j
]));
322 for(k
=i
<4?i
+12:15;k
>=j
+4;k
--)
323 if((v
&(a
[i
]|a
[j
]|a
[k
]))==v
) {
324 o(stuff_const(op
,v
&a
[i
]));
325 o(stuff_const(o2
,v
&a
[j
]));
326 o(stuff_const(o2
,v
&a
[k
]));
333 for(k
=i
<4?i
+12:15;k
>=j
+4;k
--)
334 if((nv
&(a
[i
]|a
[j
]|a
[k
]))==nv
) {
335 o(stuff_const(no
,nv
&a
[i
]));
336 o(stuff_const(n2
,nv
&a
[j
]));
337 o(stuff_const(n2
,nv
&a
[k
]));
340 o(stuff_const(op
,v
&a
[0]));
341 o(stuff_const(o2
,v
&a
[4]));
342 o(stuff_const(o2
,v
&a
[8]));
343 o(stuff_const(o2
,v
&a
[12]));
347 uint32_t encbranch(int pos
, int addr
, int fail
)
351 if(addr
>=0x1000000 || addr
<-0x1000000) {
353 tcc_error("FIXME: function bigger than 32MB");
356 return 0x0A000000|(addr
&0xffffff);
359 int decbranch(int pos
)
362 x
=*(uint32_t *)(cur_text_section
->data
+ pos
);
369 /* output a symbol and patch all calls to it */
370 void gsym_addr(int t
, int a
)
375 x
=(uint32_t *)(cur_text_section
->data
+ t
);
378 *x
=0xE1A00000; // nop
381 *x
|= encbranch(lt
,a
,1);
387 static uint32_t vfpr(int r
)
389 if(r
<TREG_F0
|| r
>TREG_F7
)
390 tcc_error("compiler error! register %i is no vfp register",r
);
394 static uint32_t fpr(int r
)
396 if(r
<TREG_F0
|| r
>TREG_F3
)
397 tcc_error("compiler error! register %i is no fpa register",r
);
402 static uint32_t intr(int r
)
406 if(r
>= TREG_R0
&& r
<= TREG_R3
)
408 if (!(r
>= TREG_SP
&& r
<= TREG_LR
))
409 tcc_error("compiler error! register %i is no int register",r
);
410 return r
+ (13 - TREG_SP
);
413 static void calcaddr(uint32_t *base
, int *off
, int *sgn
, int maxoff
, unsigned shift
)
415 if(*off
>maxoff
|| *off
&((1<<shift
)-1)) {
422 y
=stuff_const(x
,*off
&~maxoff
);
428 y
=stuff_const(x
,(*off
+maxoff
)&~maxoff
);
432 *off
=((*off
+maxoff
)&~maxoff
)-*off
;
435 stuff_const_harder(x
,*off
&~maxoff
);
440 static uint32_t mapcc(int cc
)
445 return 0x30000000; /* CC/LO */
447 return 0x20000000; /* CS/HS */
449 return 0x00000000; /* EQ */
451 return 0x10000000; /* NE */
453 return 0x90000000; /* LS */
455 return 0x80000000; /* HI */
457 return 0x40000000; /* MI */
459 return 0x50000000; /* PL */
461 return 0xB0000000; /* LT */
463 return 0xA0000000; /* GE */
465 return 0xD0000000; /* LE */
467 return 0xC0000000; /* GT */
469 tcc_error("unexpected condition code");
470 return 0xE0000000; /* AL */
473 static int negcc(int cc
)
502 tcc_error("unexpected condition code");
506 /* load 'r' from value 'sv' */
507 void load(int r
, SValue
*sv
)
509 int v
, ft
, fc
, fr
, sign
;
526 uint32_t base
= 0xB; // fp
529 v1
.r
= VT_LOCAL
| VT_LVAL
;
535 } else if(v
== VT_CONST
) {
544 } else if(v
< VT_CONST
) {
551 calcaddr(&base
,&fc
,&sign
,1020,2);
553 op
=0xED100A00; /* flds */
556 if ((ft
& VT_BTYPE
) != VT_FLOAT
)
557 op
|=0x100; /* flds -> fldd */
558 o(op
|(vfpr(r
)<<12)|(fc
>>2)|(base
<<16));
563 #if LDOUBLE_SIZE == 8
564 if ((ft
& VT_BTYPE
) != VT_FLOAT
)
567 if ((ft
& VT_BTYPE
) == VT_DOUBLE
)
569 else if ((ft
& VT_BTYPE
) == VT_LDOUBLE
)
572 o(op
|(fpr(r
)<<12)|(fc
>>2)|(base
<<16));
574 } else if((ft
& (VT_BTYPE
|VT_UNSIGNED
)) == VT_BYTE
575 || (ft
& VT_BTYPE
) == VT_SHORT
) {
576 calcaddr(&base
,&fc
,&sign
,255,0);
578 if ((ft
& VT_BTYPE
) == VT_SHORT
)
580 if ((ft
& VT_UNSIGNED
) == 0)
584 o(op
|(intr(r
)<<12)|(base
<<16)|((fc
&0xf0)<<4)|(fc
&0xf));
586 calcaddr(&base
,&fc
,&sign
,4095,0);
590 if ((ft
& VT_BTYPE
) == VT_BYTE
|| (ft
& VT_BTYPE
) == VT_BOOL
)
592 o(op
|(intr(r
)<<12)|fc
|(base
<<16));
598 op
=stuff_const(0xE3A00000|(intr(r
)<<12),sv
->c
.i
);
599 if (fr
& VT_SYM
|| !op
) {
600 o(0xE59F0000|(intr(r
)<<12));
603 greloc(cur_text_section
, sv
->sym
, ind
, R_ARM_ABS32
);
608 } else if (v
== VT_LOCAL
) {
609 op
=stuff_const(0xE28B0000|(intr(r
)<<12),sv
->c
.i
);
610 if (fr
& VT_SYM
|| !op
) {
611 o(0xE59F0000|(intr(r
)<<12));
613 if(fr
& VT_SYM
) // needed ?
614 greloc(cur_text_section
, sv
->sym
, ind
, R_ARM_ABS32
);
616 o(0xE08B0000|(intr(r
)<<12)|intr(r
));
620 } else if(v
== VT_CMP
) {
621 o(mapcc(sv
->c
.i
)|0x3A00001|(intr(r
)<<12));
622 o(mapcc(negcc(sv
->c
.i
))|0x3A00000|(intr(r
)<<12));
624 } else if (v
== VT_JMP
|| v
== VT_JMPI
) {
627 o(0xE3A00000|(intr(r
)<<12)|t
);
630 o(0xE3A00000|(intr(r
)<<12)|(t
^1));
632 } else if (v
< VT_CONST
) {
635 o(0xEEB00A40|(vfpr(r
)<<12)|vfpr(v
)|T2CPR(ft
)); /* fcpyX */
637 o(0xEE008180|(fpr(r
)<<12)|fpr(v
));
640 o(0xE1A00000|(intr(r
)<<12)|intr(v
));
644 tcc_error("load unimplemented!");
647 /* store register 'r' in lvalue 'v' */
648 void store(int r
, SValue
*sv
)
651 int v
, ft
, fc
, fr
, sign
;
666 if (fr
& VT_LVAL
|| fr
== VT_LOCAL
) {
667 uint32_t base
= 0xb; /* fp */
672 } else if(v
== VT_CONST
) {
684 calcaddr(&base
,&fc
,&sign
,1020,2);
686 op
=0xED000A00; /* fsts */
689 if ((ft
& VT_BTYPE
) != VT_FLOAT
)
690 op
|=0x100; /* fsts -> fstd */
691 o(op
|(vfpr(r
)<<12)|(fc
>>2)|(base
<<16));
696 #if LDOUBLE_SIZE == 8
697 if ((ft
& VT_BTYPE
) != VT_FLOAT
)
700 if ((ft
& VT_BTYPE
) == VT_DOUBLE
)
702 if ((ft
& VT_BTYPE
) == VT_LDOUBLE
)
705 o(op
|(fpr(r
)<<12)|(fc
>>2)|(base
<<16));
708 } else if((ft
& VT_BTYPE
) == VT_SHORT
) {
709 calcaddr(&base
,&fc
,&sign
,255,0);
713 o(op
|(intr(r
)<<12)|(base
<<16)|((fc
&0xf0)<<4)|(fc
&0xf));
715 calcaddr(&base
,&fc
,&sign
,4095,0);
719 if ((ft
& VT_BTYPE
) == VT_BYTE
|| (ft
& VT_BTYPE
) == VT_BOOL
)
721 o(op
|(intr(r
)<<12)|fc
|(base
<<16));
726 tcc_error("store unimplemented");
729 static void gadd_sp(int val
)
731 stuff_const_harder(0xE28DD000,val
);
734 /* 'is_jmp' is '1' if it is a jump */
735 static void gcall_or_jmp(int is_jmp
)
739 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
) {
741 if(vtop
->r
& VT_SYM
){
742 x
=encbranch(ind
,ind
+vtop
->c
.i
,0);
744 /* relocation case */
745 greloc(cur_text_section
, vtop
->sym
, ind
, R_ARM_PC24
);
746 o(x
|(is_jmp
?0xE0000000:0xE1000000));
749 o(0xE28FE004); // add lr,pc,#4
750 o(0xE51FF004); // ldr pc,[pc,#-4]
751 greloc(cur_text_section
, vtop
->sym
, ind
, R_ARM_ABS32
);
756 o(0xE28FE004); // add lr,pc,#4
757 o(0xE51FF004); // ldr pc,[pc,#-4]
761 /* otherwise, indirect call */
764 o(0xE1A0E00F); // mov lr,pc
765 o(0xE1A0F000|intr(r
)); // mov pc,r
769 static int unalias_ldbl(int btype
)
771 #if LDOUBLE_SIZE == 8
772 if (btype
== VT_LDOUBLE
)
778 /* Return whether a structure is an homogeneous float aggregate or not.
779 The answer is true if all the elements of the structure are of the same
780 primitive float type and there is less than 4 elements.
782 type: the type corresponding to the structure to be tested */
783 static int is_hgen_float_aggr(CType
*type
)
785 if ((type
->t
& VT_BTYPE
) == VT_STRUCT
) {
787 int btype
, nb_fields
= 0;
789 ref
= type
->ref
->next
;
790 btype
= unalias_ldbl(ref
->type
.t
& VT_BTYPE
);
791 if (btype
== VT_FLOAT
|| btype
== VT_DOUBLE
) {
792 for(; ref
&& btype
== unalias_ldbl(ref
->type
.t
& VT_BTYPE
); ref
= ref
->next
, nb_fields
++);
793 return !ref
&& nb_fields
<= 4;
800 signed char avail
[3]; /* 3 holes max with only float and double alignments */
801 int first_hole
; /* first available hole */
802 int last_hole
; /* last available hole (none if equal to first_hole) */
803 int first_free_reg
; /* next free register in the sequence, hole excluded */
806 #define AVAIL_REGS_INITIALIZER (struct avail_regs) { { 0, 0, 0}, 0, 0, 0 }
808 /* Find suitable registers for a VFP Co-Processor Register Candidate (VFP CPRC
809 param) according to the rules described in the procedure call standard for
810 the ARM architecture (AAPCS). If found, the registers are assigned to this
811 VFP CPRC parameter. Registers are allocated in sequence unless a hole exists
812 and the parameter is a single float.
814 avregs: opaque structure to keep track of available VFP co-processor regs
815 align: alignment constraints for the param, as returned by type_size()
816 size: size of the parameter, as returned by type_size() */
817 int assign_vfpreg(struct avail_regs
*avregs
, int align
, int size
)
821 if (avregs
->first_free_reg
== -1)
823 if (align
>> 3) { /* double alignment */
824 first_reg
= avregs
->first_free_reg
;
825 /* alignment constraint not respected so use next reg and record hole */
827 avregs
->avail
[avregs
->last_hole
++] = first_reg
++;
828 } else { /* no special alignment (float or array of float) */
829 /* if single float and a hole is available, assign the param to it */
830 if (size
== 4 && avregs
->first_hole
!= avregs
->last_hole
)
831 return avregs
->avail
[avregs
->first_hole
++];
833 first_reg
= avregs
->first_free_reg
;
835 if (first_reg
+ size
/ 4 <= 16) {
836 avregs
->first_free_reg
= first_reg
+ size
/ 4;
839 avregs
->first_free_reg
= -1;
843 /* Returns whether all params need to be passed in core registers or not.
844 This is the case for function part of the runtime ABI. */
845 int floats_in_core_regs(SValue
*sval
)
850 switch (sval
->sym
->v
) {
851 case TOK___floatundisf
:
852 case TOK___floatundidf
:
853 case TOK___fixunssfdi
:
854 case TOK___fixunsdfdi
:
856 case TOK___fixunsxfdi
:
858 case TOK___floatdisf
:
859 case TOK___floatdidf
:
869 /* Return the number of registers needed to return the struct, or 0 if
870 returning via struct pointer. */
871 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
, int *ret_align
, int *regsize
) {
874 size
= type_size(vt
, &align
);
875 if (float_abi
== ARM_HARD_FLOAT
&& !variadic
&&
876 (is_float(vt
->t
) || is_hgen_float_aggr(vt
))) {
881 return (size
+ 7) >> 3;
882 } else if (size
<= 4) {
895 /* Parameters are classified according to how they are copied to their final
896 destination for the function call. Because the copying is performed class
897 after class according to the order in the union below, it is important that
898 some constraints about the order of the members of this union are respected:
899 - CORE_STRUCT_CLASS must come after STACK_CLASS;
900 - CORE_CLASS must come after STACK_CLASS, CORE_STRUCT_CLASS and
902 - VFP_STRUCT_CLASS must come after VFP_CLASS.
903 See the comment for the main loop in copy_params() for the reason. */
914 int start
; /* first reg or addr used depending on the class */
915 int end
; /* last reg used or next free addr depending on the class */
916 SValue
*sval
; /* pointer to SValue on the value stack */
917 struct param_plan
*prev
; /* previous element in this class */
921 struct param_plan
*pplans
; /* array of all the param plans */
922 struct param_plan
*clsplans
[NB_CLASSES
]; /* per class lists of param plans */
925 #define add_param_plan(plan,pplan,class) \
927 pplan.prev = plan->clsplans[class]; \
928 plan->pplans[plan ## _nb] = pplan; \
929 plan->clsplans[class] = &plan->pplans[plan ## _nb++]; \
932 /* Assign parameters to registers and stack with alignment according to the
933 rules in the procedure call standard for the ARM architecture (AAPCS).
934 The overall assignment is recorded in an array of per parameter structures
935 called parameter plans. The parameter plans are also further organized in a
936 number of linked lists, one per class of parameter (see the comment for the
937 definition of union reg_class).
939 nb_args: number of parameters of the function for which a call is generated
940 float_abi: float ABI in use for this function call
941 plan: the structure where the overall assignment is recorded
942 todo: a bitmap that record which core registers hold a parameter
944 Returns the amount of stack space needed for parameter passing
946 Note: this function allocated an array in plan->pplans with tcc_malloc. It
947 is the responsibility of the caller to free this array once used (ie not
948 before copy_params). */
949 static int assign_regs(int nb_args
, int float_abi
, struct plan
*plan
, int *todo
)
952 int ncrn
/* next core register number */, nsaa
/* next stacked argument address*/;
954 struct param_plan pplan
;
955 struct avail_regs avregs
= AVAIL_REGS_INITIALIZER
;
959 plan
->pplans
= tcc_malloc(nb_args
* sizeof(*plan
->pplans
));
960 memset(plan
->clsplans
, 0, sizeof(plan
->clsplans
));
961 for(i
= nb_args
; i
-- ;) {
962 int j
, start_vfpreg
= 0;
963 CType type
= vtop
[-i
].type
;
965 size
= type_size(&type
, &align
);
966 size
= (size
+ 3) & ~3;
967 align
= (align
+ 3) & ~3;
968 switch(vtop
[-i
].type
.t
& VT_BTYPE
) {
973 if (float_abi
== ARM_HARD_FLOAT
) {
974 int is_hfa
= 0; /* Homogeneous float aggregate */
976 if (is_float(vtop
[-i
].type
.t
)
977 || (is_hfa
= is_hgen_float_aggr(&vtop
[-i
].type
))) {
980 start_vfpreg
= assign_vfpreg(&avregs
, align
, size
);
981 end_vfpreg
= start_vfpreg
+ ((size
- 1) >> 2);
982 if (start_vfpreg
>= 0) {
983 pplan
= (struct param_plan
) {start_vfpreg
, end_vfpreg
, &vtop
[-i
]};
985 add_param_plan(plan
, pplan
, VFP_STRUCT_CLASS
);
987 add_param_plan(plan
, pplan
, VFP_CLASS
);
993 ncrn
= (ncrn
+ (align
-1)/4) & ~((align
/4) - 1);
994 if (ncrn
+ size
/4 <= 4 || (ncrn
< 4 && start_vfpreg
!= -1)) {
995 /* The parameter is allocated both in core register and on stack. As
996 * such, it can be of either class: it would either be the last of
997 * CORE_STRUCT_CLASS or the first of STACK_CLASS. */
998 for (j
= ncrn
; j
< 4 && j
< ncrn
+ size
/ 4; j
++)
1000 pplan
= (struct param_plan
) {ncrn
, j
, &vtop
[-i
]};
1001 add_param_plan(plan
, pplan
, CORE_STRUCT_CLASS
);
1004 nsaa
= (ncrn
- 4) * 4;
1012 int is_long
= (vtop
[-i
].type
.t
& VT_BTYPE
) == VT_LLONG
;
1015 ncrn
= (ncrn
+ 1) & -2;
1019 pplan
= (struct param_plan
) {ncrn
, ncrn
, &vtop
[-i
]};
1023 add_param_plan(plan
, pplan
, CORE_CLASS
);
1027 nsaa
= (nsaa
+ (align
- 1)) & ~(align
- 1);
1028 pplan
= (struct param_plan
) {nsaa
, nsaa
+ size
, &vtop
[-i
]};
1029 add_param_plan(plan
, pplan
, STACK_CLASS
);
1030 nsaa
+= size
; /* size already rounded up before */
1035 #undef add_param_plan
1037 /* Copy parameters to their final destination (core reg, VFP reg or stack) for
1040 nb_args: number of parameters the function take
1041 plan: the overall assignment plan for parameters
1042 todo: a bitmap indicating what core reg will hold a parameter
1044 Returns the number of SValue added by this function on the value stack */
1045 static int copy_params(int nb_args
, struct plan
*plan
, int todo
)
1047 int size
, align
, r
, i
, nb_extra_sval
= 0;
1048 struct param_plan
*pplan
;
1051 /* Several constraints require parameters to be copied in a specific order:
1052 - structures are copied to the stack before being loaded in a reg;
1053 - floats loaded to an odd numbered VFP reg are first copied to the
1054 preceding even numbered VFP reg and then moved to the next VFP reg.
1056 It is thus important that:
1057 - structures assigned to core regs must be copied after parameters
1058 assigned to the stack but before structures assigned to VFP regs because
1059 a structure can lie partly in core registers and partly on the stack;
1060 - parameters assigned to the stack and all structures be copied before
1061 parameters assigned to a core reg since copying a parameter to the stack
1062 require using a core reg;
1063 - parameters assigned to VFP regs be copied before structures assigned to
1064 VFP regs as the copy might use an even numbered VFP reg that already
1065 holds part of a structure. */
1067 for(i
= 0; i
< NB_CLASSES
; i
++) {
1068 for(pplan
= plan
->clsplans
[i
]; pplan
; pplan
= pplan
->prev
) {
1071 && (i
!= CORE_CLASS
|| pplan
->sval
->r
< VT_CONST
))
1074 vpushv(pplan
->sval
);
1075 pplan
->sval
->r
= pplan
->sval
->r2
= VT_CONST
; /* disable entry */
1078 case CORE_STRUCT_CLASS
:
1079 case VFP_STRUCT_CLASS
:
1080 if ((pplan
->sval
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
1082 size
= type_size(&pplan
->sval
->type
, &align
);
1083 /* align to stack align size */
1084 size
= (size
+ 3) & ~3;
1085 if (i
== STACK_CLASS
&& pplan
->prev
)
1086 padding
= pplan
->start
- pplan
->prev
->end
;
1087 size
+= padding
; /* Add padding if any */
1088 /* allocate the necessary size on stack */
1090 /* generate structure store */
1091 r
= get_reg(RC_INT
);
1092 o(0xE28D0000|(intr(r
)<<12)|padding
); /* add r, sp, padding */
1093 vset(&vtop
->type
, r
| VT_LVAL
, 0);
1095 vstore(); /* memcpy to current sp + potential padding */
1097 /* Homogeneous float aggregate are loaded to VFP registers
1098 immediately since there is no way of loading data in multiple
1099 non consecutive VFP registers as what is done for other
1100 structures (see the use of todo). */
1101 if (i
== VFP_STRUCT_CLASS
) {
1102 int first
= pplan
->start
, nb
= pplan
->end
- first
+ 1;
1103 /* vpop.32 {pplan->start, ..., pplan->end} */
1104 o(0xECBD0A00|(first
&1)<<22|(first
>>1)<<12|nb
);
1105 /* No need to write the register used to a SValue since VFP regs
1106 cannot be used for gcall_or_jmp */
1109 if (is_float(pplan
->sval
->type
.t
)) {
1111 r
= vfpr(gv(RC_FLOAT
)) << 12;
1112 if ((pplan
->sval
->type
.t
& VT_BTYPE
) == VT_FLOAT
)
1116 r
|= 0x101; /* vpush.32 -> vpush.64 */
1118 o(0xED2D0A01 + r
); /* vpush */
1120 r
= fpr(gv(RC_FLOAT
)) << 12;
1121 if ((pplan
->sval
->type
.t
& VT_BTYPE
) == VT_FLOAT
)
1123 else if ((pplan
->sval
->type
.t
& VT_BTYPE
) == VT_DOUBLE
)
1126 size
= LDOUBLE_SIZE
;
1133 o(0xED2D0100|r
|(size
>>2)); /* some kind of vpush for FPA */
1136 /* simple type (currently always same size) */
1137 /* XXX: implicit cast ? */
1139 if ((pplan
->sval
->type
.t
& VT_BTYPE
) == VT_LLONG
) {
1143 o(0xE52D0004|(intr(r
)<<12)); /* push r */
1147 o(0xE52D0004|(intr(r
)<<12)); /* push r */
1149 if (i
== STACK_CLASS
&& pplan
->prev
)
1150 gadd_sp(pplan
->prev
->end
- pplan
->start
); /* Add padding if any */
1155 gv(regmask(TREG_F0
+ (pplan
->start
>> 1)));
1156 if (pplan
->start
& 1) { /* Must be in upper part of double register */
1157 o(0xEEF00A40|((pplan
->start
>>1)<<12)|(pplan
->start
>>1)); /* vmov.f32 s(n+1), sn */
1158 vtop
->r
= VT_CONST
; /* avoid being saved on stack by gv for next float */
1163 if ((pplan
->sval
->type
.t
& VT_BTYPE
) == VT_LLONG
) {
1165 gv(regmask(pplan
->end
));
1166 pplan
->sval
->r2
= vtop
->r
;
1169 gv(regmask(pplan
->start
));
1170 /* Mark register as used so that gcall_or_jmp use another one
1171 (regs >=4 are free as never used to pass parameters) */
1172 pplan
->sval
->r
= vtop
->r
;
1179 /* second pass to restore registers that were saved on stack by accident.
1180 Maybe redundant after the "lvalue_save" patch in tccgen.c:gv() */
1184 /* Manually free remaining registers since next parameters are loaded
1185 * manually, without the help of gv(int). */
1189 o(0xE8BD0000|todo
); /* pop {todo} */
1190 for(pplan
= plan
->clsplans
[CORE_STRUCT_CLASS
]; pplan
; pplan
= pplan
->prev
) {
1192 pplan
->sval
->r
= pplan
->start
;
1193 /* An SValue can only pin 2 registers at best (r and r2) but a structure
1194 can occupy more than 2 registers. Thus, we need to push on the value
1195 stack some fake parameter to have on SValue for each registers used
1196 by a structure (r2 is not used). */
1197 for (r
= pplan
->start
+ 1; r
<= pplan
->end
; r
++) {
1198 if (todo
& (1 << r
)) {
1206 return nb_extra_sval
;
1209 /* Generate function call. The function address is pushed first, then
1210 all the parameters in call order. This functions pops all the
1211 parameters and the function address. */
1212 void gfunc_call(int nb_args
)
1215 int def_float_abi
= float_abi
;
1222 if (float_abi
== ARM_HARD_FLOAT
) {
1223 variadic
= (vtop
[-nb_args
].type
.ref
->f
.func_type
== FUNC_ELLIPSIS
);
1224 if (variadic
|| floats_in_core_regs(&vtop
[-nb_args
]))
1225 float_abi
= ARM_SOFTFP_FLOAT
;
1228 /* cannot let cpu flags if other instruction are generated. Also avoid leaving
1229 VT_JMP anywhere except on the top of the stack because it would complicate
1230 the code generator. */
1231 r
= vtop
->r
& VT_VALMASK
;
1232 if (r
== VT_CMP
|| (r
& ~1) == VT_JMP
)
1235 args_size
= assign_regs(nb_args
, float_abi
, &plan
, &todo
);
1238 if (args_size
& 7) { /* Stack must be 8 byte aligned at fct call for EABI */
1239 args_size
= (args_size
+ 7) & ~7;
1240 o(0xE24DD004); /* sub sp, sp, #4 */
1244 nb_args
+= copy_params(nb_args
, &plan
, todo
);
1245 tcc_free(plan
.pplans
);
1247 /* Move fct SValue on top as required by gcall_or_jmp */
1251 gadd_sp(args_size
); /* pop all parameters passed on the stack */
1252 #if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
1253 if(float_abi
== ARM_SOFTFP_FLOAT
&& is_float(vtop
->type
.ref
->type
.t
)) {
1254 if((vtop
->type
.ref
->type
.t
& VT_BTYPE
) == VT_FLOAT
) {
1255 o(0xEE000A10); /*vmov s0, r0 */
1257 o(0xEE000B10); /* vmov.32 d0[0], r0 */
1258 o(0xEE201B10); /* vmov.32 d0[1], r1 */
1262 vtop
-= nb_args
+ 1; /* Pop all params and fct address from value stack */
1263 leaffunc
= 0; /* we are calling a function, so we aren't in a leaf function */
1264 float_abi
= def_float_abi
;
1267 /* generate function prolog of type 't' */
1268 void gfunc_prolog(Sym
*func_sym
)
1270 CType
*func_type
= &func_sym
->type
;
1272 int n
, nf
, size
, align
, rs
, struct_ret
= 0;
1273 int addr
, pn
, sn
; /* pn=core, sn=stack */
1277 struct avail_regs avregs
= AVAIL_REGS_INITIALIZER
;
1280 sym
= func_type
->ref
;
1281 func_vt
= sym
->type
;
1282 func_var
= (func_type
->ref
->f
.func_type
== FUNC_ELLIPSIS
);
1285 if ((func_vt
.t
& VT_BTYPE
) == VT_STRUCT
&&
1286 !gfunc_sret(&func_vt
, func_var
, &ret_type
, &align
, &rs
))
1290 func_vc
= 12; /* Offset from fp of the place to store the result */
1292 for(sym2
= sym
->next
; sym2
&& (n
< 4 || nf
< 16); sym2
= sym2
->next
) {
1293 size
= type_size(&sym2
->type
, &align
);
1295 if (float_abi
== ARM_HARD_FLOAT
&& !func_var
&&
1296 (is_float(sym2
->type
.t
) || is_hgen_float_aggr(&sym2
->type
))) {
1297 int tmpnf
= assign_vfpreg(&avregs
, align
, size
);
1298 tmpnf
+= (size
+ 3) / 4;
1299 nf
= (tmpnf
> nf
) ? tmpnf
: nf
;
1303 n
+= (size
+ 3) / 4;
1305 o(0xE1A0C00D); /* mov ip,sp */
1314 o(0xE92D0000|((1<<n
)-1)); /* save r0-r4 on stack if needed */
1319 nf
=(nf
+1)&-2; /* nf => HARDFLOAT => EABI */
1320 o(0xED2D0A00|nf
); /* save s0-s15 on stack if needed */
1322 o(0xE92D5800); /* save fp, ip, lr */
1323 o(0xE1A0B00D); /* mov fp, sp */
1324 func_sub_sp_offset
= ind
;
1325 o(0xE1A00000); /* nop, leave space for stack adjustment in epilog */
1328 if (float_abi
== ARM_HARD_FLOAT
) {
1330 avregs
= AVAIL_REGS_INITIALIZER
;
1333 pn
= struct_ret
, sn
= 0;
1334 while ((sym
= sym
->next
)) {
1337 size
= type_size(type
, &align
);
1338 size
= (size
+ 3) >> 2;
1339 align
= (align
+ 3) & ~3;
1341 if (float_abi
== ARM_HARD_FLOAT
&& !func_var
&& (is_float(sym
->type
.t
)
1342 || is_hgen_float_aggr(&sym
->type
))) {
1343 int fpn
= assign_vfpreg(&avregs
, align
, size
<< 2);
1352 pn
= (pn
+ (align
-1)/4) & -(align
/4);
1354 addr
= (nf
+ pn
) * 4;
1361 sn
= (sn
+ (align
-1)/4) & -(align
/4);
1363 addr
= (n
+ nf
+ sn
) * 4;
1366 sym_push(sym
->v
& ~SYM_FIELD
, type
, VT_LOCAL
| VT_LVAL
,
1374 /* generate function epilog */
1375 void gfunc_epilog(void)
1379 /* Copy float return value to core register if base standard is used and
1380 float computation is made with VFP */
1381 #if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
1382 if ((float_abi
== ARM_SOFTFP_FLOAT
|| func_var
) && is_float(func_vt
.t
)) {
1383 if((func_vt
.t
& VT_BTYPE
) == VT_FLOAT
)
1384 o(0xEE100A10); /* fmrs r0, s0 */
1386 o(0xEE100B10); /* fmrdl r0, d0 */
1387 o(0xEE301B10); /* fmrdh r1, d0 */
1391 o(0xE89BA800); /* restore fp, sp, pc */
1392 diff
= (-loc
+ 3) & -4;
1395 diff
= ((diff
+ 11) & -8) - 4;
1398 x
=stuff_const(0xE24BD000, diff
); /* sub sp,fp,# */
1400 *(uint32_t *)(cur_text_section
->data
+ func_sub_sp_offset
) = x
;
1404 o(0xE59FC004); /* ldr ip,[pc+4] */
1405 o(0xE04BD00C); /* sub sp,fp,ip */
1406 o(0xE1A0F00E); /* mov pc,lr */
1408 *(uint32_t *)(cur_text_section
->data
+ func_sub_sp_offset
) = 0xE1000000|encbranch(func_sub_sp_offset
,addr
,1);
1413 ST_FUNC
void gen_fill_nops(int bytes
)
1416 tcc_error("alignment of code section not multiple of 4");
1423 /* generate a jump to a label */
1424 ST_FUNC
int gjmp(int t
)
1430 o(0xE0000000|encbranch(r
,t
,1));
1434 /* generate a jump to a fixed address */
1435 ST_FUNC
void gjmp_addr(int a
)
1440 ST_FUNC
int gjmp_cond(int op
, int t
)
1447 op
|=encbranch(r
,t
,1);
1452 ST_FUNC
int gjmp_append(int n
, int t
)
1459 p
= decbranch(lp
=p
);
1461 x
= (uint32_t *)(cur_text_section
->data
+ lp
);
1463 *x
|= encbranch(lp
,t
,1);
1469 /* generate an integer binary operation */
1470 void gen_opi(int op
)
1473 uint32_t opc
= 0, r
, fr
;
1474 unsigned short retreg
= REG_IRET
;
1482 case TOK_ADDC1
: /* add with carry generation */
1490 case TOK_SUBC1
: /* sub with carry generation */
1494 case TOK_ADDC2
: /* add with carry use */
1498 case TOK_SUBC2
: /* sub with carry use */
1515 gv2(RC_INT
, RC_INT
);
1519 o(0xE0000090|(intr(r
)<<16)|(intr(r
)<<8)|intr(fr
));
1544 func
=TOK___aeabi_idivmod
;
1553 func
=TOK___aeabi_uidivmod
;
1561 gv2(RC_INT
, RC_INT
);
1562 r
=intr(vtop
[-1].r2
=get_reg(RC_INT
));
1564 vtop
[-1].r
=get_reg_ex(RC_INT
,regmask(c
));
1566 o(0xE0800090|(r
<<16)|(intr(vtop
->r
)<<12)|(intr(c
)<<8)|intr(vtop
[1].r
));
1575 if((vtop
[-1].r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
) {
1576 if(opc
== 4 || opc
== 5 || opc
== 0xc) {
1578 opc
|=2; // sub -> rsb
1581 if ((vtop
->r
& VT_VALMASK
) == VT_CMP
||
1582 (vtop
->r
& (VT_VALMASK
& ~1)) == VT_JMP
)
1587 opc
=0xE0000000|(opc
<<20)|(c
<<16);
1588 if((vtop
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
) {
1590 x
=stuff_const(opc
|0x2000000,vtop
->c
.i
);
1592 r
=intr(vtop
[-1].r
=get_reg_ex(RC_INT
,regmask(vtop
[-1].r
)));
1597 fr
=intr(gv(RC_INT
));
1598 r
=intr(vtop
[-1].r
=get_reg_ex(RC_INT
,two2mask(vtop
->r
,vtop
[-1].r
)));
1602 if (op
>= TOK_ULT
&& op
<= TOK_GT
)
1606 opc
=0xE1A00000|(opc
<<5);
1607 if ((vtop
->r
& VT_VALMASK
) == VT_CMP
||
1608 (vtop
->r
& (VT_VALMASK
& ~1)) == VT_JMP
)
1614 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
) {
1615 fr
=intr(vtop
[-1].r
=get_reg_ex(RC_INT
,regmask(vtop
[-1].r
)));
1616 c
= vtop
->c
.i
& 0x1f;
1617 o(opc
|(c
<<7)|(fr
<<12));
1619 fr
=intr(gv(RC_INT
));
1620 c
=intr(vtop
[-1].r
=get_reg_ex(RC_INT
,two2mask(vtop
->r
,vtop
[-1].r
)));
1621 o(opc
|(c
<<12)|(fr
<<8)|0x10);
1626 vpush_global_sym(&func_old_type
, func
);
1633 tcc_error("gen_opi %i unimplemented!",op
);
1638 static int is_zero(int i
)
1640 if((vtop
[i
].r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) != VT_CONST
)
1642 if (vtop
[i
].type
.t
== VT_FLOAT
)
1643 return (vtop
[i
].c
.f
== 0.f
);
1644 else if (vtop
[i
].type
.t
== VT_DOUBLE
)
1645 return (vtop
[i
].c
.d
== 0.0);
1646 return (vtop
[i
].c
.ld
== 0.l
);
1649 /* generate a floating point operation 'v = t1 op t2' instruction. The
1650 * two operands are guaranteed to have the same floating point type */
1651 void gen_opf(int op
)
1655 x
=0xEE000A00|T2CPR(vtop
->type
.t
);
1673 x
|=0x810000; /* fsubX -> fnegX */
1686 if(op
< TOK_ULT
|| op
> TOK_GT
) {
1687 tcc_error("unknown fp op %x!",op
);
1693 case TOK_LT
: op
=TOK_GT
; break;
1694 case TOK_GE
: op
=TOK_ULE
; break;
1695 case TOK_LE
: op
=TOK_GE
; break;
1696 case TOK_GT
: op
=TOK_ULT
; break;
1699 x
|=0xB40040; /* fcmpX */
1700 if(op
!=TOK_EQ
&& op
!=TOK_NE
)
1701 x
|=0x80; /* fcmpX -> fcmpeX */
1704 o(x
|0x10000|(vfpr(gv(RC_FLOAT
))<<12)); /* fcmp(e)X -> fcmp(e)zX */
1706 x
|=vfpr(gv(RC_FLOAT
));
1708 o(x
|(vfpr(gv(RC_FLOAT
))<<12));
1711 o(0xEEF1FA10); /* fmstat */
1714 case TOK_LE
: op
=TOK_ULE
; break;
1715 case TOK_LT
: op
=TOK_ULT
; break;
1716 case TOK_UGE
: op
=TOK_GE
; break;
1717 case TOK_UGT
: op
=TOK_GT
; break;
1732 vtop
->r
=get_reg_ex(RC_FLOAT
,r
);
1735 o(x
|(vfpr(vtop
->r
)<<12));
1739 static uint32_t is_fconst()
1743 if((vtop
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) != VT_CONST
)
1745 if (vtop
->type
.t
== VT_FLOAT
)
1747 else if (vtop
->type
.t
== VT_DOUBLE
)
1777 /* generate a floating point operation 'v = t1 op t2' instruction. The
1778 two operands are guaranteed to have the same floating point type */
1779 void gen_opf(int op
)
1781 uint32_t x
, r
, r2
, c1
, c2
;
1782 //fputs("gen_opf\n",stderr);
1788 #if LDOUBLE_SIZE == 8
1789 if ((vtop
->type
.t
& VT_BTYPE
) != VT_FLOAT
)
1792 if ((vtop
->type
.t
& VT_BTYPE
) == VT_DOUBLE
)
1794 else if ((vtop
->type
.t
& VT_BTYPE
) == VT_LDOUBLE
)
1805 r
=fpr(gv(RC_FLOAT
));
1812 r2
=fpr(gv(RC_FLOAT
));
1821 r
=fpr(gv(RC_FLOAT
));
1823 } else if(c1
&& c1
<=0xf) {
1826 r
=fpr(gv(RC_FLOAT
));
1831 r
=fpr(gv(RC_FLOAT
));
1833 r2
=fpr(gv(RC_FLOAT
));
1842 r
=fpr(gv(RC_FLOAT
));
1847 r2
=fpr(gv(RC_FLOAT
));
1855 r
=fpr(gv(RC_FLOAT
));
1857 } else if(c1
&& c1
<=0xf) {
1860 r
=fpr(gv(RC_FLOAT
));
1865 r
=fpr(gv(RC_FLOAT
));
1867 r2
=fpr(gv(RC_FLOAT
));
1871 if(op
>= TOK_ULT
&& op
<= TOK_GT
) {
1872 x
|=0xd0f110; // cmfe
1873 /* bug (intention?) in Linux FPU emulator
1874 doesn't set carry if equal */
1880 tcc_error("unsigned comparison on floats?");
1886 op
=TOK_ULE
; /* correct in unordered case only if AC bit in FPSR set */
1890 x
&=~0x400000; // cmfe -> cmf
1912 r
=fpr(gv(RC_FLOAT
));
1919 r2
=fpr(gv(RC_FLOAT
));
1925 tcc_error("unknown fp op %x!",op
);
1929 if(vtop
[-1].r
== VT_CMP
)
1935 vtop
[-1].r
=get_reg_ex(RC_FLOAT
,two2mask(vtop
[-1].r
,c1
));
1939 o(x
|(r
<<16)|(c1
<<12)|r2
);
1943 /* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
1944 and 'long long' cases. */
1945 ST_FUNC
void gen_cvt_itof(int t
)
1949 bt
=vtop
->type
.t
& VT_BTYPE
;
1950 if(bt
== VT_INT
|| bt
== VT_SHORT
|| bt
== VT_BYTE
) {
1956 r2
=vfpr(vtop
->r
=get_reg(RC_FLOAT
));
1957 o(0xEE000A10|(r
<<12)|(r2
<<16)); /* fmsr */
1959 if(!(vtop
->type
.t
& VT_UNSIGNED
))
1960 r2
|=0x80; /* fuitoX -> fsituX */
1961 o(0xEEB80A40|r2
|T2CPR(t
)); /* fYitoX*/
1963 r2
=fpr(vtop
->r
=get_reg(RC_FLOAT
));
1964 if((t
& VT_BTYPE
) != VT_FLOAT
)
1965 dsize
=0x80; /* flts -> fltd */
1966 o(0xEE000110|dsize
|(r2
<<16)|(r
<<12)); /* flts */
1967 if((vtop
->type
.t
& (VT_UNSIGNED
|VT_BTYPE
)) == (VT_UNSIGNED
|VT_INT
)) {
1969 o(0xE3500000|(r
<<12)); /* cmp */
1970 r
=fpr(get_reg(RC_FLOAT
));
1971 if(last_itod_magic
) {
1972 off
=ind
+8-last_itod_magic
;
1977 o(0xBD1F0100|(r
<<12)|off
); /* ldflts */
1979 o(0xEA000000); /* b */
1980 last_itod_magic
=ind
;
1981 o(0x4F800000); /* 4294967296.0f */
1983 o(0xBE000100|dsize
|(r2
<<16)|(r2
<<12)|r
); /* adflt */
1987 } else if(bt
== VT_LLONG
) {
1989 CType
*func_type
= 0;
1990 if((t
& VT_BTYPE
) == VT_FLOAT
) {
1991 func_type
= &func_float_type
;
1992 if(vtop
->type
.t
& VT_UNSIGNED
)
1993 func
=TOK___floatundisf
;
1995 func
=TOK___floatdisf
;
1996 #if LDOUBLE_SIZE != 8
1997 } else if((t
& VT_BTYPE
) == VT_LDOUBLE
) {
1998 func_type
= &func_ldouble_type
;
1999 if(vtop
->type
.t
& VT_UNSIGNED
)
2000 func
=TOK___floatundixf
;
2002 func
=TOK___floatdixf
;
2003 } else if((t
& VT_BTYPE
) == VT_DOUBLE
) {
2005 } else if((t
& VT_BTYPE
) == VT_DOUBLE
|| (t
& VT_BTYPE
) == VT_LDOUBLE
) {
2007 func_type
= &func_double_type
;
2008 if(vtop
->type
.t
& VT_UNSIGNED
)
2009 func
=TOK___floatundidf
;
2011 func
=TOK___floatdidf
;
2014 vpush_global_sym(func_type
, func
);
2022 tcc_error("unimplemented gen_cvt_itof %x!",vtop
->type
.t
);
2025 /* convert fp to int 't' type */
2026 void gen_cvt_ftoi(int t
)
2032 r2
=vtop
->type
.t
& VT_BTYPE
;
2035 r
=vfpr(gv(RC_FLOAT
));
2037 o(0xEEBC0AC0|(r
<<12)|r
|T2CPR(r2
)|u
); /* ftoXizY */
2038 r2
=intr(vtop
->r
=get_reg(RC_INT
));
2039 o(0xEE100A10|(r
<<16)|(r2
<<12));
2044 func
=TOK___fixunssfsi
;
2045 #if LDOUBLE_SIZE != 8
2046 else if(r2
== VT_LDOUBLE
)
2047 func
=TOK___fixunsxfsi
;
2048 else if(r2
== VT_DOUBLE
)
2050 else if(r2
== VT_LDOUBLE
|| r2
== VT_DOUBLE
)
2052 func
=TOK___fixunsdfsi
;
2054 r
=fpr(gv(RC_FLOAT
));
2055 r2
=intr(vtop
->r
=get_reg(RC_INT
));
2056 o(0xEE100170|(r2
<<12)|r
);
2060 } else if(t
== VT_LLONG
) { // unsigned handled in gen_cvt_ftoi1
2063 #if LDOUBLE_SIZE != 8
2064 else if(r2
== VT_LDOUBLE
)
2066 else if(r2
== VT_DOUBLE
)
2068 else if(r2
== VT_LDOUBLE
|| r2
== VT_DOUBLE
)
2073 vpush_global_sym(&func_old_type
, func
);
2078 vtop
->r2
= REG_IRE2
;
2082 tcc_error("unimplemented gen_cvt_ftoi!");
2085 /* convert from one floating point type to another */
2086 void gen_cvt_ftof(int t
)
2089 if(((vtop
->type
.t
& VT_BTYPE
) == VT_FLOAT
) != ((t
& VT_BTYPE
) == VT_FLOAT
)) {
2090 uint32_t r
= vfpr(gv(RC_FLOAT
));
2091 o(0xEEB70AC0|(r
<<12)|r
|T2CPR(vtop
->type
.t
));
2094 /* all we have to do on i386 and FPA ARM is to put the float in a register */
2099 /* computed goto support */
2106 /* Save the stack pointer onto the stack and return the location of its address */
2107 ST_FUNC
void gen_vla_sp_save(int addr
) {
2110 v
.r
= VT_LOCAL
| VT_LVAL
;
2115 /* Restore the SP from a location on the stack */
2116 ST_FUNC
void gen_vla_sp_restore(int addr
) {
2119 v
.r
= VT_LOCAL
| VT_LVAL
;
2124 /* Subtract from the stack pointer, and push the resulting value onto the stack */
2125 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
) {
2126 int r
= intr(gv(RC_INT
));
2127 o(0xE04D0000|(r
<<12)|r
); /* sub r, sp, r */
2135 if (align
& (align
- 1))
2136 tcc_error("alignment is not a power of 2: %i", align
);
2137 o(stuff_const(0xE3C0D000|(r
<<16), align
- 1)); /* bic sp, r, #align-1 */
2141 /* end of ARM code generator */
2142 /*************************************************************/
2144 /*************************************************************/