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[tinycc.git] / i386-asm.c
blob43c2b077ccb641a61d94531fef5bfad2b2c9769a
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #define MAX_OPERANDS 3
22
23 typedef struct ASMInstr {
24 uint16_t sym;
25 uint16_t opcode;
26 uint16_t instr_type;
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
41
42 /* in order to compress the operand type, we use specific operands and
43 we or only with EA */
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_SEG 8
53 #define OPT_ST 9
54 #define OPT_IM8 10
55 #define OPT_IM8S 11
56 #define OPT_IM16 12
57 #define OPT_IM32 13
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
64
65 /* composite types */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
71
72 /* can be ored with any OPT_xxx */
73 #define OPT_EA 0x80
74
75 uint8_t nb_ops;
76 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
77 } ASMInstr;
78
79 typedef struct Operand {
80 uint32_t type;
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
101
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg; /* register, -1 if none */
106 int8_t reg2; /* second register, -1 if none */
107 uint8_t shift;
108 ExprValue e;
109 } Operand;
110
111 static const uint8_t reg_to_size[5] = {
112 [OP_REG8] = 0,
113 [OP_REG16] = 1,
114 [OP_REG32] = 2,
115 };
116
117 #define WORD_PREFIX_OPCODE 0x66
118
119 #define NB_TEST_OPCODES 30
120
121 static const uint8_t test_bits[NB_TEST_OPCODES] = {
122 0x00, /* o */
123 0x01, /* no */
124 0x02, /* b */
125 0x02, /* c */
126 0x02, /* nae */
127 0x03, /* nb */
128 0x03, /* nc */
129 0x03, /* ae */
130 0x04, /* e */
131 0x04, /* z */
132 0x05, /* ne */
133 0x05, /* nz */
134 0x06, /* be */
135 0x06, /* na */
136 0x07, /* nbe */
137 0x07, /* a */
138 0x08, /* s */
139 0x09, /* ns */
140 0x0a, /* p */
141 0x0a, /* pe */
142 0x0b, /* np */
143 0x0b, /* po */
144 0x0c, /* l */
145 0x0c, /* nge */
146 0x0d, /* nl */
147 0x0d, /* ge */
148 0x0e, /* le */
149 0x0e, /* ng */
150 0x0f, /* nle */
151 0x0f, /* g */
152 };
153
154 static const ASMInstr asm_instrs[] = {
155 #define ALT(x) x
156 #define DEF_ASM_OP0(name, opcode)
157 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
158 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
159 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
160 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
161 #include "i386-asm.h"
162
163 /* last operation */
164 { 0, },
165 };
166
167 static const uint16_t op0_codes[] = {
168 #define ALT(x)
169 #define DEF_ASM_OP0(x, opcode) opcode,
170 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
171 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
172 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
173 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
174 #include "i386-asm.h"
175 };
176
177 static inline int get_reg_shift(TCCState *s1)
178 {
179 int shift, v;
180
181 v = asm_int_expr(s1);
182 switch(v) {
183 case 1:
184 shift = 0;
185 break;
186 case 2:
187 shift = 1;
188 break;
189 case 4:
190 shift = 2;
191 break;
192 case 8:
193 shift = 3;
194 break;
195 default:
196 expect("1, 2, 4 or 8 constant");
197 shift = 0;
198 break;
199 }
200 return shift;
201 }
202
203 static int asm_parse_reg(void)
204 {
205 int reg;
206 if (tok != '%')
207 goto error_32;
208 next();
209 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
210 reg = tok - TOK_ASM_eax;
211 next();
212 return reg;
213 } else {
214 error_32:
215 expect("32 bit register");
216 return 0;
217 }
218 }
219
220 static void parse_operand(TCCState *s1, Operand *op)
221 {
222 ExprValue e;
223 int reg, indir;
224 const char *p;
225
226 indir = 0;
227 if (tok == '*') {
228 next();
229 indir = OP_INDIR;
230 }
231
232 if (tok == '%') {
233 next();
234 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
235 reg = tok - TOK_ASM_al;
236 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
237 op->reg = reg & 7;
238 if ((op->type & OP_REG) && op->reg == TREG_EAX)
239 op->type |= OP_EAX;
240 else if (op->type == OP_REG8 && op->reg == TREG_ECX)
241 op->type |= OP_CL;
242 else if (op->type == OP_REG16 && op->reg == TREG_EDX)
243 op->type |= OP_DX;
244 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
245 op->type = OP_DB;
246 op->reg = tok - TOK_ASM_dr0;
247 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
248 op->type = OP_SEG;
249 op->reg = tok - TOK_ASM_es;
250 } else if (tok == TOK_ASM_st) {
251 op->type = OP_ST;
252 op->reg = 0;
253 next();
254 if (tok == '(') {
255 next();
256 if (tok != TOK_PPNUM)
257 goto reg_error;
258 p = tokc.cstr->data;
259 reg = p[0] - '0';
260 if ((unsigned)reg >= 8 || p[1] != '\0')
261 goto reg_error;
262 op->reg = reg;
263 next();
264 skip(')');
265 }
266 if (op->reg == 0)
267 op->type |= OP_ST0;
268 goto no_skip;
269 } else {
270 reg_error:
271 error("unknown register");
272 }
273 next();
274 no_skip: ;
275 } else if (tok == '$') {
276 /* constant value */
277 next();
278 asm_expr(s1, &e);
279 op->type = OP_IM32;
280 op->e.v = e.v;
281 op->e.sym = e.sym;
282 if (!op->e.sym) {
283 if (op->e.v == (uint8_t)op->e.v)
284 op->type |= OP_IM8;
285 if (op->e.v == (int8_t)op->e.v)
286 op->type |= OP_IM8S;
287 if (op->e.v == (uint16_t)op->e.v)
288 op->type |= OP_IM16;
289 }
290 } else {
291 /* address(reg,reg2,shift) with all variants */
292 op->type = OP_EA;
293 op->reg = -1;
294 op->reg2 = -1;
295 op->shift = 0;
296 if (tok != '(') {
297 asm_expr(s1, &e);
298 op->e.v = e.v;
299 op->e.sym = e.sym;
300 } else {
301 op->e.v = 0;
302 op->e.sym = NULL;
303 }
304 if (tok == '(') {
305 next();
306 if (tok != ',') {
307 op->reg = asm_parse_reg();
308 }
309 if (tok == ',') {
310 next();
311 if (tok != ',') {
312 op->reg2 = asm_parse_reg();
313 }
314 skip(',');
315 op->shift = get_reg_shift(s1);
316 }
317 skip(')');
318 }
319 if (op->reg == -1 && op->reg2 == -1)
320 op->type |= OP_ADDR;
321 }
322 op->type |= indir;
323 }
324
325 /* XXX: unify with C code output ? */
326 static void gen_expr32(ExprValue *pe)
327 {
328 if (pe->sym)
329 greloc(cur_text_section, pe->sym, ind, R_386_32);
330 gen_le32(pe->v);
331 }
332
333 /* XXX: unify with C code output ? */
334 static void gen_disp32(ExprValue *pe)
335 {
336 Sym *sym;
337 sym = pe->sym;
338 if (sym) {
339 if (sym->r == cur_text_section->sh_num) {
340 /* same section: we can output an absolute value. Note
341 that the TCC compiler behaves differently here because
342 it always outputs a relocation to ease (future) code
343 elimination in the linker */
344 gen_le32(pe->v + (long)sym->next - ind - 4);
345 } else {
346 greloc(cur_text_section, sym, ind, R_386_PC32);
347 gen_le32(pe->v - 4);
348 }
349 } else {
350 /* put an empty PC32 relocation */
351 put_elf_reloc(symtab_section, cur_text_section,
352 ind, R_386_PC32, 0);
353 gen_le32(pe->v - 4);
354 }
355 }
356
357
358 static void gen_le16(int v)
359 {
360 g(v);
361 g(v >> 8);
362 }
363
364 /* generate the modrm operand */
365 static inline void asm_modrm(int reg, Operand *op)
366 {
367 int mod, reg1, reg2;
368
369 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
370 g(0xc0 + (reg << 3) + op->reg);
371 } else if (op->reg == -1 && op->reg2 == -1) {
372 /* displacement only */
373 g(0x05 + (reg << 3));
374 gen_expr32(&op->e);
375 } else {
376 /* fist compute displacement encoding */
377 if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
378 mod = 0x00;
379 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
380 mod = 0x40;
381 } else {
382 mod = 0x80;
383 }
384 /* compute if sib byte needed */
385 reg1 = op->reg;
386 if (op->reg2 != -1)
387 reg1 = 4;
388 g(mod + (reg << 3) + reg1);
389 if (reg1 == 4) {
390 /* add sib byte */
391 reg2 = op->reg2;
392 if (reg2 == -1)
393 reg2 = 4; /* indicate no index */
394 g((op->shift << 6) + (reg2 << 3) + op->reg);
395 }
396
397 /* add offset */
398 if (mod == 0x40) {
399 g(op->e.v);
400 } else if (mod == 0x80) {
401 gen_expr32(&op->e);
402 }
403 }
404 }
405
406 static void asm_opcode(TCCState *s1, int opcode)
407 {
408 const ASMInstr *pa;
409 int i, modrm_index, reg, v, op1, is_short_jmp;
410 int nb_ops, s, ss;
411 Operand ops[MAX_OPERANDS], *pop;
412 int op_type[3]; /* decoded op type */
413
414 /* get operands */
415 pop = ops;
416 nb_ops = 0;
417 for(;;) {
418 if (tok == ';' || tok == TOK_LINEFEED)
419 break;
420 if (nb_ops >= MAX_OPERANDS) {
421 error("incorrect number of operands");
422 }
423 parse_operand(s1, pop);
424 pop++;
425 nb_ops++;
426 if (tok != ',')
427 break;
428 next();
429 }
430
431 is_short_jmp = 0;
432 s = 0; /* avoid warning */
433
434 /* optimize matching by using a lookup table (no hashing is needed
435 !) */
436 for(pa = asm_instrs; pa->sym != 0; pa++) {
437 s = 0;
438 if (pa->instr_type & OPC_FARITH) {
439 v = opcode - pa->sym;
440 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
441 continue;
442 } else if (pa->instr_type & OPC_ARITH) {
443 if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
444 continue;
445 goto compute_size;
446 } else if (pa->instr_type & OPC_SHIFT) {
447 if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
448 continue;
449 goto compute_size;
450 } else if (pa->instr_type & OPC_TEST) {
451 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
452 continue;
453 } else if (pa->instr_type & OPC_B) {
454 if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
455 continue;
456 compute_size:
457 s = (opcode - pa->sym) & 3;
458 } else if (pa->instr_type & OPC_WL) {
459 if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
460 continue;
461 s = opcode - pa->sym + 1;
462 } else {
463 if (pa->sym != opcode)
464 continue;
465 }
466 if (pa->nb_ops != nb_ops)
467 continue;
468 /* now decode and check each operand */
469 for(i = 0; i < nb_ops; i++) {
470 int op1, op2;
471 op1 = pa->op_type[i];
472 op2 = op1 & 0x1f;
473 switch(op2) {
474 case OPT_IM:
475 v = OP_IM8 | OP_IM16 | OP_IM32;
476 break;
477 case OPT_REG:
478 v = OP_REG8 | OP_REG16 | OP_REG32;
479 break;
480 case OPT_REGW:
481 v = OP_REG16 | OP_REG32;
482 break;
483 case OPT_IMW:
484 v = OP_IM16 | OP_IM32;
485 break;
486 default:
487 v = 1 << op2;
488 break;
489 }
490 if (op1 & OPT_EA)
491 v |= OP_EA;
492 op_type[i] = v;
493 if ((ops[i].type & v) == 0)
494 goto next;
495 }
496 /* all is matching ! */
497 break;
498 next: ;
499 }
500 if (pa->sym == 0) {
501 if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
502 int b;
503 b = op0_codes[opcode - TOK_ASM_pusha];
504 if (b & 0xff00)
505 g(b >> 8);
506 g(b);
507 return;
508 } else {
509 error("unknown opcode '%s'",
510 get_tok_str(opcode, NULL));
511 }
512 }
513 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
514 if (s == 3) {
515 for(i = 0; s == 3 && i < nb_ops; i++) {
516 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
517 s = reg_to_size[ops[i].type & OP_REG];
518 }
519 if (s == 3) {
520 error("cannot infer opcode suffix");
521 }
522 }
523
524 /* generate data16 prefix if needed */
525 ss = s;
526 if (s == 1 || (pa->instr_type & OPC_D16))
527 g(WORD_PREFIX_OPCODE);
528 else if (s == 2)
529 s = 1;
530 /* now generates the operation */
531 if (pa->instr_type & OPC_FWAIT)
532 g(0x9b);
533
534 v = pa->opcode;
535 if (v == 0x69 || v == 0x69) {
536 /* kludge for imul $im, %reg */
537 nb_ops = 3;
538 ops[2] = ops[1];
539 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
540 v--; /* int $3 case */
541 nb_ops = 0;
542 } else if ((v == 0x06 || v == 0x07)) {
543 if (ops[0].reg >= 4) {
544 /* push/pop %fs or %gs */
545 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
546 } else {
547 v += ops[0].reg << 3;
548 }
549 nb_ops = 0;
550 } else if (v <= 0x05) {
551 /* arith case */
552 v += ((opcode - TOK_ASM_addb) >> 2) << 3;
553 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
554 /* fpu arith case */
555 v += ((opcode - pa->sym) / 6) << 3;
556 }
557 if (pa->instr_type & OPC_REG) {
558 for(i = 0; i < nb_ops; i++) {
559 if (op_type[i] & (OP_REG | OP_ST)) {
560 v += ops[i].reg;
561 break;
562 }
563 }
564 /* mov $im, %reg case */
565 if (pa->opcode == 0xb0 && s >= 1)
566 v += 7;
567 }
568 if (pa->instr_type & OPC_B)
569 v += s;
570 if (pa->instr_type & OPC_TEST)
571 v += test_bits[opcode - pa->sym];
572 if (pa->instr_type & OPC_SHORTJMP) {
573 Sym *sym;
574 int jmp_disp;
575
576 /* see if we can really generate the jump with a byte offset */
577 sym = ops[0].e.sym;
578 if (!sym)
579 goto no_short_jump;
580 if (sym->r != cur_text_section->sh_num)
581 goto no_short_jump;
582 jmp_disp = ops[0].e.v + (long)sym->next - ind - 2;
583 if (jmp_disp == (int8_t)jmp_disp) {
584 /* OK to generate jump */
585 is_short_jmp = 1;
586 ops[0].e.v = jmp_disp;
587 } else {
588 no_short_jump:
589 if (pa->instr_type & OPC_JMP) {
590 /* long jump will be allowed. need to modify the
591 opcode slightly */
592 if (v == 0xeb)
593 v = 0xe9;
594 else
595 v += 0x0f10;
596 } else {
597 error("invalid displacement");
598 }
599 }
600 }
601 op1 = v >> 8;
602 if (op1)
603 g(op1);
604 g(v);
605
606 /* search which operand will used for modrm */
607 modrm_index = 0;
608 if (pa->instr_type & OPC_SHIFT) {
609 reg = (opcode - pa->sym) >> 2;
610 if (reg == 6)
611 reg = 7;
612 } else if (pa->instr_type & OPC_ARITH) {
613 reg = (opcode - pa->sym) >> 2;
614 } else if (pa->instr_type & OPC_FARITH) {
615 reg = (opcode - pa->sym) / 6;
616 } else {
617 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
618 }
619 if (pa->instr_type & OPC_MODRM) {
620 /* first look for an ea operand */
621 for(i = 0;i < nb_ops; i++) {
622 if (op_type[i] & OP_EA)
623 goto modrm_found;
624 }
625 /* then if not found, a register or indirection (shift instructions) */
626 for(i = 0;i < nb_ops; i++) {
627 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
628 goto modrm_found;
629 }
630 #ifdef ASM_DEBUG
631 error("bad op table");
632 #endif
633 modrm_found:
634 modrm_index = i;
635 /* if a register is used in another operand then it is
636 used instead of group */
637 for(i = 0;i < nb_ops; i++) {
638 v = op_type[i];
639 if (i != modrm_index &&
640 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
641 reg = ops[i].reg;
642 break;
643 }
644 }
645
646 asm_modrm(reg, &ops[modrm_index]);
647 }
648
649 /* emit constants */
650 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
651 /* ljmp or lcall kludge */
652 gen_expr32(&ops[1].e);
653 if (ops[0].e.sym)
654 error("cannot relocate");
655 gen_le16(ops[0].e.v);
656 } else {
657 for(i = 0;i < nb_ops; i++) {
658 v = op_type[i];
659 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
660 /* if multiple sizes are given it means we must look
661 at the op size */
662 if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
663 v == (OP_IM16 | OP_IM32)) {
664 if (ss == 0)
665 v = OP_IM8;
666 else if (ss == 1)
667 v = OP_IM16;
668 else
669 v = OP_IM32;
670 }
671 if (v & (OP_IM8 | OP_IM8S)) {
672 if (ops[i].e.sym)
673 goto error_relocate;
674 g(ops[i].e.v);
675 } else if (v & OP_IM16) {
676 if (ops[i].e.sym) {
677 error_relocate:
678 error("cannot relocate");
679 }
680 gen_le16(ops[i].e.v);
681 } else {
682 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
683 if (is_short_jmp)
684 g(ops[i].e.v);
685 else
686 gen_disp32(&ops[i].e);
687 } else {
688 gen_expr32(&ops[i].e);
689 }
690 }
691 }
692 }
693 }
694 }
695
696 #define NB_SAVED_REGS 3
697 #define NB_ASM_REGS 8
698
699 /* return the constraint priority (we allocate first the lowest
700 numbered constraints) */
701 static inline int constraint_priority(const char *str)
702 {
703 int priority, c, pr;
704
705 /* we take the lowest priority */
706 priority = 0;
707 for(;;) {
708 c = *str;
709 if (c == '\0')
710 break;
711 str++;
712 switch(c) {
713 case 'A':
714 pr = 0;
715 break;
716 case 'a':
717 case 'b':
718 case 'c':
719 case 'd':
720 case 'S':
721 case 'D':
722 pr = 1;
723 break;
724 case 'q':
725 pr = 2;
726 break;
727 case 'r':
728 pr = 3;
729 break;
730 case 'N':
731 case 'M':
732 case 'I':
733 case 'i':
734 case 'm':
735 case 'g':
736 pr = 4;
737 break;
738 default:
739 error("unknown constraint '%c'", c);
740 pr = 0;
741 }
742 if (pr > priority)
743 priority = pr;
744 }
745 return priority;
746 }
747
748 static const char *skip_constraint_modifiers(const char *p)
749 {
750 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
751 p++;
752 return p;
753 }
754
755 static void asm_compute_constraints(uint8_t *regs_allocated,
756 ASMOperand *operands,
757 int nb_operands1, int nb_outputs,
758 int is_output,
759 uint8_t *input_regs_allocated)
760 {
761 ASMOperand *op;
762 int sorted_op[MAX_ASM_OPERANDS];
763 int i, j, k, p1, p2, tmp, reg, c, base, nb_operands;
764 const char *str;
765
766 if (is_output) {
767 base = 0;
768 nb_operands = nb_outputs;
769 } else {
770 base = nb_outputs;
771 nb_operands = nb_operands1 - nb_outputs;
772 }
773
774 /* compute constraint priority and evaluate references to output
775 constraints if input constraints */
776 for(i=0;i<nb_operands;i++) {
777 j = base + i;
778 op = &operands[j];
779 str = op->constraint;
780 op->ref_index = -1;
781 op->reg = -1;
782 str = skip_constraint_modifiers(str);
783 if (!is_output && (isnum(*str) || *str == '[')) {
784 /* this is a reference to another constraint */
785 k = find_constraint(operands, nb_operands1, str, NULL);
786 if ((unsigned)k >= j)
787 error("invalid reference in constraint %d ('%s')",
788 j, str);
789 op->ref_index = k;
790 str = operands[k].constraint;
791 str = skip_constraint_modifiers(str);
792 }
793 op->priority = constraint_priority(str);
794 }
795
796 /* sort operands according to their priority */
797 for(i=0;i<nb_operands;i++)
798 sorted_op[i] = base + i;
799 for(i=0;i<nb_operands - 1;i++) {
800 for(j=i+1;j<nb_operands;j++) {
801 p1 = operands[sorted_op[i]].priority;
802 p2 = operands[sorted_op[j]].priority;
803 if (p2 < p1) {
804 tmp = sorted_op[i];
805 sorted_op[i] = sorted_op[j];
806 sorted_op[j] = tmp;
807 }
808 }
809 }
810
811 memset(regs_allocated, 0, NB_ASM_REGS);
812 regs_allocated[4] = 1; /* esp cannot be used */
813 regs_allocated[5] = 1; /* ebp cannot be used yet */
814
815 /* allocate registers and generate corresponding asm moves */
816 for(i=0;i<nb_operands;i++) {
817 j = sorted_op[i];
818 op = &operands[j];
819 str = op->constraint;
820
821 if (op->ref_index >= 0) {
822 str = operands[op->ref_index].constraint;
823 }
824
825 str = skip_constraint_modifiers(str);
826 try_next:
827 c = *str++;
828 switch(c) {
829 case 'A':
830 /* allocate both eax and edx */
831 if (regs_allocated[TREG_EAX] || regs_allocated[TREG_EDX])
832 goto try_next;
833 op->is_llong = 1;
834 op->reg = TREG_EAX;
835 regs_allocated[TREG_EAX] = 1;
836 regs_allocated[TREG_EDX] = 1;
837 break;
838 case 'a':
839 reg = TREG_EAX;
840 goto alloc_reg;
841 case 'b':
842 reg = 3;
843 goto alloc_reg;
844 case 'c':
845 reg = TREG_ECX;
846 goto alloc_reg;
847 case 'd':
848 reg = TREG_EDX;
849 goto alloc_reg;
850 case 'S':
851 reg = 6;
852 goto alloc_reg;
853 case 'D':
854 reg = 7;
855 alloc_reg:
856 if (regs_allocated[reg])
857 goto try_next;
858 goto reg_found;
859 case 'q':
860 /* eax, ebx, ecx or edx */
861 for(reg = 0; reg < 4; reg++) {
862 if (!regs_allocated[reg])
863 goto reg_found;
864 }
865 goto try_next;
866 case 'r':
867 /* any general register */
868 for(reg = 0; reg < 8; reg++) {
869 if (!regs_allocated[reg])
870 goto reg_found;
871 }
872 goto try_next;
873 reg_found:
874 /* now we can reload in the register */
875 op->is_llong = 0;
876 op->reg = reg;
877 regs_allocated[reg] = 1;
878 break;
879 case 'i':
880 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
881 goto try_next;
882 break;
883 case 'I':
884 case 'N':
885 case 'M':
886 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
887 goto try_next;
888 break;
889 case 'm':
890 case 'g':
891 /* nothing special to do because the operand is
892 already in memory */
893 /* XXX: fix constant case */
894 if (is_output) {
895 /* if it is a reference to a memory zone, it must lie
896 in a register, so we reserve the register in the
897 input registers and a load will be generated
898 later */
899 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
900 /* any general register */
901 for(reg = 0; reg < 8; reg++) {
902 if (!input_regs_allocated[reg])
903 goto reg_found1;
904 }
905 goto try_next;
906 reg_found1:
907 /* now we can reload in the register */
908 input_regs_allocated[reg] = 1;
909 op->reg = reg;
910 }
911 }
912 break;
913 default:
914 error("asm constraint %d ('%s') could not be satisfied",
915 j, op->constraint);
916 break;
917 }
918 }
919
920 /* print sorted constraints */
921 #ifdef ASM_DEBUG
922 if (is_output)
923 printf("outputs=\n");
924 else
925 printf("inputs=\n");
926 for(i=0;i<nb_operands;i++) {
927 j = sorted_op[i];
928 op = &operands[j];
929 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
930 j,
931 op->id ? get_tok_str(op->id, NULL) : "",
932 op->constraint,
933 op->vt->r,
934 op->reg);
935 }
936 #endif
937 }
938
939 static void subst_asm_operand(CString *add_str,
940 SValue *sv, int modifier)
941 {
942 int r, reg, size, val;
943 char buf[64];
944
945 r = sv->r;
946 if ((r & VT_VALMASK) == VT_CONST) {
947 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
948 cstr_ccat(add_str, '$');
949 if (r & VT_SYM) {
950 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
951 if (sv->c.i != 0) {
952 cstr_ccat(add_str, '+');
953 } else {
954 return;
955 }
956 }
957 val = sv->c.i;
958 if (modifier == 'n')
959 val = -val;
960 snprintf(buf, sizeof(buf), "%d", sv->c.i);
961 cstr_cat(add_str, buf);
962 } else if ((r & VT_VALMASK) == VT_LOCAL) {
963 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
964 cstr_cat(add_str, buf);
965 } else if (r & VT_LVAL) {
966 reg = r & VT_VALMASK;
967 if (reg >= VT_CONST)
968 error("internal compiler error");
969 snprintf(buf, sizeof(buf), "(%%%s)",
970 get_tok_str(TOK_ASM_eax + reg, NULL));
971 cstr_cat(add_str, buf);
972 } else {
973 /* register case */
974 reg = r & VT_VALMASK;
975 if (reg >= VT_CONST)
976 error("internal compiler error");
977
978 /* choose register operand size */
979 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
980 size = 1;
981 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
982 size = 2;
983 else
984 size = 4;
985 if (size == 1 && reg >= 4)
986 size = 4;
987
988 if (modifier == 'b') {
989 if (reg >= 4)
990 error("cannot use byte register");
991 size = 1;
992 } else if (modifier == 'h') {
993 if (reg >= 4)
994 error("cannot use byte register");
995 size = -1;
996 } else if (modifier == 'w') {
997 size = 2;
998 }
999
1000 switch(size) {
1001 case -1:
1002 reg = TOK_ASM_ah + reg;
1003 break;
1004 case 1:
1005 reg = TOK_ASM_al + reg;
1006 break;
1007 case 2:
1008 reg = TOK_ASM_ax + reg;
1009 break;
1010 default:
1011 reg = TOK_ASM_eax + reg;
1012 break;
1013 }
1014 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1015 cstr_cat(add_str, buf);
1016 }
1017 }
1018
1019 /* generate prolog and epilog code for asm statment */
1020 static void asm_gen_code(ASMOperand *operands, int nb_operands,
1021 int nb_outputs, int is_output,
1022 uint8_t *clobber_regs)
1023 {
1024 uint8_t regs_allocated[NB_ASM_REGS];
1025 ASMOperand *op;
1026 int i, reg;
1027 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1028
1029 /* mark all used registers */
1030 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1031 for(i = 0; i < nb_operands;i++) {
1032 op = &operands[i];
1033 if (op->reg >= 0)
1034 regs_allocated[op->reg] = 1;
1035 }
1036 if (!is_output) {
1037 /* generate reg save code */
1038 for(i = 0; i < NB_SAVED_REGS; i++) {
1039 reg = reg_saved[i];
1040 if (regs_allocated[reg])
1041 g(0x50 + reg);
1042 }
1043
1044 /* generate load code */
1045 for(i = nb_outputs ; i < nb_operands; i++) {
1046 op = &operands[i];
1047 if (op->reg >= 0) {
1048 load(op->reg, op->vt);
1049 if (op->is_llong) {
1050 SValue sv;
1051 sv = *op->vt;
1052 sv.c.ul += 4;
1053 load(TREG_EDX, &sv);
1054 }
1055 }
1056 }
1057 /* generate load code for output memory references */
1058 for(i = 0 ; i < nb_outputs; i++) {
1059 op = &operands[i];
1060 if (op->reg >= 0 && ((op->vt->r & VT_VALMASK) == VT_LLOCAL)) {
1061 SValue sv;
1062 sv = *op->vt;
1063 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1064 load(op->reg, &sv);
1065 }
1066 }
1067 } else {
1068 /* generate save code */
1069 for(i = 0 ; i < nb_outputs; i++) {
1070 op = &operands[i];
1071 if (op->reg >= 0 && ((op->vt->r & VT_VALMASK) != VT_LLOCAL)) {
1072 store(op->reg, op->vt);
1073 if (op->is_llong) {
1074 SValue sv;
1075 sv = *op->vt;
1076 sv.c.ul += 4;
1077 store(TREG_EDX, &sv);
1078 }
1079 }
1080 }
1081 /* generate reg restore code */
1082 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1083 reg = reg_saved[i];
1084 if (regs_allocated[reg])
1085 g(0x58 + reg);
1086 }
1087 }
1088 }
1089
1090 static void asm_clobber(uint8_t *clobber_regs, const char *str)
1091 {
1092 int reg;
1093 TokenSym *ts;
1094
1095 if (!strcmp(str, "memory") ||
1096 !strcmp(str, "cc"))
1097 return;
1098 ts = tok_alloc(str, strlen(str));
1099 reg = ts->tok;
1100 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1101 reg -= TOK_ASM_eax;
1102 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1103 reg -= TOK_ASM_ax;
1104 } else {
1105 error("invalid clobber register '%s'", str);
1106 }
1107 clobber_regs[reg] = 1;
1108 }
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