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[tinycc.git] / i386-asm.c
blobe7449bf128ac469c338c7a0f4f7effd0ece2a200
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "tcc.h"
23
24 /* #define NB_ASM_REGS 8 */
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
27
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30 #define TOK_ASM_alllast TOK_ASM_subps
31
32 #define OPC_B 0x01 /* only used with OPC_WL */
33 #define OPC_WL 0x02 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x04 /* register is added to opcode */
36 #define OPC_MODRM 0x08 /* modrm encoding */
37
38 #define OPCT_MASK 0x70
39 #define OPC_FWAIT 0x10 /* add fwait opcode */
40 #define OPC_SHIFT 0x20 /* shift opcodes */
41 #define OPC_ARITH 0x30 /* arithmetic opcodes */
42 #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
43 #define OPC_TEST 0x50 /* test opcodes */
44 #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
45
46 #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
47 #ifdef TCC_TARGET_X86_64
48 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
49 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
50 # define OPC_WLX OPC_WLQ
51 # define OPC_BWLX OPC_BWLQ
52 #else
53 # define OPC_WLX OPC_WL
54 # define OPC_BWLX OPC_BWL
55 #endif
56
57 #define OPC_GROUP_SHIFT 13
58
59 /* in order to compress the operand type, we use specific operands and
60 we or only with EA */
61 enum {
62 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
65 #ifdef TCC_TARGET_X86_64
66 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
67 #endif
68 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
70 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
71 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
72 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
73 OPT_SEG,
74 OPT_ST,
75 OPT_IM8,
76 OPT_IM8S,
77 OPT_IM16,
78 OPT_IM32,
79 #ifdef TCC_TARGET_X86_64
80 OPT_IM64,
81 #endif
82 OPT_EAX, /* %al, %ax, %eax or %rax register */
83 OPT_ST0, /* %st(0) register */
84 OPT_CL, /* %cl register */
85 OPT_DX, /* %dx register */
86 OPT_ADDR, /* OP_EA with only offset */
87 OPT_INDIR, /* *(expr) */
88 /* composite types */
89 OPT_COMPOSITE_FIRST,
90 OPT_IM, /* IM8 | IM16 | IM32 */
91 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
92 OPT_REGW, /* REG16 | REG32 | REG64 */
93 OPT_IMW, /* IM16 | IM32 */
94 OPT_MMXSSE, /* MMX | SSE */
95 OPT_DISP, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
96 OPT_DISP8, /* Like OPT_ADDR, but only 8bit (short jumps) */
97 /* can be ored with any OPT_xxx */
98 OPT_EA = 0x80
99 };
100
101 #define OP_REG8 (1 << OPT_REG8)
102 #define OP_REG16 (1 << OPT_REG16)
103 #define OP_REG32 (1 << OPT_REG32)
104 #define OP_MMX (1 << OPT_MMX)
105 #define OP_SSE (1 << OPT_SSE)
106 #define OP_CR (1 << OPT_CR)
107 #define OP_TR (1 << OPT_TR)
108 #define OP_DB (1 << OPT_DB)
109 #define OP_SEG (1 << OPT_SEG)
110 #define OP_ST (1 << OPT_ST)
111 #define OP_IM8 (1 << OPT_IM8)
112 #define OP_IM8S (1 << OPT_IM8S)
113 #define OP_IM16 (1 << OPT_IM16)
114 #define OP_IM32 (1 << OPT_IM32)
115 #define OP_EAX (1 << OPT_EAX)
116 #define OP_ST0 (1 << OPT_ST0)
117 #define OP_CL (1 << OPT_CL)
118 #define OP_DX (1 << OPT_DX)
119 #define OP_ADDR (1 << OPT_ADDR)
120 #define OP_INDIR (1 << OPT_INDIR)
121 #ifdef TCC_TARGET_X86_64
122 # define OP_REG64 (1 << OPT_REG64)
123 # define OP_IM64 (1 << OPT_IM64)
124 # define OP_EA32 (OP_EA << 1)
125 #else
126 # define OP_REG64 0
127 # define OP_IM64 0
128 # define OP_EA32 0
129 #endif
130
131 #define OP_EA 0x40000000
132 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
133
134 #ifdef TCC_TARGET_X86_64
135 # define TREG_XAX TREG_RAX
136 # define TREG_XCX TREG_RCX
137 # define TREG_XDX TREG_RDX
138 #else
139 # define TREG_XAX TREG_EAX
140 # define TREG_XCX TREG_ECX
141 # define TREG_XDX TREG_EDX
142 #endif
143
144 typedef struct ASMInstr {
145 uint16_t sym;
146 uint16_t opcode;
147 uint16_t instr_type;
148 uint8_t nb_ops;
149 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
150 } ASMInstr;
151
152 typedef struct Operand {
153 uint32_t type;
154 int8_t reg; /* register, -1 if none */
155 int8_t reg2; /* second register, -1 if none */
156 uint8_t shift;
157 ExprValue e;
158 } Operand;
159
160 static const uint8_t reg_to_size[9] = {
161 /*
162 [OP_REG8] = 0,
163 [OP_REG16] = 1,
164 [OP_REG32] = 2,
165 #ifdef TCC_TARGET_X86_64
166 [OP_REG64] = 3,
167 #endif
168 */
169 0, 0, 1, 0, 2, 0, 0, 0, 3
170 };
171
172 #define NB_TEST_OPCODES 30
173
174 static const uint8_t test_bits[NB_TEST_OPCODES] = {
175 0x00, /* o */
176 0x01, /* no */
177 0x02, /* b */
178 0x02, /* c */
179 0x02, /* nae */
180 0x03, /* nb */
181 0x03, /* nc */
182 0x03, /* ae */
183 0x04, /* e */
184 0x04, /* z */
185 0x05, /* ne */
186 0x05, /* nz */
187 0x06, /* be */
188 0x06, /* na */
189 0x07, /* nbe */
190 0x07, /* a */
191 0x08, /* s */
192 0x09, /* ns */
193 0x0a, /* p */
194 0x0a, /* pe */
195 0x0b, /* np */
196 0x0b, /* po */
197 0x0c, /* l */
198 0x0c, /* nge */
199 0x0d, /* nl */
200 0x0d, /* ge */
201 0x0e, /* le */
202 0x0e, /* ng */
203 0x0f, /* nle */
204 0x0f, /* g */
205 };
206
207 static const uint8_t segment_prefixes[] = {
208 0x26, /* es */
209 0x2e, /* cs */
210 0x36, /* ss */
211 0x3e, /* ds */
212 0x64, /* fs */
213 0x65 /* gs */
214 };
215
216 static const ASMInstr asm_instrs[] = {
217 #define ALT(x) x
218 /* This removes a 0x0f in the second byte */
219 #define O(o) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o))
220 /* This constructs instr_type from opcode, type and group. */
221 #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
222 #define DEF_ASM_OP0(name, opcode)
223 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0 },
224 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
225 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
226 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
227 #ifdef TCC_TARGET_X86_64
228 # include "x86_64-asm.h"
229 #else
230 # include "i386-asm.h"
231 #endif
232 /* last operation */
233 { 0, },
234 };
235
236 static const uint16_t op0_codes[] = {
237 #define ALT(x)
238 #define DEF_ASM_OP0(x, opcode) opcode,
239 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
240 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
241 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
242 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
243 #ifdef TCC_TARGET_X86_64
244 # include "x86_64-asm.h"
245 #else
246 # include "i386-asm.h"
247 #endif
248 };
249
250 static inline int get_reg_shift(TCCState *s1)
251 {
252 int shift, v;
253 v = asm_int_expr(s1);
254 switch(v) {
255 case 1:
256 shift = 0;
257 break;
258 case 2:
259 shift = 1;
260 break;
261 case 4:
262 shift = 2;
263 break;
264 case 8:
265 shift = 3;
266 break;
267 default:
268 expect("1, 2, 4 or 8 constant");
269 shift = 0;
270 break;
271 }
272 return shift;
273 }
274
275 static int asm_parse_reg(int *type)
276 {
277 int reg = 0;
278 *type = 0;
279 if (tok != '%')
280 goto error_32;
281 next();
282 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
283 reg = tok - TOK_ASM_eax;
284 #ifdef TCC_TARGET_X86_64
285 *type = OP_EA32;
286 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
287 reg = tok - TOK_ASM_rax;
288 } else if (tok == TOK_ASM_rip) {
289 reg = 8;
290 #endif
291 } else {
292 error_32:
293 expect("register");
294 }
295 next();
296 return reg;
297 }
298
299 static void parse_operand(TCCState *s1, Operand *op)
300 {
301 ExprValue e;
302 int reg, indir;
303 const char *p;
304
305 indir = 0;
306 if (tok == '*') {
307 next();
308 indir = OP_INDIR;
309 }
310
311 if (tok == '%') {
312 next();
313 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
314 reg = tok - TOK_ASM_al;
315 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
316 op->reg = reg & 7;
317 if ((op->type & OP_REG) && op->reg == TREG_XAX)
318 op->type |= OP_EAX;
319 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
320 op->type |= OP_CL;
321 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
322 op->type |= OP_DX;
323 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
324 op->type = OP_DB;
325 op->reg = tok - TOK_ASM_dr0;
326 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
327 op->type = OP_SEG;
328 op->reg = tok - TOK_ASM_es;
329 } else if (tok == TOK_ASM_st) {
330 op->type = OP_ST;
331 op->reg = 0;
332 next();
333 if (tok == '(') {
334 next();
335 if (tok != TOK_PPNUM)
336 goto reg_error;
337 p = tokc.str.data;
338 reg = p[0] - '0';
339 if ((unsigned)reg >= 8 || p[1] != '\0')
340 goto reg_error;
341 op->reg = reg;
342 next();
343 skip(')');
344 }
345 if (op->reg == 0)
346 op->type |= OP_ST0;
347 goto no_skip;
348 } else {
349 reg_error:
350 tcc_error("unknown register");
351 }
352 next();
353 no_skip: ;
354 } else if (tok == '$') {
355 /* constant value */
356 next();
357 asm_expr(s1, &e);
358 op->type = OP_IM32;
359 op->e.v = e.v;
360 op->e.sym = e.sym;
361 if (!op->e.sym) {
362 if (op->e.v == (uint8_t)op->e.v)
363 op->type |= OP_IM8;
364 if (op->e.v == (int8_t)op->e.v)
365 op->type |= OP_IM8S;
366 if (op->e.v == (uint16_t)op->e.v)
367 op->type |= OP_IM16;
368 #ifdef TCC_TARGET_X86_64
369 if (op->e.v != (int32_t)op->e.v)
370 op->type = OP_IM64;
371 #endif
372 }
373 } else {
374 /* address(reg,reg2,shift) with all variants */
375 op->type = OP_EA;
376 op->reg = -1;
377 op->reg2 = -1;
378 op->shift = 0;
379 if (tok != '(') {
380 asm_expr(s1, &e);
381 op->e.v = e.v;
382 op->e.sym = e.sym;
383 } else {
384 next();
385 if (tok == '%') {
386 unget_tok('(');
387 op->e.v = 0;
388 op->e.sym = NULL;
389 } else {
390 /* bracketed offset expression */
391 asm_expr(s1, &e);
392 if (tok != ')')
393 expect(")");
394 next();
395 op->e.v = e.v;
396 op->e.sym = e.sym;
397 }
398 }
399 if (tok == '(') {
400 int type = 0;
401 next();
402 if (tok != ',') {
403 op->reg = asm_parse_reg(&type);
404 }
405 if (tok == ',') {
406 next();
407 if (tok != ',') {
408 op->reg2 = asm_parse_reg(&type);
409 }
410 if (tok == ',') {
411 next();
412 op->shift = get_reg_shift(s1);
413 }
414 }
415 if (type & OP_EA32)
416 op->type |= OP_EA32;
417 skip(')');
418 }
419 if (op->reg == -1 && op->reg2 == -1)
420 op->type |= OP_ADDR;
421 }
422 op->type |= indir;
423 }
424
425 /* XXX: unify with C code output ? */
426 ST_FUNC void gen_expr32(ExprValue *pe)
427 {
428 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
429 }
430
431 #ifdef TCC_TARGET_X86_64
432 static void gen_expr64(ExprValue *pe)
433 {
434 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
435 }
436 #endif
437
438 /* XXX: unify with C code output ? */
439 static void gen_disp32(ExprValue *pe)
440 {
441 Sym *sym = pe->sym;
442 if (sym && sym->r == cur_text_section->sh_num) {
443 /* same section: we can output an absolute value. Note
444 that the TCC compiler behaves differently here because
445 it always outputs a relocation to ease (future) code
446 elimination in the linker */
447 gen_le32(pe->v + sym->jnext - ind - 4);
448 } else {
449 if (sym && sym->type.t == VT_VOID) {
450 sym->type.t = VT_FUNC;
451 sym->type.ref = NULL;
452 }
453 gen_addrpc32(VT_SYM, sym, pe->v);
454 }
455 }
456
457 /* generate the modrm operand */
458 static inline int asm_modrm(int reg, Operand *op)
459 {
460 int mod, reg1, reg2, sib_reg1;
461
462 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
463 g(0xc0 + (reg << 3) + op->reg);
464 } else if (op->reg == -1 && op->reg2 == -1) {
465 /* displacement only */
466 #ifdef TCC_TARGET_X86_64
467 g(0x04 + (reg << 3));
468 g(0x25);
469 #else
470 g(0x05 + (reg << 3));
471 #endif
472 gen_expr32(&op->e);
473 #ifdef TCC_TARGET_X86_64
474 } else if (op->reg == 8) {
475 ExprValue *pe = &op->e;
476 g(0x05 + (reg << 3));
477 gen_addrpc32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
478 return ind;
479 #endif
480 } else {
481 sib_reg1 = op->reg;
482 /* fist compute displacement encoding */
483 if (sib_reg1 == -1) {
484 sib_reg1 = 5;
485 mod = 0x00;
486 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
487 mod = 0x00;
488 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
489 mod = 0x40;
490 } else {
491 mod = 0x80;
492 }
493 /* compute if sib byte needed */
494 reg1 = op->reg;
495 if (op->reg2 != -1)
496 reg1 = 4;
497 g(mod + (reg << 3) + reg1);
498 if (reg1 == 4) {
499 /* add sib byte */
500 reg2 = op->reg2;
501 if (reg2 == -1)
502 reg2 = 4; /* indicate no index */
503 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
504 }
505 /* add offset */
506 if (mod == 0x40) {
507 g(op->e.v);
508 } else if (mod == 0x80 || op->reg == -1) {
509 gen_expr32(&op->e);
510 }
511 }
512 return 0;
513 }
514
515 static void maybe_print_stats (void)
516 {
517 static int already = 1;
518 if (!already)
519 /* print stats about opcodes */
520 {
521 const struct ASMInstr *pa;
522 int freq[4];
523 int op_vals[500];
524 int nb_op_vals, i, j;
525
526 already = 1;
527 nb_op_vals = 0;
528 memset(freq, 0, sizeof(freq));
529 for(pa = asm_instrs; pa->sym != 0; pa++) {
530 freq[pa->nb_ops]++;
531 //for(i=0;i<pa->nb_ops;i++) {
532 for(j=0;j<nb_op_vals;j++) {
533 //if (pa->op_type[i] == op_vals[j])
534 if (pa->instr_type == op_vals[j])
535 goto found;
536 }
537 //op_vals[nb_op_vals++] = pa->op_type[i];
538 op_vals[nb_op_vals++] = pa->instr_type;
539 found: ;
540 //}
541 }
542 for(i=0;i<nb_op_vals;i++) {
543 int v = op_vals[i];
544 //if ((v & (v - 1)) != 0)
545 printf("%3d: %08x\n", i, v);
546 }
547 printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
548 (int)sizeof(asm_instrs),
549 (int)sizeof(asm_instrs) / (int)sizeof(ASMInstr),
550 freq[0], freq[1], freq[2], freq[3]);
551 }
552 }
553
554 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
555 {
556 const ASMInstr *pa;
557 int i, modrm_index, reg, v, op1, seg_prefix, pc;
558 int nb_ops, s;
559 Operand ops[MAX_OPERANDS], *pop;
560 int op_type[3]; /* decoded op type */
561 int alltypes; /* OR of all operand types */
562 int autosize;
563 int p66;
564
565 maybe_print_stats();
566 /* force synthetic ';' after prefix instruction, so we can handle */
567 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
568 if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
569 unget_tok(';');
570
571 /* get operands */
572 pop = ops;
573 nb_ops = 0;
574 seg_prefix = 0;
575 alltypes = 0;
576 for(;;) {
577 if (tok == ';' || tok == TOK_LINEFEED)
578 break;
579 if (nb_ops >= MAX_OPERANDS) {
580 tcc_error("incorrect number of operands");
581 }
582 parse_operand(s1, pop);
583 if (tok == ':') {
584 if (pop->type != OP_SEG || seg_prefix)
585 tcc_error("incorrect prefix");
586 seg_prefix = segment_prefixes[pop->reg];
587 next();
588 parse_operand(s1, pop);
589 if (!(pop->type & OP_EA)) {
590 tcc_error("segment prefix must be followed by memory reference");
591 }
592 }
593 pop++;
594 nb_ops++;
595 if (tok != ',')
596 break;
597 next();
598 }
599
600 s = 0; /* avoid warning */
601
602 /* optimize matching by using a lookup table (no hashing is needed
603 !) */
604 for(pa = asm_instrs; pa->sym != 0; pa++) {
605 int it = pa->instr_type & OPCT_MASK;
606 s = 0;
607 if (it == OPC_FARITH) {
608 v = opcode - pa->sym;
609 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
610 continue;
611 } else if (it == OPC_ARITH) {
612 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
613 continue;
614 s = (opcode - pa->sym) % NBWLX;
615 if ((pa->instr_type & OPC_BWLX) == OPC_WLX)
616 {
617 /* We need to reject the xxxb opcodes that we accepted above.
618 Note that pa->sym for WLX opcodes is the 'w' token,
619 to get the 'b' token subtract one. */
620 if (((opcode - pa->sym + 1) % NBWLX) == 0)
621 continue;
622 s++;
623 }
624 } else if (it == OPC_SHIFT) {
625 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
626 continue;
627 s = (opcode - pa->sym) % NBWLX;
628 } else if (it == OPC_TEST) {
629 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
630 continue;
631 /* cmovxx is a test opcode but accepts multiple sizes.
632 TCC doesn't accept the suffixed mnemonic, instead we
633 simply force size autodetection always. */
634 if (pa->instr_type & OPC_WLX)
635 s = NBWLX - 1;
636 } else if (pa->instr_type & OPC_B) {
637 #ifdef TCC_TARGET_X86_64
638 /* Some instructions don't have the full size but only
639 bwl form. insb e.g. */
640 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
641 && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
642 continue;
643 #endif
644 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
645 continue;
646 s = opcode - pa->sym;
647 } else if (pa->instr_type & OPC_WLX) {
648 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
649 continue;
650 s = opcode - pa->sym + 1;
651 } else {
652 if (pa->sym != opcode)
653 continue;
654 }
655 if (pa->nb_ops != nb_ops)
656 continue;
657 #ifdef TCC_TARGET_X86_64
658 /* Special case for moves. Selecting the IM64->REG64 form
659 should only be done if we really have an >32bit imm64, and that
660 is hardcoded. Ignore it here. */
661 if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
662 && ops[1].type == OP_REG64
663 && !(pa->instr_type & OPC_0F))
664 continue;
665 #endif
666 /* now decode and check each operand */
667 alltypes = 0;
668 for(i = 0; i < nb_ops; i++) {
669 int op1, op2;
670 op1 = pa->op_type[i];
671 op2 = op1 & 0x1f;
672 switch(op2) {
673 case OPT_IM:
674 v = OP_IM8 | OP_IM16 | OP_IM32;
675 break;
676 case OPT_REG:
677 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
678 break;
679 case OPT_REGW:
680 v = OP_REG16 | OP_REG32 | OP_REG64;
681 break;
682 case OPT_IMW:
683 v = OP_IM16 | OP_IM32;
684 break;
685 case OPT_MMXSSE:
686 v = OP_MMX | OP_SSE;
687 break;
688 case OPT_DISP:
689 case OPT_DISP8:
690 v = OP_ADDR;
691 break;
692 default:
693 v = 1 << op2;
694 break;
695 }
696 if (op1 & OPT_EA)
697 v |= OP_EA;
698 op_type[i] = v;
699 if ((ops[i].type & v) == 0)
700 goto next;
701 alltypes |= ops[i].type;
702 }
703 /* all is matching ! */
704 break;
705 next: ;
706 }
707 if (pa->sym == 0) {
708 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
709 int b;
710 b = op0_codes[opcode - TOK_ASM_first];
711 if (b & 0xff00)
712 g(b >> 8);
713 g(b);
714 return;
715 } else if (opcode <= TOK_ASM_alllast) {
716 tcc_error("bad operand with opcode '%s'",
717 get_tok_str(opcode, NULL));
718 } else {
719 tcc_error("unknown opcode '%s'",
720 get_tok_str(opcode, NULL));
721 }
722 }
723 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
724 autosize = NBWLX-1;
725 #ifdef TCC_TARGET_X86_64
726 /* XXX the autosize should rather be zero, to not have to adjust this
727 all the time. */
728 if ((pa->instr_type & OPC_BWLQ) == OPC_B)
729 autosize = NBWLX-2;
730 #endif
731 if (s == autosize) {
732 for(i = 0; s == autosize && i < nb_ops; i++) {
733 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
734 s = reg_to_size[ops[i].type & OP_REG];
735 }
736 if (s == autosize) {
737 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
738 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
739 s = 2;
740 else
741 tcc_error("cannot infer opcode suffix");
742 }
743 }
744
745 #ifdef TCC_TARGET_X86_64
746 /* Generate addr32 prefix if needed */
747 for(i = 0; i < nb_ops; i++) {
748 if (ops[i].type & OP_EA32) {
749 g(0x67);
750 break;
751 }
752 }
753 #endif
754 /* generate data16 prefix if needed */
755 p66 = 0;
756 if (s == 1)
757 p66 = 1;
758 else {
759 /* accepting mmx+sse in all operands --> needs 0x66 to
760 switch to sse mode. Accepting only sse in an operand --> is
761 already SSE insn and needs 0x66/f2/f3 handling. */
762 for (i = 0; i < nb_ops; i++)
763 if ((op_type[i] & (OP_MMX | OP_SSE)) == (OP_MMX | OP_SSE)
764 && ops[i].type & OP_SSE)
765 p66 = 1;
766 }
767 if (p66)
768 g(0x66);
769 #ifdef TCC_TARGET_X86_64
770 if (s == 3 || (alltypes & OP_REG64)) {
771 /* generate REX prefix */
772 int default64 = 0;
773 for(i = 0; i < nb_ops; i++) {
774 if (op_type[i] == OP_REG64) {
775 /* If only 64bit regs are accepted in one operand
776 this is a default64 instruction without need for
777 REX prefixes. */
778 default64 = 1;
779 break;
780 }
781 }
782 /* XXX find better encoding for the default64 instructions. */
783 if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
784 && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
785 && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
786 && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
787 && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
788 && !default64)
789 g(0x48);
790 }
791 #endif
792
793 /* now generates the operation */
794 if (OPCT_IS(pa->instr_type, OPC_FWAIT))
795 g(0x9b);
796 if (seg_prefix)
797 g(seg_prefix);
798
799 v = pa->opcode;
800 if (pa->instr_type & OPC_0F)
801 v = ((v & ~0xff) << 8) | 0x0f00 | (v & 0xff);
802 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
803 /* kludge for imul $im, %reg */
804 nb_ops = 3;
805 ops[2] = ops[1];
806 op_type[2] = op_type[1];
807 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
808 v--; /* int $3 case */
809 nb_ops = 0;
810 } else if ((v == 0x06 || v == 0x07)) {
811 if (ops[0].reg >= 4) {
812 /* push/pop %fs or %gs */
813 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
814 } else {
815 v += ops[0].reg << 3;
816 }
817 nb_ops = 0;
818 } else if (v <= 0x05) {
819 /* arith case */
820 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
821 } else if ((pa->instr_type & (OPCT_MASK | OPC_MODRM)) == OPC_FARITH) {
822 /* fpu arith case */
823 v += ((opcode - pa->sym) / 6) << 3;
824 }
825 if (pa->instr_type & OPC_REG) {
826 /* mov $im, %reg case */
827 if (v == 0xb0 && s >= 1)
828 v += 7;
829 for(i = 0; i < nb_ops; i++) {
830 if (op_type[i] & (OP_REG | OP_ST)) {
831 v += ops[i].reg;
832 break;
833 }
834 }
835 }
836 if (pa->instr_type & OPC_B)
837 v += s >= 1;
838 if (nb_ops == 1 && pa->op_type[0] == OPT_DISP8) {
839 Sym *sym;
840 int jmp_disp;
841
842 /* see if we can really generate the jump with a byte offset */
843 sym = ops[0].e.sym;
844 if (!sym)
845 goto no_short_jump;
846 if (sym->r != cur_text_section->sh_num)
847 goto no_short_jump;
848 jmp_disp = ops[0].e.v + sym->jnext - ind - 2 - (v >= 0xff);
849 if (jmp_disp == (int8_t)jmp_disp) {
850 /* OK to generate jump */
851 ops[0].e.sym = 0;
852 ops[0].e.v = jmp_disp;
853 op_type[0] = OP_IM8S;
854 } else {
855 no_short_jump:
856 /* long jump will be allowed. need to modify the
857 opcode slightly */
858 if (v == 0xeb) /* jmp */
859 v = 0xe9;
860 else if (v == 0x70) /* jcc */
861 v += 0x0f10;
862 else
863 tcc_error("invalid displacement");
864 }
865 }
866 if (OPCT_IS(pa->instr_type, OPC_TEST))
867 v += test_bits[opcode - pa->sym];
868 op1 = v >> 16;
869 if (op1)
870 g(op1);
871 op1 = (v >> 8) & 0xff;
872 if (op1)
873 g(op1);
874 g(v);
875
876 /* search which operand will used for modrm */
877 modrm_index = 0;
878 if (OPCT_IS(pa->instr_type, OPC_SHIFT)) {
879 reg = (opcode - pa->sym) / NBWLX;
880 if (reg == 6)
881 reg = 7;
882 } else if (OPCT_IS(pa->instr_type, OPC_ARITH)) {
883 reg = (opcode - pa->sym) / NBWLX;
884 } else if (OPCT_IS(pa->instr_type, OPC_FARITH)) {
885 reg = (opcode - pa->sym) / 6;
886 } else {
887 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
888 }
889
890 pc = 0;
891 if (pa->instr_type & OPC_MODRM) {
892 /* first look for an ea operand */
893 for(i = 0;i < nb_ops; i++) {
894 if (op_type[i] & OP_EA)
895 goto modrm_found;
896 }
897 /* then if not found, a register or indirection (shift instructions) */
898 for(i = 0;i < nb_ops; i++) {
899 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
900 goto modrm_found;
901 }
902 #ifdef ASM_DEBUG
903 tcc_error("bad op table");
904 #endif
905 modrm_found:
906 modrm_index = i;
907 /* if a register is used in another operand then it is
908 used instead of group */
909 for(i = 0;i < nb_ops; i++) {
910 v = op_type[i];
911 if (i != modrm_index &&
912 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
913 reg = ops[i].reg;
914 break;
915 }
916 }
917 pc = asm_modrm(reg, &ops[modrm_index]);
918 }
919
920 /* emit constants */
921 #ifndef TCC_TARGET_X86_64
922 if (!(pa->instr_type & OPC_0F)
923 && (pa->opcode == 0x9a || pa->opcode == 0xea)) {
924 /* ljmp or lcall kludge */
925 gen_expr32(&ops[1].e);
926 if (ops[0].e.sym)
927 tcc_error("cannot relocate");
928 gen_le16(ops[0].e.v);
929 return;
930 }
931 #endif
932 for(i = 0;i < nb_ops; i++) {
933 v = op_type[i];
934 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
935 /* if multiple sizes are given it means we must look
936 at the op size */
937 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
938 if (s == 0)
939 v = OP_IM8;
940 else if (s == 1)
941 v = OP_IM16;
942 else if (s == 2 || (v & OP_IM64) == 0)
943 v = OP_IM32;
944 else
945 v = OP_IM64;
946 }
947
948 if ((v & (OP_IM8 | OP_IM8S | OP_IM16)) && ops[i].e.sym)
949 tcc_error("cannot relocate");
950
951 if (v & (OP_IM8 | OP_IM8S)) {
952 g(ops[i].e.v);
953 } else if (v & OP_IM16) {
954 gen_le16(ops[i].e.v);
955 #ifdef TCC_TARGET_X86_64
956 } else if (v & OP_IM64) {
957 gen_expr64(&ops[i].e);
958 #endif
959 } else if (pa->op_type[i] == OPT_DISP || pa->op_type[i] == OPT_DISP8) {
960 gen_disp32(&ops[i].e);
961 } else {
962 gen_expr32(&ops[i].e);
963 }
964 }
965 }
966
967 /* after immediate operands, adjust pc-relative address */
968 if (pc)
969 add32le(text_section->data + pc - 4, pc - ind);
970 }
971
972 /* return the constraint priority (we allocate first the lowest
973 numbered constraints) */
974 static inline int constraint_priority(const char *str)
975 {
976 int priority, c, pr;
977
978 /* we take the lowest priority */
979 priority = 0;
980 for(;;) {
981 c = *str;
982 if (c == '\0')
983 break;
984 str++;
985 switch(c) {
986 case 'A':
987 pr = 0;
988 break;
989 case 'a':
990 case 'b':
991 case 'c':
992 case 'd':
993 case 'S':
994 case 'D':
995 pr = 1;
996 break;
997 case 'q':
998 pr = 2;
999 break;
1000 case 'r':
1001 pr = 3;
1002 break;
1003 case 'N':
1004 case 'M':
1005 case 'I':
1006 case 'i':
1007 case 'm':
1008 case 'g':
1009 pr = 4;
1010 break;
1011 default:
1012 tcc_error("unknown constraint '%c'", c);
1013 pr = 0;
1014 }
1015 if (pr > priority)
1016 priority = pr;
1017 }
1018 return priority;
1019 }
1020
1021 static const char *skip_constraint_modifiers(const char *p)
1022 {
1023 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1024 p++;
1025 return p;
1026 }
1027
1028 #define REG_OUT_MASK 0x01
1029 #define REG_IN_MASK 0x02
1030
1031 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1032
1033 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1034 int nb_operands, int nb_outputs,
1035 const uint8_t *clobber_regs,
1036 int *pout_reg)
1037 {
1038 ASMOperand *op;
1039 int sorted_op[MAX_ASM_OPERANDS];
1040 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1041 const char *str;
1042 uint8_t regs_allocated[NB_ASM_REGS];
1043
1044 /* init fields */
1045 for(i=0;i<nb_operands;i++) {
1046 op = &operands[i];
1047 op->input_index = -1;
1048 op->ref_index = -1;
1049 op->reg = -1;
1050 op->is_memory = 0;
1051 op->is_rw = 0;
1052 }
1053 /* compute constraint priority and evaluate references to output
1054 constraints if input constraints */
1055 for(i=0;i<nb_operands;i++) {
1056 op = &operands[i];
1057 str = op->constraint;
1058 str = skip_constraint_modifiers(str);
1059 if (isnum(*str) || *str == '[') {
1060 /* this is a reference to another constraint */
1061 k = find_constraint(operands, nb_operands, str, NULL);
1062 if ((unsigned)k >= i || i < nb_outputs)
1063 tcc_error("invalid reference in constraint %d ('%s')",
1064 i, str);
1065 op->ref_index = k;
1066 if (operands[k].input_index >= 0)
1067 tcc_error("cannot reference twice the same operand");
1068 operands[k].input_index = i;
1069 op->priority = 5;
1070 } else {
1071 op->priority = constraint_priority(str);
1072 }
1073 }
1074
1075 /* sort operands according to their priority */
1076 for(i=0;i<nb_operands;i++)
1077 sorted_op[i] = i;
1078 for(i=0;i<nb_operands - 1;i++) {
1079 for(j=i+1;j<nb_operands;j++) {
1080 p1 = operands[sorted_op[i]].priority;
1081 p2 = operands[sorted_op[j]].priority;
1082 if (p2 < p1) {
1083 tmp = sorted_op[i];
1084 sorted_op[i] = sorted_op[j];
1085 sorted_op[j] = tmp;
1086 }
1087 }
1088 }
1089
1090 for(i = 0;i < NB_ASM_REGS; i++) {
1091 if (clobber_regs[i])
1092 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1093 else
1094 regs_allocated[i] = 0;
1095 }
1096 /* esp cannot be used */
1097 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1098 /* ebp cannot be used yet */
1099 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1100
1101 /* allocate registers and generate corresponding asm moves */
1102 for(i=0;i<nb_operands;i++) {
1103 j = sorted_op[i];
1104 op = &operands[j];
1105 str = op->constraint;
1106 /* no need to allocate references */
1107 if (op->ref_index >= 0)
1108 continue;
1109 /* select if register is used for output, input or both */
1110 if (op->input_index >= 0) {
1111 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1112 } else if (j < nb_outputs) {
1113 reg_mask = REG_OUT_MASK;
1114 } else {
1115 reg_mask = REG_IN_MASK;
1116 }
1117 try_next:
1118 c = *str++;
1119 switch(c) {
1120 case '=':
1121 goto try_next;
1122 case '+':
1123 op->is_rw = 1;
1124 /* FALL THRU */
1125 case '&':
1126 if (j >= nb_outputs)
1127 tcc_error("'%c' modifier can only be applied to outputs", c);
1128 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1129 goto try_next;
1130 case 'A':
1131 /* allocate both eax and edx */
1132 if (is_reg_allocated(TREG_XAX) ||
1133 is_reg_allocated(TREG_XDX))
1134 goto try_next;
1135 op->is_llong = 1;
1136 op->reg = TREG_XAX;
1137 regs_allocated[TREG_XAX] |= reg_mask;
1138 regs_allocated[TREG_XDX] |= reg_mask;
1139 break;
1140 case 'a':
1141 reg = TREG_XAX;
1142 goto alloc_reg;
1143 case 'b':
1144 reg = 3;
1145 goto alloc_reg;
1146 case 'c':
1147 reg = TREG_XCX;
1148 goto alloc_reg;
1149 case 'd':
1150 reg = TREG_XDX;
1151 goto alloc_reg;
1152 case 'S':
1153 reg = 6;
1154 goto alloc_reg;
1155 case 'D':
1156 reg = 7;
1157 alloc_reg:
1158 if (is_reg_allocated(reg))
1159 goto try_next;
1160 goto reg_found;
1161 case 'q':
1162 /* eax, ebx, ecx or edx */
1163 for(reg = 0; reg < 4; reg++) {
1164 if (!is_reg_allocated(reg))
1165 goto reg_found;
1166 }
1167 goto try_next;
1168 case 'r':
1169 /* any general register */
1170 for(reg = 0; reg < 8; reg++) {
1171 if (!is_reg_allocated(reg))
1172 goto reg_found;
1173 }
1174 goto try_next;
1175 reg_found:
1176 /* now we can reload in the register */
1177 op->is_llong = 0;
1178 op->reg = reg;
1179 regs_allocated[reg] |= reg_mask;
1180 break;
1181 case 'i':
1182 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1183 goto try_next;
1184 break;
1185 case 'I':
1186 case 'N':
1187 case 'M':
1188 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1189 goto try_next;
1190 break;
1191 case 'm':
1192 case 'g':
1193 /* nothing special to do because the operand is already in
1194 memory, except if the pointer itself is stored in a
1195 memory variable (VT_LLOCAL case) */
1196 /* XXX: fix constant case */
1197 /* if it is a reference to a memory zone, it must lie
1198 in a register, so we reserve the register in the
1199 input registers and a load will be generated
1200 later */
1201 if (j < nb_outputs || c == 'm') {
1202 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1203 /* any general register */
1204 for(reg = 0; reg < 8; reg++) {
1205 if (!(regs_allocated[reg] & REG_IN_MASK))
1206 goto reg_found1;
1207 }
1208 goto try_next;
1209 reg_found1:
1210 /* now we can reload in the register */
1211 regs_allocated[reg] |= REG_IN_MASK;
1212 op->reg = reg;
1213 op->is_memory = 1;
1214 }
1215 }
1216 break;
1217 default:
1218 tcc_error("asm constraint %d ('%s') could not be satisfied",
1219 j, op->constraint);
1220 break;
1221 }
1222 /* if a reference is present for that operand, we assign it too */
1223 if (op->input_index >= 0) {
1224 operands[op->input_index].reg = op->reg;
1225 operands[op->input_index].is_llong = op->is_llong;
1226 }
1227 }
1228
1229 /* compute out_reg. It is used to store outputs registers to memory
1230 locations references by pointers (VT_LLOCAL case) */
1231 *pout_reg = -1;
1232 for(i=0;i<nb_operands;i++) {
1233 op = &operands[i];
1234 if (op->reg >= 0 &&
1235 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1236 !op->is_memory) {
1237 for(reg = 0; reg < 8; reg++) {
1238 if (!(regs_allocated[reg] & REG_OUT_MASK))
1239 goto reg_found2;
1240 }
1241 tcc_error("could not find free output register for reloading");
1242 reg_found2:
1243 *pout_reg = reg;
1244 break;
1245 }
1246 }
1247
1248 /* print sorted constraints */
1249 #ifdef ASM_DEBUG
1250 for(i=0;i<nb_operands;i++) {
1251 j = sorted_op[i];
1252 op = &operands[j];
1253 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1254 j,
1255 op->id ? get_tok_str(op->id, NULL) : "",
1256 op->constraint,
1257 op->vt->r,
1258 op->reg);
1259 }
1260 if (*pout_reg >= 0)
1261 printf("out_reg=%d\n", *pout_reg);
1262 #endif
1263 }
1264
1265 ST_FUNC void subst_asm_operand(CString *add_str,
1266 SValue *sv, int modifier)
1267 {
1268 int r, reg, size, val;
1269 char buf[64];
1270
1271 r = sv->r;
1272 if ((r & VT_VALMASK) == VT_CONST) {
1273 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1274 cstr_ccat(add_str, '$');
1275 if (r & VT_SYM) {
1276 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL), -1);
1277 if ((uint32_t)sv->c.i == 0)
1278 goto no_offset;
1279 cstr_ccat(add_str, '+');
1280 }
1281 val = sv->c.i;
1282 if (modifier == 'n')
1283 val = -val;
1284 snprintf(buf, sizeof(buf), "%d", (int)sv->c.i);
1285 cstr_cat(add_str, buf, -1);
1286 no_offset:;
1287 #ifdef TCC_TARGET_X86_64
1288 if (r & VT_LVAL)
1289 cstr_cat(add_str, "(%rip)", -1);
1290 #endif
1291 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1292 #ifdef TCC_TARGET_X86_64
1293 snprintf(buf, sizeof(buf), "%d(%%rbp)", (int)sv->c.i);
1294 #else
1295 snprintf(buf, sizeof(buf), "%d(%%ebp)", (int)sv->c.i);
1296 #endif
1297 cstr_cat(add_str, buf, -1);
1298 } else if (r & VT_LVAL) {
1299 reg = r & VT_VALMASK;
1300 if (reg >= VT_CONST)
1301 tcc_error("internal compiler error");
1302 snprintf(buf, sizeof(buf), "(%%%s)",
1303 #ifdef TCC_TARGET_X86_64
1304 get_tok_str(TOK_ASM_rax + reg, NULL)
1305 #else
1306 get_tok_str(TOK_ASM_eax + reg, NULL)
1307 #endif
1308 );
1309 cstr_cat(add_str, buf, -1);
1310 } else {
1311 /* register case */
1312 reg = r & VT_VALMASK;
1313 if (reg >= VT_CONST)
1314 tcc_error("internal compiler error");
1315
1316 /* choose register operand size */
1317 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1318 size = 1;
1319 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1320 size = 2;
1321 #ifdef TCC_TARGET_X86_64
1322 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1323 size = 8;
1324 #endif
1325 else
1326 size = 4;
1327 if (size == 1 && reg >= 4)
1328 size = 4;
1329
1330 if (modifier == 'b') {
1331 if (reg >= 4)
1332 tcc_error("cannot use byte register");
1333 size = 1;
1334 } else if (modifier == 'h') {
1335 if (reg >= 4)
1336 tcc_error("cannot use byte register");
1337 size = -1;
1338 } else if (modifier == 'w') {
1339 size = 2;
1340 } else if (modifier == 'k') {
1341 size = 4;
1342 #ifdef TCC_TARGET_X86_64
1343 } else if (modifier == 'q') {
1344 size = 8;
1345 #endif
1346 }
1347
1348 switch(size) {
1349 case -1:
1350 reg = TOK_ASM_ah + reg;
1351 break;
1352 case 1:
1353 reg = TOK_ASM_al + reg;
1354 break;
1355 case 2:
1356 reg = TOK_ASM_ax + reg;
1357 break;
1358 default:
1359 reg = TOK_ASM_eax + reg;
1360 break;
1361 #ifdef TCC_TARGET_X86_64
1362 case 8:
1363 reg = TOK_ASM_rax + reg;
1364 break;
1365 #endif
1366 }
1367 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1368 cstr_cat(add_str, buf, -1);
1369 }
1370 }
1371
1372 /* generate prolog and epilog code for asm statement */
1373 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1374 int nb_outputs, int is_output,
1375 uint8_t *clobber_regs,
1376 int out_reg)
1377 {
1378 uint8_t regs_allocated[NB_ASM_REGS];
1379 ASMOperand *op;
1380 int i, reg;
1381 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1382
1383 /* mark all used registers */
1384 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1385 for(i = 0; i < nb_operands;i++) {
1386 op = &operands[i];
1387 if (op->reg >= 0)
1388 regs_allocated[op->reg] = 1;
1389 }
1390 if (!is_output) {
1391 /* generate reg save code */
1392 for(i = 0; i < NB_SAVED_REGS; i++) {
1393 reg = reg_saved[i];
1394 if (regs_allocated[reg]) {
1395 g(0x50 + reg);
1396 }
1397 }
1398
1399 /* generate load code */
1400 for(i = 0; i < nb_operands; i++) {
1401 op = &operands[i];
1402 if (op->reg >= 0) {
1403 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1404 op->is_memory) {
1405 /* memory reference case (for both input and
1406 output cases) */
1407 SValue sv;
1408 sv = *op->vt;
1409 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL;
1410 sv.type.t = VT_PTR;
1411 load(op->reg, &sv);
1412 } else if (i >= nb_outputs || op->is_rw) {
1413 /* load value in register */
1414 load(op->reg, op->vt);
1415 if (op->is_llong) {
1416 SValue sv;
1417 sv = *op->vt;
1418 sv.c.i += 4;
1419 load(TREG_XDX, &sv);
1420 }
1421 }
1422 }
1423 }
1424 } else {
1425 /* generate save code */
1426 for(i = 0 ; i < nb_outputs; i++) {
1427 op = &operands[i];
1428 if (op->reg >= 0) {
1429 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1430 if (!op->is_memory) {
1431 SValue sv;
1432 sv = *op->vt;
1433 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1434 load(out_reg, &sv);
1435
1436 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1437 store(op->reg, &sv);
1438 }
1439 } else {
1440 store(op->reg, op->vt);
1441 if (op->is_llong) {
1442 SValue sv;
1443 sv = *op->vt;
1444 sv.c.i += 4;
1445 store(TREG_XDX, &sv);
1446 }
1447 }
1448 }
1449 }
1450 /* generate reg restore code */
1451 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1452 reg = reg_saved[i];
1453 if (regs_allocated[reg]) {
1454 g(0x58 + reg);
1455 }
1456 }
1457 }
1458 }
1459
1460 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1461 {
1462 int reg;
1463 TokenSym *ts;
1464
1465 if (!strcmp(str, "memory") ||
1466 !strcmp(str, "cc"))
1467 return;
1468 ts = tok_alloc(str, strlen(str));
1469 reg = ts->tok;
1470 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1471 reg -= TOK_ASM_eax;
1472 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1473 reg -= TOK_ASM_ax;
1474 #ifdef TCC_TARGET_X86_64
1475 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1476 reg -= TOK_ASM_rax;
1477 #endif
1478 } else {
1479 tcc_error("invalid clobber register '%s'", str);
1480 }
1481 clobber_regs[reg] = 1;
1482 }
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