2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 /* #define NB_ASM_REGS 8 */
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30 #define TOK_ASM_alllast TOK_ASM_subps
32 #define OPC_B 0x01 /* only used with OPC_WL */
33 #define OPC_WL 0x02 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x04 /* register is added to opcode */
36 #define OPC_MODRM 0x08 /* modrm encoding */
38 #define OPCT_MASK 0x70
39 #define OPC_FWAIT 0x10 /* add fwait opcode */
40 #define OPC_SHIFT 0x20 /* shift opcodes */
41 #define OPC_ARITH 0x30 /* arithmetic opcodes */
42 #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
43 #define OPC_TEST 0x50 /* test opcodes */
44 #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
46 #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
47 #ifdef TCC_TARGET_X86_64
48 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
49 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
50 # define OPC_WLX OPC_WLQ
51 # define OPC_BWLX OPC_BWLQ
53 # define OPC_WLX OPC_WL
54 # define OPC_BWLX OPC_BWL
57 #define OPC_GROUP_SHIFT 13
59 /* in order to compress the operand type, we use specific operands and
62 OPT_REG8
=0, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_REG16
, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_REG32
, /* warning: value is hardcoded from TOK_ASM_xxx */
65 #ifdef TCC_TARGET_X86_64
66 OPT_REG64
, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_MMX
, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_SSE
, /* warning: value is hardcoded from TOK_ASM_xxx */
70 OPT_CR
, /* warning: value is hardcoded from TOK_ASM_xxx */
71 OPT_TR
, /* warning: value is hardcoded from TOK_ASM_xxx */
72 OPT_DB
, /* warning: value is hardcoded from TOK_ASM_xxx */
79 #ifdef TCC_TARGET_X86_64
82 OPT_EAX
, /* %al, %ax, %eax or %rax register */
83 OPT_ST0
, /* %st(0) register */
84 OPT_CL
, /* %cl register */
85 OPT_DX
, /* %dx register */
86 OPT_ADDR
, /* OP_EA with only offset */
87 OPT_INDIR
, /* *(expr) */
90 OPT_IM
, /* IM8 | IM16 | IM32 */
91 OPT_REG
, /* REG8 | REG16 | REG32 | REG64 */
92 OPT_REGW
, /* REG16 | REG32 | REG64 */
93 OPT_IMW
, /* IM16 | IM32 */
94 OPT_MMXSSE
, /* MMX | SSE */
95 OPT_DISP
, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
96 OPT_DISP8
, /* Like OPT_ADDR, but only 8bit (short jumps) */
97 /* can be ored with any OPT_xxx */
101 #define OP_REG8 (1 << OPT_REG8)
102 #define OP_REG16 (1 << OPT_REG16)
103 #define OP_REG32 (1 << OPT_REG32)
104 #define OP_MMX (1 << OPT_MMX)
105 #define OP_SSE (1 << OPT_SSE)
106 #define OP_CR (1 << OPT_CR)
107 #define OP_TR (1 << OPT_TR)
108 #define OP_DB (1 << OPT_DB)
109 #define OP_SEG (1 << OPT_SEG)
110 #define OP_ST (1 << OPT_ST)
111 #define OP_IM8 (1 << OPT_IM8)
112 #define OP_IM8S (1 << OPT_IM8S)
113 #define OP_IM16 (1 << OPT_IM16)
114 #define OP_IM32 (1 << OPT_IM32)
115 #define OP_EAX (1 << OPT_EAX)
116 #define OP_ST0 (1 << OPT_ST0)
117 #define OP_CL (1 << OPT_CL)
118 #define OP_DX (1 << OPT_DX)
119 #define OP_ADDR (1 << OPT_ADDR)
120 #define OP_INDIR (1 << OPT_INDIR)
121 #ifdef TCC_TARGET_X86_64
122 # define OP_REG64 (1 << OPT_REG64)
123 # define OP_IM64 (1 << OPT_IM64)
124 # define OP_EA32 (OP_EA << 1)
131 #define OP_EA 0x40000000
132 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
134 #ifdef TCC_TARGET_X86_64
135 # define TREG_XAX TREG_RAX
136 # define TREG_XCX TREG_RCX
137 # define TREG_XDX TREG_RDX
139 # define TREG_XAX TREG_EAX
140 # define TREG_XCX TREG_ECX
141 # define TREG_XDX TREG_EDX
144 typedef struct ASMInstr
{
149 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
152 typedef struct Operand
{
154 int8_t reg
; /* register, -1 if none */
155 int8_t reg2
; /* second register, -1 if none */
160 static const uint8_t reg_to_size
[9] = {
165 #ifdef TCC_TARGET_X86_64
169 0, 0, 1, 0, 2, 0, 0, 0, 3
172 #define NB_TEST_OPCODES 30
174 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
207 static const uint8_t segment_prefixes
[] = {
216 static const ASMInstr asm_instrs
[] = {
218 /* This removes a 0x0f in the second byte */
219 #define O(o) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o))
220 /* This constructs instr_type from opcode, type and group. */
221 #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
222 #define DEF_ASM_OP0(name, opcode)
223 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0 },
224 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
225 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
226 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
227 #ifdef TCC_TARGET_X86_64
228 # include "x86_64-asm.h"
230 # include "i386-asm.h"
236 static const uint16_t op0_codes
[] = {
238 #define DEF_ASM_OP0(x, opcode) opcode,
239 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
240 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
241 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
242 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
243 #ifdef TCC_TARGET_X86_64
244 # include "x86_64-asm.h"
246 # include "i386-asm.h"
250 static inline int get_reg_shift(TCCState
*s1
)
253 v
= asm_int_expr(s1
);
268 expect("1, 2, 4 or 8 constant");
275 static int asm_parse_reg(int *type
)
282 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
283 reg
= tok
- TOK_ASM_eax
;
284 #ifdef TCC_TARGET_X86_64
286 } else if (tok
>= TOK_ASM_rax
&& tok
<= TOK_ASM_rdi
) {
287 reg
= tok
- TOK_ASM_rax
;
288 } else if (tok
== TOK_ASM_rip
) {
299 static void parse_operand(TCCState
*s1
, Operand
*op
)
313 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
314 reg
= tok
- TOK_ASM_al
;
315 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
317 if ((op
->type
& OP_REG
) && op
->reg
== TREG_XAX
)
319 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_XCX
)
321 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_XDX
)
323 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
325 op
->reg
= tok
- TOK_ASM_dr0
;
326 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
328 op
->reg
= tok
- TOK_ASM_es
;
329 } else if (tok
== TOK_ASM_st
) {
335 if (tok
!= TOK_PPNUM
)
339 if ((unsigned)reg
>= 8 || p
[1] != '\0')
350 tcc_error("unknown register");
354 } else if (tok
== '$') {
362 if (op
->e
.v
== (uint8_t)op
->e
.v
)
364 if (op
->e
.v
== (int8_t)op
->e
.v
)
366 if (op
->e
.v
== (uint16_t)op
->e
.v
)
368 #ifdef TCC_TARGET_X86_64
369 if (op
->e
.v
!= (int32_t)op
->e
.v
)
374 /* address(reg,reg2,shift) with all variants */
390 /* bracketed offset expression */
403 op
->reg
= asm_parse_reg(&type
);
408 op
->reg2
= asm_parse_reg(&type
);
412 op
->shift
= get_reg_shift(s1
);
419 if (op
->reg
== -1 && op
->reg2
== -1)
425 /* XXX: unify with C code output ? */
426 ST_FUNC
void gen_expr32(ExprValue
*pe
)
428 gen_addr32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
431 #ifdef TCC_TARGET_X86_64
432 static void gen_expr64(ExprValue
*pe
)
434 gen_addr64(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
438 /* XXX: unify with C code output ? */
439 static void gen_disp32(ExprValue
*pe
)
442 if (sym
&& sym
->r
== cur_text_section
->sh_num
) {
443 /* same section: we can output an absolute value. Note
444 that the TCC compiler behaves differently here because
445 it always outputs a relocation to ease (future) code
446 elimination in the linker */
447 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
449 if (sym
&& sym
->type
.t
== VT_VOID
) {
450 sym
->type
.t
= VT_FUNC
;
451 sym
->type
.ref
= NULL
;
453 gen_addrpc32(VT_SYM
, sym
, pe
->v
);
457 /* generate the modrm operand */
458 static inline int asm_modrm(int reg
, Operand
*op
)
460 int mod
, reg1
, reg2
, sib_reg1
;
462 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
463 g(0xc0 + (reg
<< 3) + op
->reg
);
464 } else if (op
->reg
== -1 && op
->reg2
== -1) {
465 /* displacement only */
466 #ifdef TCC_TARGET_X86_64
467 g(0x04 + (reg
<< 3));
470 g(0x05 + (reg
<< 3));
473 #ifdef TCC_TARGET_X86_64
474 } else if (op
->reg
== 8) {
475 ExprValue
*pe
= &op
->e
;
476 g(0x05 + (reg
<< 3));
477 gen_addrpc32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
482 /* fist compute displacement encoding */
483 if (sib_reg1
== -1) {
486 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
488 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
493 /* compute if sib byte needed */
497 g(mod
+ (reg
<< 3) + reg1
);
502 reg2
= 4; /* indicate no index */
503 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
508 } else if (mod
== 0x80 || op
->reg
== -1) {
515 static void maybe_print_stats (void)
517 static int already
= 1;
519 /* print stats about opcodes */
521 const struct ASMInstr
*pa
;
524 int nb_op_vals
, i
, j
;
528 memset(freq
, 0, sizeof(freq
));
529 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
531 //for(i=0;i<pa->nb_ops;i++) {
532 for(j
=0;j
<nb_op_vals
;j
++) {
533 //if (pa->op_type[i] == op_vals[j])
534 if (pa
->instr_type
== op_vals
[j
])
537 //op_vals[nb_op_vals++] = pa->op_type[i];
538 op_vals
[nb_op_vals
++] = pa
->instr_type
;
542 for(i
=0;i
<nb_op_vals
;i
++) {
544 //if ((v & (v - 1)) != 0)
545 printf("%3d: %08x\n", i
, v
);
547 printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
548 (int)sizeof(asm_instrs
),
549 (int)sizeof(asm_instrs
) / (int)sizeof(ASMInstr
),
550 freq
[0], freq
[1], freq
[2], freq
[3]);
554 ST_FUNC
void asm_opcode(TCCState
*s1
, int opcode
)
557 int i
, modrm_index
, reg
, v
, op1
, seg_prefix
, pc
;
559 Operand ops
[MAX_OPERANDS
], *pop
;
560 int op_type
[3]; /* decoded op type */
561 int alltypes
; /* OR of all operand types */
566 /* force synthetic ';' after prefix instruction, so we can handle */
567 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
568 if (opcode
>= TOK_ASM_wait
&& opcode
<= TOK_ASM_repnz
)
577 if (tok
== ';' || tok
== TOK_LINEFEED
)
579 if (nb_ops
>= MAX_OPERANDS
) {
580 tcc_error("incorrect number of operands");
582 parse_operand(s1
, pop
);
584 if (pop
->type
!= OP_SEG
|| seg_prefix
)
585 tcc_error("incorrect prefix");
586 seg_prefix
= segment_prefixes
[pop
->reg
];
588 parse_operand(s1
, pop
);
589 if (!(pop
->type
& OP_EA
)) {
590 tcc_error("segment prefix must be followed by memory reference");
600 s
= 0; /* avoid warning */
602 /* optimize matching by using a lookup table (no hashing is needed
604 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
605 int it
= pa
->instr_type
& OPCT_MASK
;
607 if (it
== OPC_FARITH
) {
608 v
= opcode
- pa
->sym
;
609 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
611 } else if (it
== OPC_ARITH
) {
612 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8*NBWLX
))
614 s
= (opcode
- pa
->sym
) % NBWLX
;
615 if ((pa
->instr_type
& OPC_BWLX
) == OPC_WLX
)
617 /* We need to reject the xxxb opcodes that we accepted above.
618 Note that pa->sym for WLX opcodes is the 'w' token,
619 to get the 'b' token subtract one. */
620 if (((opcode
- pa
->sym
+ 1) % NBWLX
) == 0)
624 } else if (it
== OPC_SHIFT
) {
625 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7*NBWLX
))
627 s
= (opcode
- pa
->sym
) % NBWLX
;
628 } else if (it
== OPC_TEST
) {
629 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
631 /* cmovxx is a test opcode but accepts multiple sizes.
632 TCC doesn't accept the suffixed mnemonic, instead we
633 simply force size autodetection always. */
634 if (pa
->instr_type
& OPC_WLX
)
636 } else if (pa
->instr_type
& OPC_B
) {
637 #ifdef TCC_TARGET_X86_64
638 /* Some instructions don't have the full size but only
639 bwl form. insb e.g. */
640 if ((pa
->instr_type
& OPC_WLQ
) != OPC_WLQ
641 && !(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
644 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
))
646 s
= opcode
- pa
->sym
;
647 } else if (pa
->instr_type
& OPC_WLX
) {
648 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
650 s
= opcode
- pa
->sym
+ 1;
652 if (pa
->sym
!= opcode
)
655 if (pa
->nb_ops
!= nb_ops
)
657 #ifdef TCC_TARGET_X86_64
658 /* Special case for moves. Selecting the IM64->REG64 form
659 should only be done if we really have an >32bit imm64, and that
660 is hardcoded. Ignore it here. */
661 if (pa
->opcode
== 0xb0 && ops
[0].type
!= OP_IM64
662 && ops
[1].type
== OP_REG64
663 && !(pa
->instr_type
& OPC_0F
))
666 /* now decode and check each operand */
668 for(i
= 0; i
< nb_ops
; i
++) {
670 op1
= pa
->op_type
[i
];
674 v
= OP_IM8
| OP_IM16
| OP_IM32
;
677 v
= OP_REG8
| OP_REG16
| OP_REG32
| OP_REG64
;
680 v
= OP_REG16
| OP_REG32
| OP_REG64
;
683 v
= OP_IM16
| OP_IM32
;
699 if ((ops
[i
].type
& v
) == 0)
701 alltypes
|= ops
[i
].type
;
703 /* all is matching ! */
708 if (opcode
>= TOK_ASM_first
&& opcode
<= TOK_ASM_last
) {
710 b
= op0_codes
[opcode
- TOK_ASM_first
];
715 } else if (opcode
<= TOK_ASM_alllast
) {
716 tcc_error("bad operand with opcode '%s'",
717 get_tok_str(opcode
, NULL
));
719 tcc_error("unknown opcode '%s'",
720 get_tok_str(opcode
, NULL
));
723 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
725 #ifdef TCC_TARGET_X86_64
726 /* XXX the autosize should rather be zero, to not have to adjust this
728 if ((pa
->instr_type
& OPC_BWLQ
) == OPC_B
)
732 for(i
= 0; s
== autosize
&& i
< nb_ops
; i
++) {
733 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
734 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
737 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
738 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
)))
741 tcc_error("cannot infer opcode suffix");
745 #ifdef TCC_TARGET_X86_64
746 /* Generate addr32 prefix if needed */
747 for(i
= 0; i
< nb_ops
; i
++) {
748 if (ops
[i
].type
& OP_EA32
) {
754 /* generate data16 prefix if needed */
759 /* accepting mmx+sse in all operands --> needs 0x66 to
760 switch to sse mode. Accepting only sse in an operand --> is
761 already SSE insn and needs 0x66/f2/f3 handling. */
762 for (i
= 0; i
< nb_ops
; i
++)
763 if ((op_type
[i
] & (OP_MMX
| OP_SSE
)) == (OP_MMX
| OP_SSE
)
764 && ops
[i
].type
& OP_SSE
)
769 #ifdef TCC_TARGET_X86_64
770 if (s
== 3 || (alltypes
& OP_REG64
)) {
771 /* generate REX prefix */
773 for(i
= 0; i
< nb_ops
; i
++) {
774 if (op_type
[i
] == OP_REG64
) {
775 /* If only 64bit regs are accepted in one operand
776 this is a default64 instruction without need for
782 /* XXX find better encoding for the default64 instructions. */
783 if (((opcode
!= TOK_ASM_push
&& opcode
!= TOK_ASM_pop
784 && opcode
!= TOK_ASM_pushw
&& opcode
!= TOK_ASM_pushl
785 && opcode
!= TOK_ASM_pushq
&& opcode
!= TOK_ASM_popw
786 && opcode
!= TOK_ASM_popl
&& opcode
!= TOK_ASM_popq
787 && opcode
!= TOK_ASM_call
&& opcode
!= TOK_ASM_jmp
))
793 /* now generates the operation */
794 if (OPCT_IS(pa
->instr_type
, OPC_FWAIT
))
800 if (pa
->instr_type
& OPC_0F
)
801 v
= ((v
& ~0xff) << 8) | 0x0f00 | (v
& 0xff);
802 if ((v
== 0x69 || v
== 0x6b) && nb_ops
== 2) {
803 /* kludge for imul $im, %reg */
806 op_type
[2] = op_type
[1];
807 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
808 v
--; /* int $3 case */
810 } else if ((v
== 0x06 || v
== 0x07)) {
811 if (ops
[0].reg
>= 4) {
812 /* push/pop %fs or %gs */
813 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
815 v
+= ops
[0].reg
<< 3;
818 } else if (v
<= 0x05) {
820 v
+= ((opcode
- TOK_ASM_addb
) / NBWLX
) << 3;
821 } else if ((pa
->instr_type
& (OPCT_MASK
| OPC_MODRM
)) == OPC_FARITH
) {
823 v
+= ((opcode
- pa
->sym
) / 6) << 3;
825 if (pa
->instr_type
& OPC_REG
) {
826 /* mov $im, %reg case */
827 if (v
== 0xb0 && s
>= 1)
829 for(i
= 0; i
< nb_ops
; i
++) {
830 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
836 if (pa
->instr_type
& OPC_B
)
838 if (nb_ops
== 1 && pa
->op_type
[0] == OPT_DISP8
) {
842 /* see if we can really generate the jump with a byte offset */
846 if (sym
->r
!= cur_text_section
->sh_num
)
848 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2 - (v
>= 0xff);
849 if (jmp_disp
== (int8_t)jmp_disp
) {
850 /* OK to generate jump */
852 ops
[0].e
.v
= jmp_disp
;
853 op_type
[0] = OP_IM8S
;
856 /* long jump will be allowed. need to modify the
858 if (v
== 0xeb) /* jmp */
860 else if (v
== 0x70) /* jcc */
863 tcc_error("invalid displacement");
866 if (OPCT_IS(pa
->instr_type
, OPC_TEST
))
867 v
+= test_bits
[opcode
- pa
->sym
];
871 op1
= (v
>> 8) & 0xff;
876 /* search which operand will used for modrm */
878 if (OPCT_IS(pa
->instr_type
, OPC_SHIFT
)) {
879 reg
= (opcode
- pa
->sym
) / NBWLX
;
882 } else if (OPCT_IS(pa
->instr_type
, OPC_ARITH
)) {
883 reg
= (opcode
- pa
->sym
) / NBWLX
;
884 } else if (OPCT_IS(pa
->instr_type
, OPC_FARITH
)) {
885 reg
= (opcode
- pa
->sym
) / 6;
887 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
891 if (pa
->instr_type
& OPC_MODRM
) {
892 /* first look for an ea operand */
893 for(i
= 0;i
< nb_ops
; i
++) {
894 if (op_type
[i
] & OP_EA
)
897 /* then if not found, a register or indirection (shift instructions) */
898 for(i
= 0;i
< nb_ops
; i
++) {
899 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
903 tcc_error("bad op table");
907 /* if a register is used in another operand then it is
908 used instead of group */
909 for(i
= 0;i
< nb_ops
; i
++) {
911 if (i
!= modrm_index
&&
912 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
917 pc
= asm_modrm(reg
, &ops
[modrm_index
]);
921 #ifndef TCC_TARGET_X86_64
922 if (!(pa
->instr_type
& OPC_0F
)
923 && (pa
->opcode
== 0x9a || pa
->opcode
== 0xea)) {
924 /* ljmp or lcall kludge */
925 gen_expr32(&ops
[1].e
);
927 tcc_error("cannot relocate");
928 gen_le16(ops
[0].e
.v
);
932 for(i
= 0;i
< nb_ops
; i
++) {
934 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
| OP_IM8S
| OP_ADDR
)) {
935 /* if multiple sizes are given it means we must look
937 if ((v
| OP_IM8
| OP_IM64
) == (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
)) {
942 else if (s
== 2 || (v
& OP_IM64
) == 0)
948 if ((v
& (OP_IM8
| OP_IM8S
| OP_IM16
)) && ops
[i
].e
.sym
)
949 tcc_error("cannot relocate");
951 if (v
& (OP_IM8
| OP_IM8S
)) {
953 } else if (v
& OP_IM16
) {
954 gen_le16(ops
[i
].e
.v
);
955 #ifdef TCC_TARGET_X86_64
956 } else if (v
& OP_IM64
) {
957 gen_expr64(&ops
[i
].e
);
959 } else if (pa
->op_type
[i
] == OPT_DISP
|| pa
->op_type
[i
] == OPT_DISP8
) {
960 gen_disp32(&ops
[i
].e
);
962 gen_expr32(&ops
[i
].e
);
967 /* after immediate operands, adjust pc-relative address */
969 add32le(text_section
->data
+ pc
- 4, pc
- ind
);
972 /* return the constraint priority (we allocate first the lowest
973 numbered constraints) */
974 static inline int constraint_priority(const char *str
)
978 /* we take the lowest priority */
1012 tcc_error("unknown constraint '%c'", c
);
1021 static const char *skip_constraint_modifiers(const char *p
)
1023 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1028 #define REG_OUT_MASK 0x01
1029 #define REG_IN_MASK 0x02
1031 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1033 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
,
1034 int nb_operands
, int nb_outputs
,
1035 const uint8_t *clobber_regs
,
1039 int sorted_op
[MAX_ASM_OPERANDS
];
1040 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1042 uint8_t regs_allocated
[NB_ASM_REGS
];
1045 for(i
=0;i
<nb_operands
;i
++) {
1047 op
->input_index
= -1;
1053 /* compute constraint priority and evaluate references to output
1054 constraints if input constraints */
1055 for(i
=0;i
<nb_operands
;i
++) {
1057 str
= op
->constraint
;
1058 str
= skip_constraint_modifiers(str
);
1059 if (isnum(*str
) || *str
== '[') {
1060 /* this is a reference to another constraint */
1061 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1062 if ((unsigned)k
>= i
|| i
< nb_outputs
)
1063 tcc_error("invalid reference in constraint %d ('%s')",
1066 if (operands
[k
].input_index
>= 0)
1067 tcc_error("cannot reference twice the same operand");
1068 operands
[k
].input_index
= i
;
1071 op
->priority
= constraint_priority(str
);
1075 /* sort operands according to their priority */
1076 for(i
=0;i
<nb_operands
;i
++)
1078 for(i
=0;i
<nb_operands
- 1;i
++) {
1079 for(j
=i
+1;j
<nb_operands
;j
++) {
1080 p1
= operands
[sorted_op
[i
]].priority
;
1081 p2
= operands
[sorted_op
[j
]].priority
;
1084 sorted_op
[i
] = sorted_op
[j
];
1090 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
1091 if (clobber_regs
[i
])
1092 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1094 regs_allocated
[i
] = 0;
1096 /* esp cannot be used */
1097 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
1098 /* ebp cannot be used yet */
1099 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1101 /* allocate registers and generate corresponding asm moves */
1102 for(i
=0;i
<nb_operands
;i
++) {
1105 str
= op
->constraint
;
1106 /* no need to allocate references */
1107 if (op
->ref_index
>= 0)
1109 /* select if register is used for output, input or both */
1110 if (op
->input_index
>= 0) {
1111 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1112 } else if (j
< nb_outputs
) {
1113 reg_mask
= REG_OUT_MASK
;
1115 reg_mask
= REG_IN_MASK
;
1126 if (j
>= nb_outputs
)
1127 tcc_error("'%c' modifier can only be applied to outputs", c
);
1128 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1131 /* allocate both eax and edx */
1132 if (is_reg_allocated(TREG_XAX
) ||
1133 is_reg_allocated(TREG_XDX
))
1137 regs_allocated
[TREG_XAX
] |= reg_mask
;
1138 regs_allocated
[TREG_XDX
] |= reg_mask
;
1158 if (is_reg_allocated(reg
))
1162 /* eax, ebx, ecx or edx */
1163 for(reg
= 0; reg
< 4; reg
++) {
1164 if (!is_reg_allocated(reg
))
1169 /* any general register */
1170 for(reg
= 0; reg
< 8; reg
++) {
1171 if (!is_reg_allocated(reg
))
1176 /* now we can reload in the register */
1179 regs_allocated
[reg
] |= reg_mask
;
1182 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1188 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1193 /* nothing special to do because the operand is already in
1194 memory, except if the pointer itself is stored in a
1195 memory variable (VT_LLOCAL case) */
1196 /* XXX: fix constant case */
1197 /* if it is a reference to a memory zone, it must lie
1198 in a register, so we reserve the register in the
1199 input registers and a load will be generated
1201 if (j
< nb_outputs
|| c
== 'm') {
1202 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1203 /* any general register */
1204 for(reg
= 0; reg
< 8; reg
++) {
1205 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1210 /* now we can reload in the register */
1211 regs_allocated
[reg
] |= REG_IN_MASK
;
1218 tcc_error("asm constraint %d ('%s') could not be satisfied",
1222 /* if a reference is present for that operand, we assign it too */
1223 if (op
->input_index
>= 0) {
1224 operands
[op
->input_index
].reg
= op
->reg
;
1225 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1229 /* compute out_reg. It is used to store outputs registers to memory
1230 locations references by pointers (VT_LLOCAL case) */
1232 for(i
=0;i
<nb_operands
;i
++) {
1235 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1237 for(reg
= 0; reg
< 8; reg
++) {
1238 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1241 tcc_error("could not find free output register for reloading");
1248 /* print sorted constraints */
1250 for(i
=0;i
<nb_operands
;i
++) {
1253 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1255 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1261 printf("out_reg=%d\n", *pout_reg
);
1265 ST_FUNC
void subst_asm_operand(CString
*add_str
,
1266 SValue
*sv
, int modifier
)
1268 int r
, reg
, size
, val
;
1272 if ((r
& VT_VALMASK
) == VT_CONST
) {
1273 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n')
1274 cstr_ccat(add_str
, '$');
1276 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
), -1);
1277 if ((uint32_t)sv
->c
.i
== 0)
1279 cstr_ccat(add_str
, '+');
1282 if (modifier
== 'n')
1284 snprintf(buf
, sizeof(buf
), "%d", (int)sv
->c
.i
);
1285 cstr_cat(add_str
, buf
, -1);
1287 #ifdef TCC_TARGET_X86_64
1289 cstr_cat(add_str
, "(%rip)", -1);
1291 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1292 #ifdef TCC_TARGET_X86_64
1293 snprintf(buf
, sizeof(buf
), "%d(%%rbp)", (int)sv
->c
.i
);
1295 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", (int)sv
->c
.i
);
1297 cstr_cat(add_str
, buf
, -1);
1298 } else if (r
& VT_LVAL
) {
1299 reg
= r
& VT_VALMASK
;
1300 if (reg
>= VT_CONST
)
1301 tcc_error("internal compiler error");
1302 snprintf(buf
, sizeof(buf
), "(%%%s)",
1303 #ifdef TCC_TARGET_X86_64
1304 get_tok_str(TOK_ASM_rax
+ reg
, NULL
)
1306 get_tok_str(TOK_ASM_eax
+ reg
, NULL
)
1309 cstr_cat(add_str
, buf
, -1);
1312 reg
= r
& VT_VALMASK
;
1313 if (reg
>= VT_CONST
)
1314 tcc_error("internal compiler error");
1316 /* choose register operand size */
1317 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1319 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1321 #ifdef TCC_TARGET_X86_64
1322 else if ((sv
->type
.t
& VT_BTYPE
) == VT_LLONG
)
1327 if (size
== 1 && reg
>= 4)
1330 if (modifier
== 'b') {
1332 tcc_error("cannot use byte register");
1334 } else if (modifier
== 'h') {
1336 tcc_error("cannot use byte register");
1338 } else if (modifier
== 'w') {
1340 } else if (modifier
== 'k') {
1342 #ifdef TCC_TARGET_X86_64
1343 } else if (modifier
== 'q') {
1350 reg
= TOK_ASM_ah
+ reg
;
1353 reg
= TOK_ASM_al
+ reg
;
1356 reg
= TOK_ASM_ax
+ reg
;
1359 reg
= TOK_ASM_eax
+ reg
;
1361 #ifdef TCC_TARGET_X86_64
1363 reg
= TOK_ASM_rax
+ reg
;
1367 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1368 cstr_cat(add_str
, buf
, -1);
1372 /* generate prolog and epilog code for asm statement */
1373 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1374 int nb_outputs
, int is_output
,
1375 uint8_t *clobber_regs
,
1378 uint8_t regs_allocated
[NB_ASM_REGS
];
1381 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1383 /* mark all used registers */
1384 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1385 for(i
= 0; i
< nb_operands
;i
++) {
1388 regs_allocated
[op
->reg
] = 1;
1391 /* generate reg save code */
1392 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1394 if (regs_allocated
[reg
]) {
1399 /* generate load code */
1400 for(i
= 0; i
< nb_operands
; i
++) {
1403 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1405 /* memory reference case (for both input and
1409 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
| VT_LVAL
;
1412 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1413 /* load value in register */
1414 load(op
->reg
, op
->vt
);
1419 load(TREG_XDX
, &sv
);
1425 /* generate save code */
1426 for(i
= 0 ; i
< nb_outputs
; i
++) {
1429 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1430 if (!op
->is_memory
) {
1433 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1436 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1437 store(op
->reg
, &sv
);
1440 store(op
->reg
, op
->vt
);
1445 store(TREG_XDX
, &sv
);
1450 /* generate reg restore code */
1451 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1453 if (regs_allocated
[reg
]) {
1460 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1465 if (!strcmp(str
, "memory") ||
1468 ts
= tok_alloc(str
, strlen(str
));
1470 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1472 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1474 #ifdef TCC_TARGET_X86_64
1475 } else if (reg
>= TOK_ASM_rax
&& reg
<= TOK_ASM_rdi
) {
1479 tcc_error("invalid clobber register '%s'", str
);
1481 clobber_regs
[reg
] = 1;